7 config RWSEM_GENERIC_SPINLOCK
10 config RWSEM_XCHGADD_ALGORITHM
16 select HAVE_ARCH_TRACEHOOK
17 select HAVE_DYNAMIC_FTRACE
18 select HAVE_FTRACE_MCOUNT_RECORD
19 select HAVE_FUNCTION_GRAPH_TRACER
20 select HAVE_FUNCTION_TRACER
21 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
23 select HAVE_KERNEL_GZIP if RAMKERNEL
24 select HAVE_KERNEL_BZIP2 if RAMKERNEL
25 select HAVE_KERNEL_LZMA if RAMKERNEL
26 select HAVE_KERNEL_LZO if RAMKERNEL
28 select HAVE_PERF_EVENTS
29 select ARCH_HAVE_CUSTOM_GPIO_H
30 select ARCH_REQUIRE_GPIOLIB
32 select HAVE_UNDERSCORE_SYMBOL_PREFIX
34 select ARCH_WANT_IPC_PARSE_VERSION
35 select HAVE_GENERIC_HARDIRQS
36 select GENERIC_ATOMIC64
37 select GENERIC_IRQ_PROBE
38 select USE_GENERIC_SMP_HELPERS if SMP
39 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
40 select GENERIC_SMP_IDLE_THREAD
41 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
42 select HAVE_MOD_ARCH_SPECIFIC
43 select MODULES_USE_ELF_RELA
44 select HAVE_DEBUG_STACKOVERFLOW
56 config FORCE_MAX_ZONEORDER
60 config GENERIC_CALIBRATE_DELAY
63 config LOCKDEP_SUPPORT
66 config STACKTRACE_SUPPORT
69 config TRACE_IRQFLAGS_SUPPORT
74 source "kernel/Kconfig.preempt"
76 source "kernel/Kconfig.freezer"
78 menu "Blackfin Processor Options"
80 comment "Processor and Board Settings"
89 BF512 Processor Support.
94 BF514 Processor Support.
99 BF516 Processor Support.
104 BF518 Processor Support.
109 BF522 Processor Support.
114 BF523 Processor Support.
119 BF524 Processor Support.
124 BF525 Processor Support.
129 BF526 Processor Support.
134 BF527 Processor Support.
139 BF531 Processor Support.
144 BF532 Processor Support.
149 BF533 Processor Support.
154 BF534 Processor Support.
159 BF536 Processor Support.
164 BF537 Processor Support.
169 BF538 Processor Support.
174 BF539 Processor Support.
179 BF542 Processor Support.
184 BF542 Processor Support.
189 BF544 Processor Support.
194 BF544 Processor Support.
199 BF547 Processor Support.
204 BF547 Processor Support.
209 BF548 Processor Support.
214 BF548 Processor Support.
219 BF549 Processor Support.
224 BF549 Processor Support.
229 BF561 Processor Support.
235 BF609 Processor Support.
241 select TICKSOURCE_CORETMR
242 bool "Symmetric multi-processing support"
244 This enables support for systems with more than one CPU,
245 like the dual core BF561. If you have a system with only one
246 CPU, say N. If you have a system with more than one CPU, say Y.
248 If you don't know what to do here, say N.
256 bool "Support for hot-pluggable CPUs"
262 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
263 default 2 if (BF537 || BF536 || BF534)
264 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
265 default 4 if (BF538 || BF539)
269 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
270 default 3 if (BF537 || BF536 || BF534 || BF54xM)
271 default 5 if (BF561 || BF538 || BF539)
272 default 6 if (BF533 || BF532 || BF531)
276 default BF_REV_0_0 if (BF51x || BF52x || BF60x)
277 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
278 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
282 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
286 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
290 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
294 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
298 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
302 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
306 depends on (BF533 || BF532 || BF531)
318 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
321 config MEM_MT48LC64M4A2FB_7E
323 depends on (BFIN533_STAMP)
326 config MEM_MT48LC16M16A2TG_75
328 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
329 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
330 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
331 || BFIN527_BLUETECHNIX_CM)
334 config MEM_MT48LC32M8A2_75
336 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
339 config MEM_MT48LC8M32B2B5_7
341 depends on (BFIN561_BLUETECHNIX_CM)
344 config MEM_MT48LC32M16A2TG_75
346 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
349 config MEM_MT48H32M16LFCJ_75
351 depends on (BFIN526_EZBRD)
354 config MEM_MT47H64M16
356 depends on (BFIN609_EZKIT)
359 source "arch/blackfin/mach-bf518/Kconfig"
360 source "arch/blackfin/mach-bf527/Kconfig"
361 source "arch/blackfin/mach-bf533/Kconfig"
362 source "arch/blackfin/mach-bf561/Kconfig"
363 source "arch/blackfin/mach-bf537/Kconfig"
364 source "arch/blackfin/mach-bf538/Kconfig"
365 source "arch/blackfin/mach-bf548/Kconfig"
366 source "arch/blackfin/mach-bf609/Kconfig"
368 menu "Board customizations"
371 bool "Default bootloader kernel arguments"
374 string "Initial kernel command string"
375 depends on CMDLINE_BOOL
376 default "console=ttyBF0,57600"
378 If you don't have a boot loader capable of passing a command line string
379 to the kernel, you may specify one here. As a minimum, you should specify
380 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
383 hex "Kernel load address for booting"
385 range 0x1000 0x20000000
387 This option allows you to set the load address of the kernel.
388 This can be useful if you are on a board which has a small amount
389 of memory or you wish to reserve some memory at the beginning of
392 Note that you need to keep this value above 4k (0x1000) as this
393 memory region is used to capture NULL pointer references as well
394 as some core kernel functions.
396 config PHY_RAM_BASE_ADDRESS
397 hex "Physical RAM Base"
400 set BF609 FPGA physical SRAM base address
403 hex "Kernel ROM Base"
406 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
407 range 0x20000000 0x30000000 if (BF54x || BF561)
408 range 0xB0000000 0xC0000000 if (BF60x)
410 Make sure your ROM base does not include any file-header
411 information that is prepended to the kernel.
413 For example, the bootable U-Boot format (created with
414 mkimage) has a 64 byte header (0x40). So while the image
415 you write to flash might start at say 0x20080000, you have
416 to add 0x40 to get the kernel's ROM base as it will come
419 comment "Clock/PLL Setup"
422 int "Frequency of the crystal on the board in Hz"
423 default "10000000" if BFIN532_IP0X
424 default "11059200" if BFIN533_STAMP
425 default "24576000" if PNAV10
426 default "25000000" # most people use this
427 default "27000000" if BFIN533_EZKIT
428 default "30000000" if BFIN561_EZKIT
429 default "24000000" if BFIN527_AD7160EVAL
431 The frequency of CLKIN crystal oscillator on the board in Hz.
432 Warning: This value should match the crystal on the board. Otherwise,
433 peripherals won't work properly.
435 config BFIN_KERNEL_CLOCK
436 bool "Re-program Clocks while Kernel boots?"
439 This option decides if kernel clocks are re-programed from the
440 bootloader settings. If the clocks are not set, the SDRAM settings
441 are also not changed, and the Bootloader does 100% of the hardware
446 depends on BFIN_KERNEL_CLOCK && (!BF60x)
451 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
454 If this is set the clock will be divided by 2, before it goes to the PLL.
458 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
460 default "22" if BFIN533_EZKIT
461 default "45" if BFIN533_STAMP
462 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
463 default "22" if BFIN533_BLUETECHNIX_CM
464 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
465 default "20" if (BFIN561_EZKIT || BF609)
466 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
467 default "25" if BFIN527_AD7160EVAL
469 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
470 PLL Frequency = (Crystal Frequency) * (this setting)
473 prompt "Core Clock Divider"
474 depends on BFIN_KERNEL_CLOCK
477 This sets the frequency of the core. It can be 1, 2, 4 or 8
478 Core Frequency = (PLL frequency) / (this setting)
494 int "System Clock Divider"
495 depends on BFIN_KERNEL_CLOCK
499 This sets the frequency of the system clock (including SDRAM or DDR) on
500 !BF60x else it set the clock for system buses and provides the
501 source from which SCLK0 and SCLK1 are derived.
502 This can be between 1 and 15
503 System Clock = (PLL frequency) / (this setting)
506 int "System Clock0 Divider"
507 depends on BFIN_KERNEL_CLOCK && BF60x
511 This sets the frequency of the system clock0 for PVP and all other
512 peripherals not clocked by SCLK1.
513 This can be between 1 and 15
514 System Clock0 = (System Clock) / (this setting)
517 int "System Clock1 Divider"
518 depends on BFIN_KERNEL_CLOCK && BF60x
522 This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
523 This can be between 1 and 15
524 System Clock1 = (System Clock) / (this setting)
527 int "DDR Clock Divider"
528 depends on BFIN_KERNEL_CLOCK && BF60x
532 This sets the frequency of the DDR memory.
533 This can be between 1 and 15
534 DDR Clock = (PLL frequency) / (this setting)
537 prompt "DDR SDRAM Chip Type"
538 depends on BFIN_KERNEL_CLOCK
540 default MEM_MT46V32M16_5B
542 config MEM_MT46V32M16_6T
545 config MEM_MT46V32M16_5B
550 prompt "DDR/SDRAM Timing"
551 depends on BFIN_KERNEL_CLOCK && !BF60x
552 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
554 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
555 The calculated SDRAM timing parameters may not be 100%
556 accurate - This option is therefore marked experimental.
558 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
559 bool "Calculate Timings"
561 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
562 bool "Provide accurate Timings based on target SCLK"
564 Please consult the Blackfin Hardware Reference Manuals as well
565 as the memory device datasheet.
566 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
569 menu "Memory Init Control"
570 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
587 config MEM_EBIU_DDRQUE
604 # Max & Min Speeds for various Chips
608 default 400000000 if BF512
609 default 400000000 if BF514
610 default 400000000 if BF516
611 default 400000000 if BF518
612 default 400000000 if BF522
613 default 600000000 if BF523
614 default 400000000 if BF524
615 default 600000000 if BF525
616 default 400000000 if BF526
617 default 600000000 if BF527
618 default 400000000 if BF531
619 default 400000000 if BF532
620 default 750000000 if BF533
621 default 500000000 if BF534
622 default 400000000 if BF536
623 default 600000000 if BF537
624 default 533333333 if BF538
625 default 533333333 if BF539
626 default 600000000 if BF542
627 default 533333333 if BF544
628 default 600000000 if BF547
629 default 600000000 if BF548
630 default 533333333 if BF549
631 default 600000000 if BF561
632 default 800000000 if BF609
640 default 200000000 if BF609
647 comment "Kernel Timer/Scheduler"
649 source kernel/Kconfig.hz
651 config SET_GENERIC_CLOCKEVENTS
652 bool "Generic clock events"
654 select GENERIC_CLOCKEVENTS
656 menu "Clock event device"
657 depends on GENERIC_CLOCKEVENTS
658 config TICKSOURCE_GPTMR0
663 config TICKSOURCE_CORETMR
669 depends on GENERIC_CLOCKEVENTS
670 config CYCLES_CLOCKSOURCE
673 depends on !BFIN_SCRATCH_REG_CYCLES
676 If you say Y here, you will enable support for using the 'cycles'
677 registers as a clock source. Doing so means you will be unable to
678 safely write to the 'cycles' register during runtime. You will
679 still be able to read it (such as for performance monitoring), but
680 writing the registers will most likely crash the kernel.
682 config GPTMR0_CLOCKSOURCE
685 depends on !TICKSOURCE_GPTMR0
691 prompt "Blackfin Exception Scratch Register"
692 default BFIN_SCRATCH_REG_RETN
694 Select the resource to reserve for the Exception handler:
695 - RETN: Non-Maskable Interrupt (NMI)
696 - RETE: Exception Return (JTAG/ICE)
697 - CYCLES: Performance counter
699 If you are unsure, please select "RETN".
701 config BFIN_SCRATCH_REG_RETN
704 Use the RETN register in the Blackfin exception handler
705 as a stack scratch register. This means you cannot
706 safely use NMI on the Blackfin while running Linux, but
707 you can debug the system with a JTAG ICE and use the
708 CYCLES performance registers.
710 If you are unsure, please select "RETN".
712 config BFIN_SCRATCH_REG_RETE
715 Use the RETE register in the Blackfin exception handler
716 as a stack scratch register. This means you cannot
717 safely use a JTAG ICE while debugging a Blackfin board,
718 but you can safely use the CYCLES performance registers
721 If you are unsure, please select "RETN".
723 config BFIN_SCRATCH_REG_CYCLES
726 Use the CYCLES register in the Blackfin exception handler
727 as a stack scratch register. This means you cannot
728 safely use the CYCLES performance registers on a Blackfin
729 board at anytime, but you can debug the system with a JTAG
732 If you are unsure, please select "RETN".
739 menu "Blackfin Kernel Optimizations"
741 comment "Memory Optimizations"
744 bool "Locate interrupt entry code in L1 Memory"
748 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
749 into L1 instruction memory. (less latency)
751 config EXCPT_IRQ_SYSC_L1
752 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
756 If enabled, the entire ASM lowlevel exception and interrupt entry code
757 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
761 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
765 If enabled, the frequently called do_irq dispatcher function is linked
766 into L1 instruction memory. (less latency)
768 config CORE_TIMER_IRQ_L1
769 bool "Locate frequently called timer_interrupt() function in L1 Memory"
773 If enabled, the frequently called timer_interrupt() function is linked
774 into L1 instruction memory. (less latency)
777 bool "Locate frequently idle function in L1 Memory"
781 If enabled, the frequently called idle function is linked
782 into L1 instruction memory. (less latency)
785 bool "Locate kernel schedule function in L1 Memory"
789 If enabled, the frequently called kernel schedule is linked
790 into L1 instruction memory. (less latency)
792 config ARITHMETIC_OPS_L1
793 bool "Locate kernel owned arithmetic functions in L1 Memory"
797 If enabled, arithmetic functions are linked
798 into L1 instruction memory. (less latency)
801 bool "Locate access_ok function in L1 Memory"
805 If enabled, the access_ok function is linked
806 into L1 instruction memory. (less latency)
809 bool "Locate memset function in L1 Memory"
813 If enabled, the memset function is linked
814 into L1 instruction memory. (less latency)
817 bool "Locate memcpy function in L1 Memory"
821 If enabled, the memcpy function is linked
822 into L1 instruction memory. (less latency)
825 bool "locate strcmp function in L1 Memory"
829 If enabled, the strcmp function is linked
830 into L1 instruction memory (less latency).
833 bool "locate strncmp function in L1 Memory"
837 If enabled, the strncmp function is linked
838 into L1 instruction memory (less latency).
841 bool "locate strcpy function in L1 Memory"
845 If enabled, the strcpy function is linked
846 into L1 instruction memory (less latency).
849 bool "locate strncpy function in L1 Memory"
853 If enabled, the strncpy function is linked
854 into L1 instruction memory (less latency).
856 config SYS_BFIN_SPINLOCK_L1
857 bool "Locate sys_bfin_spinlock function in L1 Memory"
861 If enabled, sys_bfin_spinlock function is linked
862 into L1 instruction memory. (less latency)
864 config IP_CHECKSUM_L1
865 bool "Locate IP Checksum function in L1 Memory"
869 If enabled, the IP Checksum function is linked
870 into L1 instruction memory. (less latency)
872 config CACHELINE_ALIGNED_L1
873 bool "Locate cacheline_aligned data to L1 Data Memory"
876 depends on !SMP && !BF531 && !CRC32
878 If enabled, cacheline_aligned data is linked
879 into L1 data memory. (less latency)
881 config SYSCALL_TAB_L1
882 bool "Locate Syscall Table L1 Data Memory"
884 depends on !SMP && !BF531
886 If enabled, the Syscall LUT is linked
887 into L1 data memory. (less latency)
889 config CPLB_SWITCH_TAB_L1
890 bool "Locate CPLB Switch Tables L1 Data Memory"
892 depends on !SMP && !BF531
894 If enabled, the CPLB Switch Tables are linked
895 into L1 data memory. (less latency)
897 config ICACHE_FLUSH_L1
898 bool "Locate icache flush funcs in L1 Inst Memory"
901 If enabled, the Blackfin icache flushing functions are linked
902 into L1 instruction memory.
904 Note that this might be required to address anomalies, but
905 these functions are pretty small, so it shouldn't be too bad.
906 If you are using a processor affected by an anomaly, the build
907 system will double check for you and prevent it.
909 config DCACHE_FLUSH_L1
910 bool "Locate dcache flush funcs in L1 Inst Memory"
914 If enabled, the Blackfin dcache flushing functions are linked
915 into L1 instruction memory.
918 bool "Support locating application stack in L1 Scratch Memory"
922 If enabled the application stack can be located in L1
923 scratch memory (less latency).
925 Currently only works with FLAT binaries.
927 config EXCEPTION_L1_SCRATCH
928 bool "Locate exception stack in L1 Scratch Memory"
930 depends on !SMP && !APP_STACK_L1
932 Whenever an exception occurs, use the L1 Scratch memory for
933 stack storage. You cannot place the stacks of FLAT binaries
934 in L1 when using this option.
936 If you don't use L1 Scratch, then you should say Y here.
938 comment "Speed Optimizations"
939 config BFIN_INS_LOWOVERHEAD
940 bool "ins[bwl] low overhead, higher interrupt latency"
944 Reads on the Blackfin are speculative. In Blackfin terms, this means
945 they can be interrupted at any time (even after they have been issued
946 on to the external bus), and re-issued after the interrupt occurs.
947 For memory - this is not a big deal, since memory does not change if
950 If a FIFO is sitting on the end of the read, it will see two reads,
951 when the core only sees one since the FIFO receives both the read
952 which is cancelled (and not delivered to the core) and the one which
953 is re-issued (which is delivered to the core).
955 To solve this, interrupts are turned off before reads occur to
956 I/O space. This option controls which the overhead/latency of
957 controlling interrupts during this time
958 "n" turns interrupts off every read
959 (higher overhead, but lower interrupt latency)
960 "y" turns interrupts off every loop
961 (low overhead, but longer interrupt latency)
963 default behavior is to leave this set to on (type "Y"). If you are experiencing
964 interrupt latency issues, it is safe and OK to turn this off.
969 prompt "Kernel executes from"
971 Choose the memory type that the kernel will be running in.
976 The kernel will be resident in RAM when running.
981 The kernel will be resident in FLASH/ROM when running.
985 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
994 tristate "Enable Blackfin General Purpose Timers API"
997 Enable support for the General Purpose Timers API. If you
1000 To compile this driver as a module, choose M here: the module
1001 will be called gptimers.
1004 prompt "Uncached DMA region"
1005 default DMA_UNCACHED_1M
1006 config DMA_UNCACHED_32M
1007 bool "Enable 32M DMA region"
1008 config DMA_UNCACHED_16M
1009 bool "Enable 16M DMA region"
1010 config DMA_UNCACHED_8M
1011 bool "Enable 8M DMA region"
1012 config DMA_UNCACHED_4M
1013 bool "Enable 4M DMA region"
1014 config DMA_UNCACHED_2M
1015 bool "Enable 2M DMA region"
1016 config DMA_UNCACHED_1M
1017 bool "Enable 1M DMA region"
1018 config DMA_UNCACHED_512K
1019 bool "Enable 512K DMA region"
1020 config DMA_UNCACHED_256K
1021 bool "Enable 256K DMA region"
1022 config DMA_UNCACHED_128K
1023 bool "Enable 128K DMA region"
1024 config DMA_UNCACHED_NONE
1025 bool "Disable DMA region"
1029 comment "Cache Support"
1032 bool "Enable ICACHE"
1034 config BFIN_EXTMEM_ICACHEABLE
1035 bool "Enable ICACHE for external memory"
1036 depends on BFIN_ICACHE
1038 config BFIN_L2_ICACHEABLE
1039 bool "Enable ICACHE for L2 SRAM"
1040 depends on BFIN_ICACHE
1041 depends on (BF54x || BF561 || BF60x) && !SMP
1045 bool "Enable DCACHE"
1047 config BFIN_DCACHE_BANKA
1048 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1049 depends on BFIN_DCACHE && !BF531
1051 config BFIN_EXTMEM_DCACHEABLE
1052 bool "Enable DCACHE for external memory"
1053 depends on BFIN_DCACHE
1056 prompt "External memory DCACHE policy"
1057 depends on BFIN_EXTMEM_DCACHEABLE
1058 default BFIN_EXTMEM_WRITEBACK if !SMP
1059 default BFIN_EXTMEM_WRITETHROUGH if SMP
1060 config BFIN_EXTMEM_WRITEBACK
1065 Cached data will be written back to SDRAM only when needed.
1066 This can give a nice increase in performance, but beware of
1067 broken drivers that do not properly invalidate/flush their
1070 Write Through Policy:
1071 Cached data will always be written back to SDRAM when the
1072 cache is updated. This is a completely safe setting, but
1073 performance is worse than Write Back.
1075 If you are unsure of the options and you want to be safe,
1076 then go with Write Through.
1078 config BFIN_EXTMEM_WRITETHROUGH
1079 bool "Write through"
1082 Cached data will be written back to SDRAM only when needed.
1083 This can give a nice increase in performance, but beware of
1084 broken drivers that do not properly invalidate/flush their
1087 Write Through Policy:
1088 Cached data will always be written back to SDRAM when the
1089 cache is updated. This is a completely safe setting, but
1090 performance is worse than Write Back.
1092 If you are unsure of the options and you want to be safe,
1093 then go with Write Through.
1097 config BFIN_L2_DCACHEABLE
1098 bool "Enable DCACHE for L2 SRAM"
1099 depends on BFIN_DCACHE
1100 depends on (BF54x || BF561 || BF60x) && !SMP
1103 prompt "L2 SRAM DCACHE policy"
1104 depends on BFIN_L2_DCACHEABLE
1105 default BFIN_L2_WRITEBACK
1106 config BFIN_L2_WRITEBACK
1109 config BFIN_L2_WRITETHROUGH
1110 bool "Write through"
1114 comment "Memory Protection Unit"
1116 bool "Enable the memory protection unit"
1119 Use the processor's MPU to protect applications from accessing
1120 memory they do not own. This comes at a performance penalty
1121 and is recommended only for debugging.
1123 comment "Asynchronous Memory Configuration"
1125 menu "EBIU_AMGCTL Global Control"
1128 bool "Enable CLKOUT"
1132 bool "DMA has priority over core for ext. accesses"
1137 bool "Bank 0 16 bit packing enable"
1142 bool "Bank 1 16 bit packing enable"
1147 bool "Bank 2 16 bit packing enable"
1152 bool "Bank 3 16 bit packing enable"
1156 prompt "Enable Asynchronous Memory Banks"
1160 bool "Disable All Banks"
1163 bool "Enable Bank 0"
1165 config C_AMBEN_B0_B1
1166 bool "Enable Bank 0 & 1"
1168 config C_AMBEN_B0_B1_B2
1169 bool "Enable Bank 0 & 1 & 2"
1172 bool "Enable All Banks"
1176 menu "EBIU_AMBCTL Control"
1179 hex "Bank 0 (AMBCTL0.L)"
1182 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1183 used to control the Asynchronous Memory Bank 0 settings.
1186 hex "Bank 1 (AMBCTL0.H)"
1188 default 0x5558 if BF54x
1190 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1191 used to control the Asynchronous Memory Bank 1 settings.
1194 hex "Bank 2 (AMBCTL1.L)"
1197 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1198 used to control the Asynchronous Memory Bank 2 settings.
1201 hex "Bank 3 (AMBCTL1.H)"
1204 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1205 used to control the Asynchronous Memory Bank 3 settings.
1209 config EBIU_MBSCTLVAL
1210 hex "EBIU Bank Select Control Register"
1215 hex "Flash Memory Mode Control Register"
1220 hex "Flash Memory Bank Control Register"
1225 #############################################################################
1226 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1232 Support for PCI bus.
1234 source "drivers/pci/Kconfig"
1236 source "drivers/pcmcia/Kconfig"
1238 source "drivers/pci/hotplug/Kconfig"
1242 menu "Executable file formats"
1244 source "fs/Kconfig.binfmt"
1248 menu "Power management options"
1250 source "kernel/power/Kconfig"
1252 config ARCH_SUSPEND_POSSIBLE
1256 prompt "Standby Power Saving Mode"
1257 depends on PM && !BF60x
1258 default PM_BFIN_SLEEP_DEEPER
1259 config PM_BFIN_SLEEP_DEEPER
1262 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1263 power dissipation by disabling the clock to the processor core (CCLK).
1264 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1265 to 0.85 V to provide the greatest power savings, while preserving the
1267 The PLL and system clock (SCLK) continue to operate at a very low
1268 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1269 the SDRAM is put into Self Refresh Mode. Typically an external event
1270 such as GPIO interrupt or RTC activity wakes up the processor.
1271 Various Peripherals such as UART, SPORT, PPI may not function as
1272 normal during Sleep Deeper, due to the reduced SCLK frequency.
1273 When in the sleep mode, system DMA access to L1 memory is not supported.
1275 If unsure, select "Sleep Deeper".
1277 config PM_BFIN_SLEEP
1280 Sleep Mode (High Power Savings) - The sleep mode reduces power
1281 dissipation by disabling the clock to the processor core (CCLK).
1282 The PLL and system clock (SCLK), however, continue to operate in
1283 this mode. Typically an external event or RTC activity will wake
1284 up the processor. When in the sleep mode, system DMA access to L1
1285 memory is not supported.
1287 If unsure, select "Sleep Deeper".
1290 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1293 config PM_BFIN_WAKE_PH6
1294 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1295 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1298 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1300 config PM_BFIN_WAKE_GP
1301 bool "Allow Wake-Up from GPIOs"
1302 depends on PM && BF54x
1305 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1306 (all processors, except ADSP-BF549). This option sets
1307 the general-purpose wake-up enable (GPWE) control bit to enable
1308 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1309 On ADSP-BF549 this option enables the same functionality on the
1310 /MRXON pin also PH7.
1312 config PM_BFIN_WAKE_PA15
1313 bool "Allow Wake-Up from PA15"
1314 depends on PM && BF60x
1319 config PM_BFIN_WAKE_PA15_POL
1320 int "Wake-up priority"
1321 depends on PM_BFIN_WAKE_PA15
1324 Wake-Up priority 0(low) 1(high)
1326 config PM_BFIN_WAKE_PB15
1327 bool "Allow Wake-Up from PB15"
1328 depends on PM && BF60x
1333 config PM_BFIN_WAKE_PB15_POL
1334 int "Wake-up priority"
1335 depends on PM_BFIN_WAKE_PB15
1338 Wake-Up priority 0(low) 1(high)
1340 config PM_BFIN_WAKE_PC15
1341 bool "Allow Wake-Up from PC15"
1342 depends on PM && BF60x
1347 config PM_BFIN_WAKE_PC15_POL
1348 int "Wake-up priority"
1349 depends on PM_BFIN_WAKE_PC15
1352 Wake-Up priority 0(low) 1(high)
1354 config PM_BFIN_WAKE_PD06
1355 bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1356 depends on PM && BF60x
1359 Enable PD06(ETH0_PHYINT) Wake-up
1361 config PM_BFIN_WAKE_PD06_POL
1362 int "Wake-up priority"
1363 depends on PM_BFIN_WAKE_PD06
1366 Wake-Up priority 0(low) 1(high)
1368 config PM_BFIN_WAKE_PE12
1369 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1370 depends on PM && BF60x
1373 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1375 config PM_BFIN_WAKE_PE12_POL
1376 int "Wake-up priority"
1377 depends on PM_BFIN_WAKE_PE12
1380 Wake-Up priority 0(low) 1(high)
1382 config PM_BFIN_WAKE_PG04
1383 bool "Allow Wake-Up from PG04(CAN0_RX)"
1384 depends on PM && BF60x
1387 Enable PG04(CAN0_RX) Wake-up
1389 config PM_BFIN_WAKE_PG04_POL
1390 int "Wake-up priority"
1391 depends on PM_BFIN_WAKE_PG04
1394 Wake-Up priority 0(low) 1(high)
1396 config PM_BFIN_WAKE_PG13
1397 bool "Allow Wake-Up from PG13"
1398 depends on PM && BF60x
1403 config PM_BFIN_WAKE_PG13_POL
1404 int "Wake-up priority"
1405 depends on PM_BFIN_WAKE_PG13
1408 Wake-Up priority 0(low) 1(high)
1410 config PM_BFIN_WAKE_USB
1411 bool "Allow Wake-Up from (USB)"
1412 depends on PM && BF60x
1415 Enable (USB) Wake-up
1417 config PM_BFIN_WAKE_USB_POL
1418 int "Wake-up priority"
1419 depends on PM_BFIN_WAKE_USB
1422 Wake-Up priority 0(low) 1(high)
1426 menu "CPU Frequency scaling"
1428 source "drivers/cpufreq/Kconfig"
1430 config BFIN_CPU_FREQ
1433 select CPU_FREQ_TABLE
1437 bool "CPU Voltage scaling"
1441 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1442 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1443 manuals. There is a theoretical risk that during VDDINT transitions
1448 source "net/Kconfig"
1450 source "drivers/Kconfig"
1452 source "drivers/firmware/Kconfig"
1456 source "arch/blackfin/Kconfig.debug"
1458 source "security/Kconfig"
1460 source "crypto/Kconfig"
1462 source "lib/Kconfig"