11 config RWSEM_GENERIC_SPINLOCK
14 config RWSEM_XCHGADD_ALGORITHM
20 select HAVE_ARCH_TRACEHOOK
21 select HAVE_DYNAMIC_FTRACE
22 select HAVE_FTRACE_MCOUNT_RECORD
23 select HAVE_FUNCTION_GRAPH_TRACER
24 select HAVE_FUNCTION_TRACER
25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
28 select HAVE_KERNEL_GZIP if RAMKERNEL
29 select HAVE_KERNEL_BZIP2 if RAMKERNEL
30 select HAVE_KERNEL_LZMA if RAMKERNEL
31 select HAVE_KERNEL_LZO if RAMKERNEL
33 select HAVE_PERF_EVENTS
34 select ARCH_WANT_OPTIONAL_GPIOLIB
35 select HAVE_GENERIC_HARDIRQS
36 select GENERIC_ATOMIC64
37 select GENERIC_IRQ_PROBE
38 select IRQ_PER_CPU if SMP
39 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
54 config FORCE_MAX_ZONEORDER
58 config GENERIC_CALIBRATE_DELAY
61 config LOCKDEP_SUPPORT
64 config STACKTRACE_SUPPORT
67 config TRACE_IRQFLAGS_SUPPORT
72 source "kernel/Kconfig.preempt"
74 source "kernel/Kconfig.freezer"
76 menu "Blackfin Processor Options"
78 comment "Processor and Board Settings"
87 BF512 Processor Support.
92 BF514 Processor Support.
97 BF516 Processor Support.
102 BF518 Processor Support.
107 BF522 Processor Support.
112 BF523 Processor Support.
117 BF524 Processor Support.
122 BF525 Processor Support.
127 BF526 Processor Support.
132 BF527 Processor Support.
137 BF531 Processor Support.
142 BF532 Processor Support.
147 BF533 Processor Support.
152 BF534 Processor Support.
157 BF536 Processor Support.
162 BF537 Processor Support.
167 BF538 Processor Support.
172 BF539 Processor Support.
177 BF542 Processor Support.
182 BF542 Processor Support.
187 BF544 Processor Support.
192 BF544 Processor Support.
197 BF547 Processor Support.
202 BF547 Processor Support.
207 BF548 Processor Support.
212 BF548 Processor Support.
217 BF549 Processor Support.
222 BF549 Processor Support.
227 BF561 Processor Support.
233 BF609 Processor Support.
239 select TICKSOURCE_CORETMR
240 bool "Symmetric multi-processing support"
242 This enables support for systems with more than one CPU,
243 like the dual core BF561. If you have a system with only one
244 CPU, say N. If you have a system with more than one CPU, say Y.
246 If you don't know what to do here, say N.
254 bool "Support for hot-pluggable CPUs"
255 depends on SMP && HOTPLUG
260 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
261 default 2 if (BF537 || BF536 || BF534)
262 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
263 default 4 if (BF538 || BF539)
267 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
268 default 3 if (BF537 || BF536 || BF534 || BF54xM)
269 default 5 if (BF561 || BF538 || BF539)
270 default 6 if (BF533 || BF532 || BF531)
274 default BF_REV_0_0 if (BF51x || BF52x || BF60x)
275 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
276 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
280 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
284 depends on (BF51x || BF52x || (BF54x && !BF54xM))
288 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
292 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
296 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
300 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
304 depends on (BF533 || BF532 || BF531)
316 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
319 config MEM_MT48LC64M4A2FB_7E
321 depends on (BFIN533_STAMP)
324 config MEM_MT48LC16M16A2TG_75
326 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
327 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
328 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
329 || BFIN527_BLUETECHNIX_CM)
332 config MEM_MT48LC32M8A2_75
334 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
337 config MEM_MT48LC8M32B2B5_7
339 depends on (BFIN561_BLUETECHNIX_CM)
342 config MEM_MT48LC32M16A2TG_75
344 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
347 config MEM_MT48H32M16LFCJ_75
349 depends on (BFIN526_EZBRD)
352 source "arch/blackfin/mach-bf518/Kconfig"
353 source "arch/blackfin/mach-bf527/Kconfig"
354 source "arch/blackfin/mach-bf533/Kconfig"
355 source "arch/blackfin/mach-bf561/Kconfig"
356 source "arch/blackfin/mach-bf537/Kconfig"
357 source "arch/blackfin/mach-bf538/Kconfig"
358 source "arch/blackfin/mach-bf548/Kconfig"
359 source "arch/blackfin/mach-bf609/Kconfig"
361 menu "Board customizations"
364 bool "Default bootloader kernel arguments"
367 string "Initial kernel command string"
368 depends on CMDLINE_BOOL
369 default "console=ttyBF0,57600"
371 If you don't have a boot loader capable of passing a command line string
372 to the kernel, you may specify one here. As a minimum, you should specify
373 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
376 hex "Kernel load address for booting"
378 range 0x1000 0x20000000
380 This option allows you to set the load address of the kernel.
381 This can be useful if you are on a board which has a small amount
382 of memory or you wish to reserve some memory at the beginning of
385 Note that you need to keep this value above 4k (0x1000) as this
386 memory region is used to capture NULL pointer references as well
387 as some core kernel functions.
389 config PHY_RAM_BASE_ADDRESS
390 hex "Physical RAM Base"
393 set BF609 FPGA physical SRAM base address
396 hex "Kernel ROM Base"
399 range 0x20000000 0x20400000 if !(BF54x || BF561)
400 range 0x20000000 0x30000000 if (BF54x || BF561)
402 Make sure your ROM base does not include any file-header
403 information that is prepended to the kernel.
405 For example, the bootable U-Boot format (created with
406 mkimage) has a 64 byte header (0x40). So while the image
407 you write to flash might start at say 0x20080000, you have
408 to add 0x40 to get the kernel's ROM base as it will come
411 comment "Clock/PLL Setup"
414 int "Frequency of the crystal on the board in Hz"
415 default "10000000" if BFIN532_IP0X
416 default "11059200" if BFIN533_STAMP
417 default "24576000" if PNAV10
418 default "25000000" # most people use this
419 default "27000000" if BFIN533_EZKIT
420 default "30000000" if BFIN561_EZKIT
421 default "24000000" if BFIN527_AD7160EVAL
423 The frequency of CLKIN crystal oscillator on the board in Hz.
424 Warning: This value should match the crystal on the board. Otherwise,
425 peripherals won't work properly.
427 config BFIN_KERNEL_CLOCK
428 bool "Re-program Clocks while Kernel boots?"
431 This option decides if kernel clocks are re-programed from the
432 bootloader settings. If the clocks are not set, the SDRAM settings
433 are also not changed, and the Bootloader does 100% of the hardware
438 depends on BFIN_KERNEL_CLOCK && (!BF60x)
443 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
446 If this is set the clock will be divided by 2, before it goes to the PLL.
450 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
452 default "22" if BFIN533_EZKIT
453 default "45" if BFIN533_STAMP
454 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
455 default "22" if BFIN533_BLUETECHNIX_CM
456 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
457 default "20" if (BFIN561_EZKIT || BF609)
458 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
459 default "25" if BFIN527_AD7160EVAL
461 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
462 PLL Frequency = (Crystal Frequency) * (this setting)
465 prompt "Core Clock Divider"
466 depends on BFIN_KERNEL_CLOCK
469 This sets the frequency of the core. It can be 1, 2, 4 or 8
470 Core Frequency = (PLL frequency) / (this setting)
486 int "System Clock Divider"
487 depends on BFIN_KERNEL_CLOCK
491 This sets the frequency of the system clock (including SDRAM or DDR) on
492 !BF60x else it set the clock for system buses and provides the
493 source from which SCLK0 and SCLK1 are derived.
494 This can be between 1 and 15
495 System Clock = (PLL frequency) / (this setting)
498 int "System Clock0 Divider"
499 depends on BFIN_KERNEL_CLOCK && BF60x
503 This sets the frequency of the system clock0 for PVP and all other
504 peripherals not clocked by SCLK1.
505 This can be between 1 and 15
506 System Clock0 = (System Clock) / (this setting)
509 int "System Clock1 Divider"
510 depends on BFIN_KERNEL_CLOCK && BF60x
514 This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
515 This can be between 1 and 15
516 System Clock1 = (System Clock) / (this setting)
519 int "DDR Clock Divider"
520 depends on BFIN_KERNEL_CLOCK && BF60x
524 This sets the frequency of the DDR memory.
525 This can be between 1 and 15
526 DDR Clock = (PLL frequency) / (this setting)
529 prompt "DDR SDRAM Chip Type"
530 depends on BFIN_KERNEL_CLOCK
532 default MEM_MT46V32M16_5B
534 config MEM_MT46V32M16_6T
537 config MEM_MT46V32M16_5B
542 prompt "DDR/SDRAM Timing"
543 depends on BFIN_KERNEL_CLOCK && !BF60x
544 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
546 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
547 The calculated SDRAM timing parameters may not be 100%
548 accurate - This option is therefore marked experimental.
550 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
551 bool "Calculate Timings (EXPERIMENTAL)"
552 depends on EXPERIMENTAL
554 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
555 bool "Provide accurate Timings based on target SCLK"
557 Please consult the Blackfin Hardware Reference Manuals as well
558 as the memory device datasheet.
559 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
562 menu "Memory Init Control"
563 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
580 config MEM_EBIU_DDRQUE
597 # Max & Min Speeds for various Chips
601 default 400000000 if BF512
602 default 400000000 if BF514
603 default 400000000 if BF516
604 default 400000000 if BF518
605 default 400000000 if BF522
606 default 600000000 if BF523
607 default 400000000 if BF524
608 default 600000000 if BF525
609 default 400000000 if BF526
610 default 600000000 if BF527
611 default 400000000 if BF531
612 default 400000000 if BF532
613 default 750000000 if BF533
614 default 500000000 if BF534
615 default 400000000 if BF536
616 default 600000000 if BF537
617 default 533333333 if BF538
618 default 533333333 if BF539
619 default 600000000 if BF542
620 default 533333333 if BF544
621 default 600000000 if BF547
622 default 600000000 if BF548
623 default 533333333 if BF549
624 default 600000000 if BF561
625 default 800000000 if BF609
633 default 200000000 if BF609
640 comment "Kernel Timer/Scheduler"
642 source kernel/Kconfig.hz
644 config GENERIC_CLOCKEVENTS
645 bool "Generic clock events"
648 menu "Clock event device"
649 depends on GENERIC_CLOCKEVENTS
650 config TICKSOURCE_GPTMR0
655 config TICKSOURCE_CORETMR
661 depends on GENERIC_CLOCKEVENTS
662 config CYCLES_CLOCKSOURCE
665 depends on !BFIN_SCRATCH_REG_CYCLES
668 If you say Y here, you will enable support for using the 'cycles'
669 registers as a clock source. Doing so means you will be unable to
670 safely write to the 'cycles' register during runtime. You will
671 still be able to read it (such as for performance monitoring), but
672 writing the registers will most likely crash the kernel.
674 config GPTMR0_CLOCKSOURCE
677 depends on !TICKSOURCE_GPTMR0
680 config ARCH_USES_GETTIMEOFFSET
681 depends on !GENERIC_CLOCKEVENTS
684 source kernel/time/Kconfig
689 prompt "Blackfin Exception Scratch Register"
690 default BFIN_SCRATCH_REG_RETN
692 Select the resource to reserve for the Exception handler:
693 - RETN: Non-Maskable Interrupt (NMI)
694 - RETE: Exception Return (JTAG/ICE)
695 - CYCLES: Performance counter
697 If you are unsure, please select "RETN".
699 config BFIN_SCRATCH_REG_RETN
702 Use the RETN register in the Blackfin exception handler
703 as a stack scratch register. This means you cannot
704 safely use NMI on the Blackfin while running Linux, but
705 you can debug the system with a JTAG ICE and use the
706 CYCLES performance registers.
708 If you are unsure, please select "RETN".
710 config BFIN_SCRATCH_REG_RETE
713 Use the RETE register in the Blackfin exception handler
714 as a stack scratch register. This means you cannot
715 safely use a JTAG ICE while debugging a Blackfin board,
716 but you can safely use the CYCLES performance registers
719 If you are unsure, please select "RETN".
721 config BFIN_SCRATCH_REG_CYCLES
724 Use the CYCLES register in the Blackfin exception handler
725 as a stack scratch register. This means you cannot
726 safely use the CYCLES performance registers on a Blackfin
727 board at anytime, but you can debug the system with a JTAG
730 If you are unsure, please select "RETN".
737 menu "Blackfin Kernel Optimizations"
739 comment "Memory Optimizations"
742 bool "Locate interrupt entry code in L1 Memory"
746 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
747 into L1 instruction memory. (less latency)
749 config EXCPT_IRQ_SYSC_L1
750 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
754 If enabled, the entire ASM lowlevel exception and interrupt entry code
755 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
759 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
763 If enabled, the frequently called do_irq dispatcher function is linked
764 into L1 instruction memory. (less latency)
766 config CORE_TIMER_IRQ_L1
767 bool "Locate frequently called timer_interrupt() function in L1 Memory"
771 If enabled, the frequently called timer_interrupt() function is linked
772 into L1 instruction memory. (less latency)
775 bool "Locate frequently idle function in L1 Memory"
779 If enabled, the frequently called idle function is linked
780 into L1 instruction memory. (less latency)
783 bool "Locate kernel schedule function in L1 Memory"
787 If enabled, the frequently called kernel schedule is linked
788 into L1 instruction memory. (less latency)
790 config ARITHMETIC_OPS_L1
791 bool "Locate kernel owned arithmetic functions in L1 Memory"
795 If enabled, arithmetic functions are linked
796 into L1 instruction memory. (less latency)
799 bool "Locate access_ok function in L1 Memory"
803 If enabled, the access_ok function is linked
804 into L1 instruction memory. (less latency)
807 bool "Locate memset function in L1 Memory"
811 If enabled, the memset function is linked
812 into L1 instruction memory. (less latency)
815 bool "Locate memcpy function in L1 Memory"
819 If enabled, the memcpy function is linked
820 into L1 instruction memory. (less latency)
823 bool "locate strcmp function in L1 Memory"
827 If enabled, the strcmp function is linked
828 into L1 instruction memory (less latency).
831 bool "locate strncmp function in L1 Memory"
835 If enabled, the strncmp function is linked
836 into L1 instruction memory (less latency).
839 bool "locate strcpy function in L1 Memory"
843 If enabled, the strcpy function is linked
844 into L1 instruction memory (less latency).
847 bool "locate strncpy function in L1 Memory"
851 If enabled, the strncpy function is linked
852 into L1 instruction memory (less latency).
854 config SYS_BFIN_SPINLOCK_L1
855 bool "Locate sys_bfin_spinlock function in L1 Memory"
859 If enabled, sys_bfin_spinlock function is linked
860 into L1 instruction memory. (less latency)
862 config IP_CHECKSUM_L1
863 bool "Locate IP Checksum function in L1 Memory"
867 If enabled, the IP Checksum function is linked
868 into L1 instruction memory. (less latency)
870 config CACHELINE_ALIGNED_L1
871 bool "Locate cacheline_aligned data to L1 Data Memory"
874 depends on !SMP && !BF531 && !CRC32
876 If enabled, cacheline_aligned data is linked
877 into L1 data memory. (less latency)
879 config SYSCALL_TAB_L1
880 bool "Locate Syscall Table L1 Data Memory"
882 depends on !SMP && !BF531
884 If enabled, the Syscall LUT is linked
885 into L1 data memory. (less latency)
887 config CPLB_SWITCH_TAB_L1
888 bool "Locate CPLB Switch Tables L1 Data Memory"
890 depends on !SMP && !BF531
892 If enabled, the CPLB Switch Tables are linked
893 into L1 data memory. (less latency)
895 config ICACHE_FLUSH_L1
896 bool "Locate icache flush funcs in L1 Inst Memory"
899 If enabled, the Blackfin icache flushing functions are linked
900 into L1 instruction memory.
902 Note that this might be required to address anomalies, but
903 these functions are pretty small, so it shouldn't be too bad.
904 If you are using a processor affected by an anomaly, the build
905 system will double check for you and prevent it.
907 config DCACHE_FLUSH_L1
908 bool "Locate dcache flush funcs in L1 Inst Memory"
912 If enabled, the Blackfin dcache flushing functions are linked
913 into L1 instruction memory.
916 bool "Support locating application stack in L1 Scratch Memory"
920 If enabled the application stack can be located in L1
921 scratch memory (less latency).
923 Currently only works with FLAT binaries.
925 config EXCEPTION_L1_SCRATCH
926 bool "Locate exception stack in L1 Scratch Memory"
928 depends on !SMP && !APP_STACK_L1
930 Whenever an exception occurs, use the L1 Scratch memory for
931 stack storage. You cannot place the stacks of FLAT binaries
932 in L1 when using this option.
934 If you don't use L1 Scratch, then you should say Y here.
936 comment "Speed Optimizations"
937 config BFIN_INS_LOWOVERHEAD
938 bool "ins[bwl] low overhead, higher interrupt latency"
942 Reads on the Blackfin are speculative. In Blackfin terms, this means
943 they can be interrupted at any time (even after they have been issued
944 on to the external bus), and re-issued after the interrupt occurs.
945 For memory - this is not a big deal, since memory does not change if
948 If a FIFO is sitting on the end of the read, it will see two reads,
949 when the core only sees one since the FIFO receives both the read
950 which is cancelled (and not delivered to the core) and the one which
951 is re-issued (which is delivered to the core).
953 To solve this, interrupts are turned off before reads occur to
954 I/O space. This option controls which the overhead/latency of
955 controlling interrupts during this time
956 "n" turns interrupts off every read
957 (higher overhead, but lower interrupt latency)
958 "y" turns interrupts off every loop
959 (low overhead, but longer interrupt latency)
961 default behavior is to leave this set to on (type "Y"). If you are experiencing
962 interrupt latency issues, it is safe and OK to turn this off.
967 prompt "Kernel executes from"
969 Choose the memory type that the kernel will be running in.
974 The kernel will be resident in RAM when running.
979 The kernel will be resident in FLASH/ROM when running.
983 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
992 tristate "Enable Blackfin General Purpose Timers API"
995 Enable support for the General Purpose Timers API. If you
998 To compile this driver as a module, choose M here: the module
999 will be called gptimers.
1002 tristate "Enable PWM API support"
1003 depends on BFIN_GPTIMERS
1005 Enable support for the Pulse Width Modulation framework (as
1006 found in linux/pwm.h).
1008 To compile this driver as a module, choose M here: the module
1012 prompt "Uncached DMA region"
1013 default DMA_UNCACHED_1M
1014 config DMA_UNCACHED_4M
1015 bool "Enable 4M DMA region"
1016 config DMA_UNCACHED_2M
1017 bool "Enable 2M DMA region"
1018 config DMA_UNCACHED_1M
1019 bool "Enable 1M DMA region"
1020 config DMA_UNCACHED_512K
1021 bool "Enable 512K DMA region"
1022 config DMA_UNCACHED_256K
1023 bool "Enable 256K DMA region"
1024 config DMA_UNCACHED_128K
1025 bool "Enable 128K DMA region"
1026 config DMA_UNCACHED_NONE
1027 bool "Disable DMA region"
1031 comment "Cache Support"
1034 bool "Enable ICACHE"
1036 config BFIN_EXTMEM_ICACHEABLE
1037 bool "Enable ICACHE for external memory"
1038 depends on BFIN_ICACHE
1040 config BFIN_L2_ICACHEABLE
1041 bool "Enable ICACHE for L2 SRAM"
1042 depends on BFIN_ICACHE
1043 depends on BF54x || BF561
1047 bool "Enable DCACHE"
1049 config BFIN_DCACHE_BANKA
1050 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1051 depends on BFIN_DCACHE && !BF531
1053 config BFIN_EXTMEM_DCACHEABLE
1054 bool "Enable DCACHE for external memory"
1055 depends on BFIN_DCACHE
1058 prompt "External memory DCACHE policy"
1059 depends on BFIN_EXTMEM_DCACHEABLE
1060 default BFIN_EXTMEM_WRITEBACK if !SMP
1061 default BFIN_EXTMEM_WRITETHROUGH if SMP
1062 config BFIN_EXTMEM_WRITEBACK
1067 Cached data will be written back to SDRAM only when needed.
1068 This can give a nice increase in performance, but beware of
1069 broken drivers that do not properly invalidate/flush their
1072 Write Through Policy:
1073 Cached data will always be written back to SDRAM when the
1074 cache is updated. This is a completely safe setting, but
1075 performance is worse than Write Back.
1077 If you are unsure of the options and you want to be safe,
1078 then go with Write Through.
1080 config BFIN_EXTMEM_WRITETHROUGH
1081 bool "Write through"
1084 Cached data will be written back to SDRAM only when needed.
1085 This can give a nice increase in performance, but beware of
1086 broken drivers that do not properly invalidate/flush their
1089 Write Through Policy:
1090 Cached data will always be written back to SDRAM when the
1091 cache is updated. This is a completely safe setting, but
1092 performance is worse than Write Back.
1094 If you are unsure of the options and you want to be safe,
1095 then go with Write Through.
1099 config BFIN_L2_DCACHEABLE
1100 bool "Enable DCACHE for L2 SRAM"
1101 depends on BFIN_DCACHE
1102 depends on (BF54x || BF561 || BF60x) && !SMP
1105 prompt "L2 SRAM DCACHE policy"
1106 depends on BFIN_L2_DCACHEABLE
1107 default BFIN_L2_WRITEBACK
1108 config BFIN_L2_WRITEBACK
1111 config BFIN_L2_WRITETHROUGH
1112 bool "Write through"
1116 comment "Memory Protection Unit"
1118 bool "Enable the memory protection unit (EXPERIMENTAL)"
1121 Use the processor's MPU to protect applications from accessing
1122 memory they do not own. This comes at a performance penalty
1123 and is recommended only for debugging.
1125 comment "Asynchronous Memory Configuration"
1127 menu "EBIU_AMGCTL Global Control"
1130 bool "Enable CLKOUT"
1134 bool "DMA has priority over core for ext. accesses"
1139 bool "Bank 0 16 bit packing enable"
1144 bool "Bank 1 16 bit packing enable"
1149 bool "Bank 2 16 bit packing enable"
1154 bool "Bank 3 16 bit packing enable"
1158 prompt "Enable Asynchronous Memory Banks"
1162 bool "Disable All Banks"
1165 bool "Enable Bank 0"
1167 config C_AMBEN_B0_B1
1168 bool "Enable Bank 0 & 1"
1170 config C_AMBEN_B0_B1_B2
1171 bool "Enable Bank 0 & 1 & 2"
1174 bool "Enable All Banks"
1178 menu "EBIU_AMBCTL Control"
1181 hex "Bank 0 (AMBCTL0.L)"
1184 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1185 used to control the Asynchronous Memory Bank 0 settings.
1188 hex "Bank 1 (AMBCTL0.H)"
1190 default 0x5558 if BF54x
1192 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1193 used to control the Asynchronous Memory Bank 1 settings.
1196 hex "Bank 2 (AMBCTL1.L)"
1199 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1200 used to control the Asynchronous Memory Bank 2 settings.
1203 hex "Bank 3 (AMBCTL1.H)"
1206 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1207 used to control the Asynchronous Memory Bank 3 settings.
1211 config EBIU_MBSCTLVAL
1212 hex "EBIU Bank Select Control Register"
1217 hex "Flash Memory Mode Control Register"
1222 hex "Flash Memory Bank Control Register"
1227 #############################################################################
1228 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1234 Support for PCI bus.
1236 source "drivers/pci/Kconfig"
1238 source "drivers/pcmcia/Kconfig"
1240 source "drivers/pci/hotplug/Kconfig"
1244 menu "Executable file formats"
1246 source "fs/Kconfig.binfmt"
1250 menu "Power management options"
1252 source "kernel/power/Kconfig"
1254 config ARCH_SUSPEND_POSSIBLE
1258 prompt "Standby Power Saving Mode"
1260 default PM_BFIN_SLEEP_DEEPER
1261 config PM_BFIN_SLEEP_DEEPER
1264 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1265 power dissipation by disabling the clock to the processor core (CCLK).
1266 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1267 to 0.85 V to provide the greatest power savings, while preserving the
1269 The PLL and system clock (SCLK) continue to operate at a very low
1270 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1271 the SDRAM is put into Self Refresh Mode. Typically an external event
1272 such as GPIO interrupt or RTC activity wakes up the processor.
1273 Various Peripherals such as UART, SPORT, PPI may not function as
1274 normal during Sleep Deeper, due to the reduced SCLK frequency.
1275 When in the sleep mode, system DMA access to L1 memory is not supported.
1277 If unsure, select "Sleep Deeper".
1279 config PM_BFIN_SLEEP
1282 Sleep Mode (High Power Savings) - The sleep mode reduces power
1283 dissipation by disabling the clock to the processor core (CCLK).
1284 The PLL and system clock (SCLK), however, continue to operate in
1285 this mode. Typically an external event or RTC activity will wake
1286 up the processor. When in the sleep mode, system DMA access to L1
1287 memory is not supported.
1289 If unsure, select "Sleep Deeper".
1292 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1295 config PM_BFIN_WAKE_PH6
1296 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1297 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1300 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1302 config PM_BFIN_WAKE_GP
1303 bool "Allow Wake-Up from GPIOs"
1304 depends on PM && BF54x
1307 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1308 (all processors, except ADSP-BF549). This option sets
1309 the general-purpose wake-up enable (GPWE) control bit to enable
1310 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1311 On ADSP-BF549 this option enables the the same functionality on the
1312 /MRXON pin also PH7.
1316 menu "CPU Frequency scaling"
1318 source "drivers/cpufreq/Kconfig"
1320 config BFIN_CPU_FREQ
1323 select CPU_FREQ_TABLE
1327 bool "CPU Voltage scaling"
1328 depends on EXPERIMENTAL
1332 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1333 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1334 manuals. There is a theoretical risk that during VDDINT transitions
1339 source "net/Kconfig"
1341 source "drivers/Kconfig"
1343 source "drivers/firmware/Kconfig"
1347 source "arch/blackfin/Kconfig.debug"
1349 source "security/Kconfig"
1351 source "crypto/Kconfig"
1353 source "lib/Kconfig"