11 config RWSEM_GENERIC_SPINLOCK
14 config RWSEM_XCHGADD_ALGORITHM
20 select HAVE_ARCH_TRACEHOOK
21 select HAVE_DYNAMIC_FTRACE
22 select HAVE_FTRACE_MCOUNT_RECORD
23 select HAVE_FUNCTION_GRAPH_TRACER
24 select HAVE_FUNCTION_TRACER
25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
28 select HAVE_KERNEL_GZIP if RAMKERNEL
29 select HAVE_KERNEL_BZIP2 if RAMKERNEL
30 select HAVE_KERNEL_LZMA if RAMKERNEL
31 select HAVE_KERNEL_LZO if RAMKERNEL
33 select HAVE_PERF_EVENTS
34 select ARCH_HAVE_CUSTOM_GPIO_H
35 select ARCH_WANT_OPTIONAL_GPIOLIB
36 select ARCH_WANT_IPC_PARSE_VERSION
37 select HAVE_GENERIC_HARDIRQS
38 select GENERIC_ATOMIC64
39 select GENERIC_IRQ_PROBE
40 select IRQ_PER_CPU if SMP
41 select USE_GENERIC_SMP_HELPERS if SMP
42 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
43 select GENERIC_SMP_IDLE_THREAD
44 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
45 select HAVE_MOD_ARCH_SPECIFIC
46 select MODULES_USE_ELF_RELA
61 config FORCE_MAX_ZONEORDER
65 config GENERIC_CALIBRATE_DELAY
68 config LOCKDEP_SUPPORT
71 config STACKTRACE_SUPPORT
74 config TRACE_IRQFLAGS_SUPPORT
79 source "kernel/Kconfig.preempt"
81 source "kernel/Kconfig.freezer"
83 menu "Blackfin Processor Options"
85 comment "Processor and Board Settings"
94 BF512 Processor Support.
99 BF514 Processor Support.
104 BF516 Processor Support.
109 BF518 Processor Support.
114 BF522 Processor Support.
119 BF523 Processor Support.
124 BF524 Processor Support.
129 BF525 Processor Support.
134 BF526 Processor Support.
139 BF527 Processor Support.
144 BF531 Processor Support.
149 BF532 Processor Support.
154 BF533 Processor Support.
159 BF534 Processor Support.
164 BF536 Processor Support.
169 BF537 Processor Support.
174 BF538 Processor Support.
179 BF539 Processor Support.
184 BF542 Processor Support.
189 BF542 Processor Support.
194 BF544 Processor Support.
199 BF544 Processor Support.
204 BF547 Processor Support.
209 BF547 Processor Support.
214 BF548 Processor Support.
219 BF548 Processor Support.
224 BF549 Processor Support.
229 BF549 Processor Support.
234 BF561 Processor Support.
240 BF609 Processor Support.
246 select TICKSOURCE_CORETMR
247 bool "Symmetric multi-processing support"
249 This enables support for systems with more than one CPU,
250 like the dual core BF561. If you have a system with only one
251 CPU, say N. If you have a system with more than one CPU, say Y.
253 If you don't know what to do here, say N.
261 bool "Support for hot-pluggable CPUs"
262 depends on SMP && HOTPLUG
267 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
268 default 2 if (BF537 || BF536 || BF534)
269 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
270 default 4 if (BF538 || BF539)
274 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
275 default 3 if (BF537 || BF536 || BF534 || BF54xM)
276 default 5 if (BF561 || BF538 || BF539)
277 default 6 if (BF533 || BF532 || BF531)
281 default BF_REV_0_0 if (BF51x || BF52x || BF60x)
282 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
283 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
287 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
291 depends on (BF51x || BF52x || (BF54x && !BF54xM))
295 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
299 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
303 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
307 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
311 depends on (BF533 || BF532 || BF531)
323 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
326 config MEM_MT48LC64M4A2FB_7E
328 depends on (BFIN533_STAMP)
331 config MEM_MT48LC16M16A2TG_75
333 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
334 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
335 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
336 || BFIN527_BLUETECHNIX_CM)
339 config MEM_MT48LC32M8A2_75
341 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
344 config MEM_MT48LC8M32B2B5_7
346 depends on (BFIN561_BLUETECHNIX_CM)
349 config MEM_MT48LC32M16A2TG_75
351 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
354 config MEM_MT48H32M16LFCJ_75
356 depends on (BFIN526_EZBRD)
359 config MEM_MT47H64M16
361 depends on (BFIN609_EZKIT)
364 source "arch/blackfin/mach-bf518/Kconfig"
365 source "arch/blackfin/mach-bf527/Kconfig"
366 source "arch/blackfin/mach-bf533/Kconfig"
367 source "arch/blackfin/mach-bf561/Kconfig"
368 source "arch/blackfin/mach-bf537/Kconfig"
369 source "arch/blackfin/mach-bf538/Kconfig"
370 source "arch/blackfin/mach-bf548/Kconfig"
371 source "arch/blackfin/mach-bf609/Kconfig"
373 menu "Board customizations"
376 bool "Default bootloader kernel arguments"
379 string "Initial kernel command string"
380 depends on CMDLINE_BOOL
381 default "console=ttyBF0,57600"
383 If you don't have a boot loader capable of passing a command line string
384 to the kernel, you may specify one here. As a minimum, you should specify
385 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
388 hex "Kernel load address for booting"
390 range 0x1000 0x20000000
392 This option allows you to set the load address of the kernel.
393 This can be useful if you are on a board which has a small amount
394 of memory or you wish to reserve some memory at the beginning of
397 Note that you need to keep this value above 4k (0x1000) as this
398 memory region is used to capture NULL pointer references as well
399 as some core kernel functions.
401 config PHY_RAM_BASE_ADDRESS
402 hex "Physical RAM Base"
405 set BF609 FPGA physical SRAM base address
408 hex "Kernel ROM Base"
411 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
412 range 0x20000000 0x30000000 if (BF54x || BF561)
413 range 0xB0000000 0xC0000000 if (BF60x)
415 Make sure your ROM base does not include any file-header
416 information that is prepended to the kernel.
418 For example, the bootable U-Boot format (created with
419 mkimage) has a 64 byte header (0x40). So while the image
420 you write to flash might start at say 0x20080000, you have
421 to add 0x40 to get the kernel's ROM base as it will come
424 comment "Clock/PLL Setup"
427 int "Frequency of the crystal on the board in Hz"
428 default "10000000" if BFIN532_IP0X
429 default "11059200" if BFIN533_STAMP
430 default "24576000" if PNAV10
431 default "25000000" # most people use this
432 default "27000000" if BFIN533_EZKIT
433 default "30000000" if BFIN561_EZKIT
434 default "24000000" if BFIN527_AD7160EVAL
436 The frequency of CLKIN crystal oscillator on the board in Hz.
437 Warning: This value should match the crystal on the board. Otherwise,
438 peripherals won't work properly.
440 config BFIN_KERNEL_CLOCK
441 bool "Re-program Clocks while Kernel boots?"
444 This option decides if kernel clocks are re-programed from the
445 bootloader settings. If the clocks are not set, the SDRAM settings
446 are also not changed, and the Bootloader does 100% of the hardware
451 depends on BFIN_KERNEL_CLOCK && (!BF60x)
456 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
459 If this is set the clock will be divided by 2, before it goes to the PLL.
463 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
465 default "22" if BFIN533_EZKIT
466 default "45" if BFIN533_STAMP
467 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
468 default "22" if BFIN533_BLUETECHNIX_CM
469 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
470 default "20" if (BFIN561_EZKIT || BF609)
471 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
472 default "25" if BFIN527_AD7160EVAL
474 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
475 PLL Frequency = (Crystal Frequency) * (this setting)
478 prompt "Core Clock Divider"
479 depends on BFIN_KERNEL_CLOCK
482 This sets the frequency of the core. It can be 1, 2, 4 or 8
483 Core Frequency = (PLL frequency) / (this setting)
499 int "System Clock Divider"
500 depends on BFIN_KERNEL_CLOCK
504 This sets the frequency of the system clock (including SDRAM or DDR) on
505 !BF60x else it set the clock for system buses and provides the
506 source from which SCLK0 and SCLK1 are derived.
507 This can be between 1 and 15
508 System Clock = (PLL frequency) / (this setting)
511 int "System Clock0 Divider"
512 depends on BFIN_KERNEL_CLOCK && BF60x
516 This sets the frequency of the system clock0 for PVP and all other
517 peripherals not clocked by SCLK1.
518 This can be between 1 and 15
519 System Clock0 = (System Clock) / (this setting)
522 int "System Clock1 Divider"
523 depends on BFIN_KERNEL_CLOCK && BF60x
527 This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
528 This can be between 1 and 15
529 System Clock1 = (System Clock) / (this setting)
532 int "DDR Clock Divider"
533 depends on BFIN_KERNEL_CLOCK && BF60x
537 This sets the frequency of the DDR memory.
538 This can be between 1 and 15
539 DDR Clock = (PLL frequency) / (this setting)
542 prompt "DDR SDRAM Chip Type"
543 depends on BFIN_KERNEL_CLOCK
545 default MEM_MT46V32M16_5B
547 config MEM_MT46V32M16_6T
550 config MEM_MT46V32M16_5B
555 prompt "DDR/SDRAM Timing"
556 depends on BFIN_KERNEL_CLOCK && !BF60x
557 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
559 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
560 The calculated SDRAM timing parameters may not be 100%
561 accurate - This option is therefore marked experimental.
563 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
564 bool "Calculate Timings (EXPERIMENTAL)"
565 depends on EXPERIMENTAL
567 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
568 bool "Provide accurate Timings based on target SCLK"
570 Please consult the Blackfin Hardware Reference Manuals as well
571 as the memory device datasheet.
572 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
575 menu "Memory Init Control"
576 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
593 config MEM_EBIU_DDRQUE
610 # Max & Min Speeds for various Chips
614 default 400000000 if BF512
615 default 400000000 if BF514
616 default 400000000 if BF516
617 default 400000000 if BF518
618 default 400000000 if BF522
619 default 600000000 if BF523
620 default 400000000 if BF524
621 default 600000000 if BF525
622 default 400000000 if BF526
623 default 600000000 if BF527
624 default 400000000 if BF531
625 default 400000000 if BF532
626 default 750000000 if BF533
627 default 500000000 if BF534
628 default 400000000 if BF536
629 default 600000000 if BF537
630 default 533333333 if BF538
631 default 533333333 if BF539
632 default 600000000 if BF542
633 default 533333333 if BF544
634 default 600000000 if BF547
635 default 600000000 if BF548
636 default 533333333 if BF549
637 default 600000000 if BF561
638 default 800000000 if BF609
646 default 200000000 if BF609
653 comment "Kernel Timer/Scheduler"
655 source kernel/Kconfig.hz
657 config SET_GENERIC_CLOCKEVENTS
658 bool "Generic clock events"
660 select GENERIC_CLOCKEVENTS
662 menu "Clock event device"
663 depends on GENERIC_CLOCKEVENTS
664 config TICKSOURCE_GPTMR0
669 config TICKSOURCE_CORETMR
675 depends on GENERIC_CLOCKEVENTS
676 config CYCLES_CLOCKSOURCE
679 depends on !BFIN_SCRATCH_REG_CYCLES
682 If you say Y here, you will enable support for using the 'cycles'
683 registers as a clock source. Doing so means you will be unable to
684 safely write to the 'cycles' register during runtime. You will
685 still be able to read it (such as for performance monitoring), but
686 writing the registers will most likely crash the kernel.
688 config GPTMR0_CLOCKSOURCE
691 depends on !TICKSOURCE_GPTMR0
697 prompt "Blackfin Exception Scratch Register"
698 default BFIN_SCRATCH_REG_RETN
700 Select the resource to reserve for the Exception handler:
701 - RETN: Non-Maskable Interrupt (NMI)
702 - RETE: Exception Return (JTAG/ICE)
703 - CYCLES: Performance counter
705 If you are unsure, please select "RETN".
707 config BFIN_SCRATCH_REG_RETN
710 Use the RETN register in the Blackfin exception handler
711 as a stack scratch register. This means you cannot
712 safely use NMI on the Blackfin while running Linux, but
713 you can debug the system with a JTAG ICE and use the
714 CYCLES performance registers.
716 If you are unsure, please select "RETN".
718 config BFIN_SCRATCH_REG_RETE
721 Use the RETE register in the Blackfin exception handler
722 as a stack scratch register. This means you cannot
723 safely use a JTAG ICE while debugging a Blackfin board,
724 but you can safely use the CYCLES performance registers
727 If you are unsure, please select "RETN".
729 config BFIN_SCRATCH_REG_CYCLES
732 Use the CYCLES register in the Blackfin exception handler
733 as a stack scratch register. This means you cannot
734 safely use the CYCLES performance registers on a Blackfin
735 board at anytime, but you can debug the system with a JTAG
738 If you are unsure, please select "RETN".
745 menu "Blackfin Kernel Optimizations"
747 comment "Memory Optimizations"
750 bool "Locate interrupt entry code in L1 Memory"
754 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
755 into L1 instruction memory. (less latency)
757 config EXCPT_IRQ_SYSC_L1
758 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
762 If enabled, the entire ASM lowlevel exception and interrupt entry code
763 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
767 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
771 If enabled, the frequently called do_irq dispatcher function is linked
772 into L1 instruction memory. (less latency)
774 config CORE_TIMER_IRQ_L1
775 bool "Locate frequently called timer_interrupt() function in L1 Memory"
779 If enabled, the frequently called timer_interrupt() function is linked
780 into L1 instruction memory. (less latency)
783 bool "Locate frequently idle function in L1 Memory"
787 If enabled, the frequently called idle function is linked
788 into L1 instruction memory. (less latency)
791 bool "Locate kernel schedule function in L1 Memory"
795 If enabled, the frequently called kernel schedule is linked
796 into L1 instruction memory. (less latency)
798 config ARITHMETIC_OPS_L1
799 bool "Locate kernel owned arithmetic functions in L1 Memory"
803 If enabled, arithmetic functions are linked
804 into L1 instruction memory. (less latency)
807 bool "Locate access_ok function in L1 Memory"
811 If enabled, the access_ok function is linked
812 into L1 instruction memory. (less latency)
815 bool "Locate memset function in L1 Memory"
819 If enabled, the memset function is linked
820 into L1 instruction memory. (less latency)
823 bool "Locate memcpy function in L1 Memory"
827 If enabled, the memcpy function is linked
828 into L1 instruction memory. (less latency)
831 bool "locate strcmp function in L1 Memory"
835 If enabled, the strcmp function is linked
836 into L1 instruction memory (less latency).
839 bool "locate strncmp function in L1 Memory"
843 If enabled, the strncmp function is linked
844 into L1 instruction memory (less latency).
847 bool "locate strcpy function in L1 Memory"
851 If enabled, the strcpy function is linked
852 into L1 instruction memory (less latency).
855 bool "locate strncpy function in L1 Memory"
859 If enabled, the strncpy function is linked
860 into L1 instruction memory (less latency).
862 config SYS_BFIN_SPINLOCK_L1
863 bool "Locate sys_bfin_spinlock function in L1 Memory"
867 If enabled, sys_bfin_spinlock function is linked
868 into L1 instruction memory. (less latency)
870 config IP_CHECKSUM_L1
871 bool "Locate IP Checksum function in L1 Memory"
875 If enabled, the IP Checksum function is linked
876 into L1 instruction memory. (less latency)
878 config CACHELINE_ALIGNED_L1
879 bool "Locate cacheline_aligned data to L1 Data Memory"
882 depends on !SMP && !BF531 && !CRC32
884 If enabled, cacheline_aligned data is linked
885 into L1 data memory. (less latency)
887 config SYSCALL_TAB_L1
888 bool "Locate Syscall Table L1 Data Memory"
890 depends on !SMP && !BF531
892 If enabled, the Syscall LUT is linked
893 into L1 data memory. (less latency)
895 config CPLB_SWITCH_TAB_L1
896 bool "Locate CPLB Switch Tables L1 Data Memory"
898 depends on !SMP && !BF531
900 If enabled, the CPLB Switch Tables are linked
901 into L1 data memory. (less latency)
903 config ICACHE_FLUSH_L1
904 bool "Locate icache flush funcs in L1 Inst Memory"
907 If enabled, the Blackfin icache flushing functions are linked
908 into L1 instruction memory.
910 Note that this might be required to address anomalies, but
911 these functions are pretty small, so it shouldn't be too bad.
912 If you are using a processor affected by an anomaly, the build
913 system will double check for you and prevent it.
915 config DCACHE_FLUSH_L1
916 bool "Locate dcache flush funcs in L1 Inst Memory"
920 If enabled, the Blackfin dcache flushing functions are linked
921 into L1 instruction memory.
924 bool "Support locating application stack in L1 Scratch Memory"
928 If enabled the application stack can be located in L1
929 scratch memory (less latency).
931 Currently only works with FLAT binaries.
933 config EXCEPTION_L1_SCRATCH
934 bool "Locate exception stack in L1 Scratch Memory"
936 depends on !SMP && !APP_STACK_L1
938 Whenever an exception occurs, use the L1 Scratch memory for
939 stack storage. You cannot place the stacks of FLAT binaries
940 in L1 when using this option.
942 If you don't use L1 Scratch, then you should say Y here.
944 comment "Speed Optimizations"
945 config BFIN_INS_LOWOVERHEAD
946 bool "ins[bwl] low overhead, higher interrupt latency"
950 Reads on the Blackfin are speculative. In Blackfin terms, this means
951 they can be interrupted at any time (even after they have been issued
952 on to the external bus), and re-issued after the interrupt occurs.
953 For memory - this is not a big deal, since memory does not change if
956 If a FIFO is sitting on the end of the read, it will see two reads,
957 when the core only sees one since the FIFO receives both the read
958 which is cancelled (and not delivered to the core) and the one which
959 is re-issued (which is delivered to the core).
961 To solve this, interrupts are turned off before reads occur to
962 I/O space. This option controls which the overhead/latency of
963 controlling interrupts during this time
964 "n" turns interrupts off every read
965 (higher overhead, but lower interrupt latency)
966 "y" turns interrupts off every loop
967 (low overhead, but longer interrupt latency)
969 default behavior is to leave this set to on (type "Y"). If you are experiencing
970 interrupt latency issues, it is safe and OK to turn this off.
975 prompt "Kernel executes from"
977 Choose the memory type that the kernel will be running in.
982 The kernel will be resident in RAM when running.
987 The kernel will be resident in FLASH/ROM when running.
991 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
1000 tristate "Enable Blackfin General Purpose Timers API"
1003 Enable support for the General Purpose Timers API. If you
1006 To compile this driver as a module, choose M here: the module
1007 will be called gptimers.
1010 prompt "Uncached DMA region"
1011 default DMA_UNCACHED_1M
1012 config DMA_UNCACHED_32M
1013 bool "Enable 32M DMA region"
1014 config DMA_UNCACHED_16M
1015 bool "Enable 16M DMA region"
1016 config DMA_UNCACHED_8M
1017 bool "Enable 8M DMA region"
1018 config DMA_UNCACHED_4M
1019 bool "Enable 4M DMA region"
1020 config DMA_UNCACHED_2M
1021 bool "Enable 2M DMA region"
1022 config DMA_UNCACHED_1M
1023 bool "Enable 1M DMA region"
1024 config DMA_UNCACHED_512K
1025 bool "Enable 512K DMA region"
1026 config DMA_UNCACHED_256K
1027 bool "Enable 256K DMA region"
1028 config DMA_UNCACHED_128K
1029 bool "Enable 128K DMA region"
1030 config DMA_UNCACHED_NONE
1031 bool "Disable DMA region"
1035 comment "Cache Support"
1038 bool "Enable ICACHE"
1040 config BFIN_EXTMEM_ICACHEABLE
1041 bool "Enable ICACHE for external memory"
1042 depends on BFIN_ICACHE
1044 config BFIN_L2_ICACHEABLE
1045 bool "Enable ICACHE for L2 SRAM"
1046 depends on BFIN_ICACHE
1047 depends on (BF54x || BF561 || BF60x) && !SMP
1051 bool "Enable DCACHE"
1053 config BFIN_DCACHE_BANKA
1054 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1055 depends on BFIN_DCACHE && !BF531
1057 config BFIN_EXTMEM_DCACHEABLE
1058 bool "Enable DCACHE for external memory"
1059 depends on BFIN_DCACHE
1062 prompt "External memory DCACHE policy"
1063 depends on BFIN_EXTMEM_DCACHEABLE
1064 default BFIN_EXTMEM_WRITEBACK if !SMP
1065 default BFIN_EXTMEM_WRITETHROUGH if SMP
1066 config BFIN_EXTMEM_WRITEBACK
1071 Cached data will be written back to SDRAM only when needed.
1072 This can give a nice increase in performance, but beware of
1073 broken drivers that do not properly invalidate/flush their
1076 Write Through Policy:
1077 Cached data will always be written back to SDRAM when the
1078 cache is updated. This is a completely safe setting, but
1079 performance is worse than Write Back.
1081 If you are unsure of the options and you want to be safe,
1082 then go with Write Through.
1084 config BFIN_EXTMEM_WRITETHROUGH
1085 bool "Write through"
1088 Cached data will be written back to SDRAM only when needed.
1089 This can give a nice increase in performance, but beware of
1090 broken drivers that do not properly invalidate/flush their
1093 Write Through Policy:
1094 Cached data will always be written back to SDRAM when the
1095 cache is updated. This is a completely safe setting, but
1096 performance is worse than Write Back.
1098 If you are unsure of the options and you want to be safe,
1099 then go with Write Through.
1103 config BFIN_L2_DCACHEABLE
1104 bool "Enable DCACHE for L2 SRAM"
1105 depends on BFIN_DCACHE
1106 depends on (BF54x || BF561 || BF60x) && !SMP
1109 prompt "L2 SRAM DCACHE policy"
1110 depends on BFIN_L2_DCACHEABLE
1111 default BFIN_L2_WRITEBACK
1112 config BFIN_L2_WRITEBACK
1115 config BFIN_L2_WRITETHROUGH
1116 bool "Write through"
1120 comment "Memory Protection Unit"
1122 bool "Enable the memory protection unit (EXPERIMENTAL)"
1125 Use the processor's MPU to protect applications from accessing
1126 memory they do not own. This comes at a performance penalty
1127 and is recommended only for debugging.
1129 comment "Asynchronous Memory Configuration"
1131 menu "EBIU_AMGCTL Global Control"
1134 bool "Enable CLKOUT"
1138 bool "DMA has priority over core for ext. accesses"
1143 bool "Bank 0 16 bit packing enable"
1148 bool "Bank 1 16 bit packing enable"
1153 bool "Bank 2 16 bit packing enable"
1158 bool "Bank 3 16 bit packing enable"
1162 prompt "Enable Asynchronous Memory Banks"
1166 bool "Disable All Banks"
1169 bool "Enable Bank 0"
1171 config C_AMBEN_B0_B1
1172 bool "Enable Bank 0 & 1"
1174 config C_AMBEN_B0_B1_B2
1175 bool "Enable Bank 0 & 1 & 2"
1178 bool "Enable All Banks"
1182 menu "EBIU_AMBCTL Control"
1185 hex "Bank 0 (AMBCTL0.L)"
1188 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1189 used to control the Asynchronous Memory Bank 0 settings.
1192 hex "Bank 1 (AMBCTL0.H)"
1194 default 0x5558 if BF54x
1196 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1197 used to control the Asynchronous Memory Bank 1 settings.
1200 hex "Bank 2 (AMBCTL1.L)"
1203 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1204 used to control the Asynchronous Memory Bank 2 settings.
1207 hex "Bank 3 (AMBCTL1.H)"
1210 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1211 used to control the Asynchronous Memory Bank 3 settings.
1215 config EBIU_MBSCTLVAL
1216 hex "EBIU Bank Select Control Register"
1221 hex "Flash Memory Mode Control Register"
1226 hex "Flash Memory Bank Control Register"
1231 #############################################################################
1232 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1238 Support for PCI bus.
1240 source "drivers/pci/Kconfig"
1242 source "drivers/pcmcia/Kconfig"
1244 source "drivers/pci/hotplug/Kconfig"
1248 menu "Executable file formats"
1250 source "fs/Kconfig.binfmt"
1254 menu "Power management options"
1256 source "kernel/power/Kconfig"
1258 config ARCH_SUSPEND_POSSIBLE
1262 prompt "Standby Power Saving Mode"
1263 depends on PM && !BF60x
1264 default PM_BFIN_SLEEP_DEEPER
1265 config PM_BFIN_SLEEP_DEEPER
1268 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1269 power dissipation by disabling the clock to the processor core (CCLK).
1270 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1271 to 0.85 V to provide the greatest power savings, while preserving the
1273 The PLL and system clock (SCLK) continue to operate at a very low
1274 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1275 the SDRAM is put into Self Refresh Mode. Typically an external event
1276 such as GPIO interrupt or RTC activity wakes up the processor.
1277 Various Peripherals such as UART, SPORT, PPI may not function as
1278 normal during Sleep Deeper, due to the reduced SCLK frequency.
1279 When in the sleep mode, system DMA access to L1 memory is not supported.
1281 If unsure, select "Sleep Deeper".
1283 config PM_BFIN_SLEEP
1286 Sleep Mode (High Power Savings) - The sleep mode reduces power
1287 dissipation by disabling the clock to the processor core (CCLK).
1288 The PLL and system clock (SCLK), however, continue to operate in
1289 this mode. Typically an external event or RTC activity will wake
1290 up the processor. When in the sleep mode, system DMA access to L1
1291 memory is not supported.
1293 If unsure, select "Sleep Deeper".
1296 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1299 config PM_BFIN_WAKE_PH6
1300 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1301 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1304 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1306 config PM_BFIN_WAKE_GP
1307 bool "Allow Wake-Up from GPIOs"
1308 depends on PM && BF54x
1311 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1312 (all processors, except ADSP-BF549). This option sets
1313 the general-purpose wake-up enable (GPWE) control bit to enable
1314 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1315 On ADSP-BF549 this option enables the same functionality on the
1316 /MRXON pin also PH7.
1318 config PM_BFIN_WAKE_PA15
1319 bool "Allow Wake-Up from PA15"
1320 depends on PM && BF60x
1325 config PM_BFIN_WAKE_PA15_POL
1326 int "Wake-up priority"
1327 depends on PM_BFIN_WAKE_PA15
1330 Wake-Up priority 0(low) 1(high)
1332 config PM_BFIN_WAKE_PB15
1333 bool "Allow Wake-Up from PB15"
1334 depends on PM && BF60x
1339 config PM_BFIN_WAKE_PB15_POL
1340 int "Wake-up priority"
1341 depends on PM_BFIN_WAKE_PB15
1344 Wake-Up priority 0(low) 1(high)
1346 config PM_BFIN_WAKE_PC15
1347 bool "Allow Wake-Up from PC15"
1348 depends on PM && BF60x
1353 config PM_BFIN_WAKE_PC15_POL
1354 int "Wake-up priority"
1355 depends on PM_BFIN_WAKE_PC15
1358 Wake-Up priority 0(low) 1(high)
1360 config PM_BFIN_WAKE_PD06
1361 bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1362 depends on PM && BF60x
1365 Enable PD06(ETH0_PHYINT) Wake-up
1367 config PM_BFIN_WAKE_PD06_POL
1368 int "Wake-up priority"
1369 depends on PM_BFIN_WAKE_PD06
1372 Wake-Up priority 0(low) 1(high)
1374 config PM_BFIN_WAKE_PE12
1375 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1376 depends on PM && BF60x
1379 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1381 config PM_BFIN_WAKE_PE12_POL
1382 int "Wake-up priority"
1383 depends on PM_BFIN_WAKE_PE12
1386 Wake-Up priority 0(low) 1(high)
1388 config PM_BFIN_WAKE_PG04
1389 bool "Allow Wake-Up from PG04(CAN0_RX)"
1390 depends on PM && BF60x
1393 Enable PG04(CAN0_RX) Wake-up
1395 config PM_BFIN_WAKE_PG04_POL
1396 int "Wake-up priority"
1397 depends on PM_BFIN_WAKE_PG04
1400 Wake-Up priority 0(low) 1(high)
1402 config PM_BFIN_WAKE_PG13
1403 bool "Allow Wake-Up from PG13"
1404 depends on PM && BF60x
1409 config PM_BFIN_WAKE_PG13_POL
1410 int "Wake-up priority"
1411 depends on PM_BFIN_WAKE_PG13
1414 Wake-Up priority 0(low) 1(high)
1416 config PM_BFIN_WAKE_USB
1417 bool "Allow Wake-Up from (USB)"
1418 depends on PM && BF60x
1421 Enable (USB) Wake-up
1423 config PM_BFIN_WAKE_USB_POL
1424 int "Wake-up priority"
1425 depends on PM_BFIN_WAKE_USB
1428 Wake-Up priority 0(low) 1(high)
1432 menu "CPU Frequency scaling"
1434 source "drivers/cpufreq/Kconfig"
1436 config BFIN_CPU_FREQ
1439 select CPU_FREQ_TABLE
1443 bool "CPU Voltage scaling"
1444 depends on EXPERIMENTAL
1448 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1449 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1450 manuals. There is a theoretical risk that during VDDINT transitions
1455 source "net/Kconfig"
1457 source "drivers/Kconfig"
1459 source "drivers/firmware/Kconfig"
1463 source "arch/blackfin/Kconfig.debug"
1465 source "security/Kconfig"
1467 source "crypto/Kconfig"
1469 source "lib/Kconfig"