7 config RWSEM_GENERIC_SPINLOCK
10 config RWSEM_XCHGADD_ALGORITHM
16 select HAVE_ARCH_TRACEHOOK
17 select HAVE_DYNAMIC_FTRACE
18 select HAVE_FTRACE_MCOUNT_RECORD
19 select HAVE_FUNCTION_GRAPH_TRACER
20 select HAVE_FUNCTION_TRACER
21 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
23 select HAVE_KERNEL_GZIP if RAMKERNEL
24 select HAVE_KERNEL_BZIP2 if RAMKERNEL
25 select HAVE_KERNEL_LZMA if RAMKERNEL
26 select HAVE_KERNEL_LZO if RAMKERNEL
28 select HAVE_PERF_EVENTS
29 select ARCH_HAVE_CUSTOM_GPIO_H
30 select ARCH_WANT_OPTIONAL_GPIOLIB
32 select HAVE_UNDERSCORE_SYMBOL_PREFIX
34 select ARCH_WANT_IPC_PARSE_VERSION
35 select HAVE_GENERIC_HARDIRQS
36 select GENERIC_ATOMIC64
37 select GENERIC_IRQ_PROBE
38 select USE_GENERIC_SMP_HELPERS if SMP
39 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
40 select GENERIC_SMP_IDLE_THREAD
41 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
42 select HAVE_MOD_ARCH_SPECIFIC
43 select MODULES_USE_ELF_RELA
58 config FORCE_MAX_ZONEORDER
62 config GENERIC_CALIBRATE_DELAY
65 config LOCKDEP_SUPPORT
68 config STACKTRACE_SUPPORT
71 config TRACE_IRQFLAGS_SUPPORT
76 source "kernel/Kconfig.preempt"
78 source "kernel/Kconfig.freezer"
80 menu "Blackfin Processor Options"
82 comment "Processor and Board Settings"
91 BF512 Processor Support.
96 BF514 Processor Support.
101 BF516 Processor Support.
106 BF518 Processor Support.
111 BF522 Processor Support.
116 BF523 Processor Support.
121 BF524 Processor Support.
126 BF525 Processor Support.
131 BF526 Processor Support.
136 BF527 Processor Support.
141 BF531 Processor Support.
146 BF532 Processor Support.
151 BF533 Processor Support.
156 BF534 Processor Support.
161 BF536 Processor Support.
166 BF537 Processor Support.
171 BF538 Processor Support.
176 BF539 Processor Support.
181 BF542 Processor Support.
186 BF542 Processor Support.
191 BF544 Processor Support.
196 BF544 Processor Support.
201 BF547 Processor Support.
206 BF547 Processor Support.
211 BF548 Processor Support.
216 BF548 Processor Support.
221 BF549 Processor Support.
226 BF549 Processor Support.
231 BF561 Processor Support.
237 BF609 Processor Support.
243 select TICKSOURCE_CORETMR
244 bool "Symmetric multi-processing support"
246 This enables support for systems with more than one CPU,
247 like the dual core BF561. If you have a system with only one
248 CPU, say N. If you have a system with more than one CPU, say Y.
250 If you don't know what to do here, say N.
258 bool "Support for hot-pluggable CPUs"
259 depends on SMP && HOTPLUG
264 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
265 default 2 if (BF537 || BF536 || BF534)
266 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
267 default 4 if (BF538 || BF539)
271 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
272 default 3 if (BF537 || BF536 || BF534 || BF54xM)
273 default 5 if (BF561 || BF538 || BF539)
274 default 6 if (BF533 || BF532 || BF531)
278 default BF_REV_0_0 if (BF51x || BF52x || BF60x)
279 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
280 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
284 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
288 depends on (BF51x || BF52x || (BF54x && !BF54xM))
292 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
296 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
300 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
304 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
308 depends on (BF533 || BF532 || BF531)
320 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
323 config MEM_MT48LC64M4A2FB_7E
325 depends on (BFIN533_STAMP)
328 config MEM_MT48LC16M16A2TG_75
330 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
331 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
332 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
333 || BFIN527_BLUETECHNIX_CM)
336 config MEM_MT48LC32M8A2_75
338 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
341 config MEM_MT48LC8M32B2B5_7
343 depends on (BFIN561_BLUETECHNIX_CM)
346 config MEM_MT48LC32M16A2TG_75
348 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
351 config MEM_MT48H32M16LFCJ_75
353 depends on (BFIN526_EZBRD)
356 config MEM_MT47H64M16
358 depends on (BFIN609_EZKIT)
361 source "arch/blackfin/mach-bf518/Kconfig"
362 source "arch/blackfin/mach-bf527/Kconfig"
363 source "arch/blackfin/mach-bf533/Kconfig"
364 source "arch/blackfin/mach-bf561/Kconfig"
365 source "arch/blackfin/mach-bf537/Kconfig"
366 source "arch/blackfin/mach-bf538/Kconfig"
367 source "arch/blackfin/mach-bf548/Kconfig"
368 source "arch/blackfin/mach-bf609/Kconfig"
370 menu "Board customizations"
373 bool "Default bootloader kernel arguments"
376 string "Initial kernel command string"
377 depends on CMDLINE_BOOL
378 default "console=ttyBF0,57600"
380 If you don't have a boot loader capable of passing a command line string
381 to the kernel, you may specify one here. As a minimum, you should specify
382 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
385 hex "Kernel load address for booting"
387 range 0x1000 0x20000000
389 This option allows you to set the load address of the kernel.
390 This can be useful if you are on a board which has a small amount
391 of memory or you wish to reserve some memory at the beginning of
394 Note that you need to keep this value above 4k (0x1000) as this
395 memory region is used to capture NULL pointer references as well
396 as some core kernel functions.
398 config PHY_RAM_BASE_ADDRESS
399 hex "Physical RAM Base"
402 set BF609 FPGA physical SRAM base address
405 hex "Kernel ROM Base"
408 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
409 range 0x20000000 0x30000000 if (BF54x || BF561)
410 range 0xB0000000 0xC0000000 if (BF60x)
412 Make sure your ROM base does not include any file-header
413 information that is prepended to the kernel.
415 For example, the bootable U-Boot format (created with
416 mkimage) has a 64 byte header (0x40). So while the image
417 you write to flash might start at say 0x20080000, you have
418 to add 0x40 to get the kernel's ROM base as it will come
421 comment "Clock/PLL Setup"
424 int "Frequency of the crystal on the board in Hz"
425 default "10000000" if BFIN532_IP0X
426 default "11059200" if BFIN533_STAMP
427 default "24576000" if PNAV10
428 default "25000000" # most people use this
429 default "27000000" if BFIN533_EZKIT
430 default "30000000" if BFIN561_EZKIT
431 default "24000000" if BFIN527_AD7160EVAL
433 The frequency of CLKIN crystal oscillator on the board in Hz.
434 Warning: This value should match the crystal on the board. Otherwise,
435 peripherals won't work properly.
437 config BFIN_KERNEL_CLOCK
438 bool "Re-program Clocks while Kernel boots?"
441 This option decides if kernel clocks are re-programed from the
442 bootloader settings. If the clocks are not set, the SDRAM settings
443 are also not changed, and the Bootloader does 100% of the hardware
448 depends on BFIN_KERNEL_CLOCK && (!BF60x)
453 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
456 If this is set the clock will be divided by 2, before it goes to the PLL.
460 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
462 default "22" if BFIN533_EZKIT
463 default "45" if BFIN533_STAMP
464 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
465 default "22" if BFIN533_BLUETECHNIX_CM
466 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
467 default "20" if (BFIN561_EZKIT || BF609)
468 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
469 default "25" if BFIN527_AD7160EVAL
471 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
472 PLL Frequency = (Crystal Frequency) * (this setting)
475 prompt "Core Clock Divider"
476 depends on BFIN_KERNEL_CLOCK
479 This sets the frequency of the core. It can be 1, 2, 4 or 8
480 Core Frequency = (PLL frequency) / (this setting)
496 int "System Clock Divider"
497 depends on BFIN_KERNEL_CLOCK
501 This sets the frequency of the system clock (including SDRAM or DDR) on
502 !BF60x else it set the clock for system buses and provides the
503 source from which SCLK0 and SCLK1 are derived.
504 This can be between 1 and 15
505 System Clock = (PLL frequency) / (this setting)
508 int "System Clock0 Divider"
509 depends on BFIN_KERNEL_CLOCK && BF60x
513 This sets the frequency of the system clock0 for PVP and all other
514 peripherals not clocked by SCLK1.
515 This can be between 1 and 15
516 System Clock0 = (System Clock) / (this setting)
519 int "System Clock1 Divider"
520 depends on BFIN_KERNEL_CLOCK && BF60x
524 This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
525 This can be between 1 and 15
526 System Clock1 = (System Clock) / (this setting)
529 int "DDR Clock Divider"
530 depends on BFIN_KERNEL_CLOCK && BF60x
534 This sets the frequency of the DDR memory.
535 This can be between 1 and 15
536 DDR Clock = (PLL frequency) / (this setting)
539 prompt "DDR SDRAM Chip Type"
540 depends on BFIN_KERNEL_CLOCK
542 default MEM_MT46V32M16_5B
544 config MEM_MT46V32M16_6T
547 config MEM_MT46V32M16_5B
552 prompt "DDR/SDRAM Timing"
553 depends on BFIN_KERNEL_CLOCK && !BF60x
554 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
556 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
557 The calculated SDRAM timing parameters may not be 100%
558 accurate - This option is therefore marked experimental.
560 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
561 bool "Calculate Timings"
563 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
564 bool "Provide accurate Timings based on target SCLK"
566 Please consult the Blackfin Hardware Reference Manuals as well
567 as the memory device datasheet.
568 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
571 menu "Memory Init Control"
572 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
589 config MEM_EBIU_DDRQUE
606 # Max & Min Speeds for various Chips
610 default 400000000 if BF512
611 default 400000000 if BF514
612 default 400000000 if BF516
613 default 400000000 if BF518
614 default 400000000 if BF522
615 default 600000000 if BF523
616 default 400000000 if BF524
617 default 600000000 if BF525
618 default 400000000 if BF526
619 default 600000000 if BF527
620 default 400000000 if BF531
621 default 400000000 if BF532
622 default 750000000 if BF533
623 default 500000000 if BF534
624 default 400000000 if BF536
625 default 600000000 if BF537
626 default 533333333 if BF538
627 default 533333333 if BF539
628 default 600000000 if BF542
629 default 533333333 if BF544
630 default 600000000 if BF547
631 default 600000000 if BF548
632 default 533333333 if BF549
633 default 600000000 if BF561
634 default 800000000 if BF609
642 default 200000000 if BF609
649 comment "Kernel Timer/Scheduler"
651 source kernel/Kconfig.hz
653 config SET_GENERIC_CLOCKEVENTS
654 bool "Generic clock events"
656 select GENERIC_CLOCKEVENTS
658 menu "Clock event device"
659 depends on GENERIC_CLOCKEVENTS
660 config TICKSOURCE_GPTMR0
665 config TICKSOURCE_CORETMR
671 depends on GENERIC_CLOCKEVENTS
672 config CYCLES_CLOCKSOURCE
675 depends on !BFIN_SCRATCH_REG_CYCLES
678 If you say Y here, you will enable support for using the 'cycles'
679 registers as a clock source. Doing so means you will be unable to
680 safely write to the 'cycles' register during runtime. You will
681 still be able to read it (such as for performance monitoring), but
682 writing the registers will most likely crash the kernel.
684 config GPTMR0_CLOCKSOURCE
687 depends on !TICKSOURCE_GPTMR0
693 prompt "Blackfin Exception Scratch Register"
694 default BFIN_SCRATCH_REG_RETN
696 Select the resource to reserve for the Exception handler:
697 - RETN: Non-Maskable Interrupt (NMI)
698 - RETE: Exception Return (JTAG/ICE)
699 - CYCLES: Performance counter
701 If you are unsure, please select "RETN".
703 config BFIN_SCRATCH_REG_RETN
706 Use the RETN register in the Blackfin exception handler
707 as a stack scratch register. This means you cannot
708 safely use NMI on the Blackfin while running Linux, but
709 you can debug the system with a JTAG ICE and use the
710 CYCLES performance registers.
712 If you are unsure, please select "RETN".
714 config BFIN_SCRATCH_REG_RETE
717 Use the RETE register in the Blackfin exception handler
718 as a stack scratch register. This means you cannot
719 safely use a JTAG ICE while debugging a Blackfin board,
720 but you can safely use the CYCLES performance registers
723 If you are unsure, please select "RETN".
725 config BFIN_SCRATCH_REG_CYCLES
728 Use the CYCLES register in the Blackfin exception handler
729 as a stack scratch register. This means you cannot
730 safely use the CYCLES performance registers on a Blackfin
731 board at anytime, but you can debug the system with a JTAG
734 If you are unsure, please select "RETN".
741 menu "Blackfin Kernel Optimizations"
743 comment "Memory Optimizations"
746 bool "Locate interrupt entry code in L1 Memory"
750 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
751 into L1 instruction memory. (less latency)
753 config EXCPT_IRQ_SYSC_L1
754 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
758 If enabled, the entire ASM lowlevel exception and interrupt entry code
759 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
763 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
767 If enabled, the frequently called do_irq dispatcher function is linked
768 into L1 instruction memory. (less latency)
770 config CORE_TIMER_IRQ_L1
771 bool "Locate frequently called timer_interrupt() function in L1 Memory"
775 If enabled, the frequently called timer_interrupt() function is linked
776 into L1 instruction memory. (less latency)
779 bool "Locate frequently idle function in L1 Memory"
783 If enabled, the frequently called idle function is linked
784 into L1 instruction memory. (less latency)
787 bool "Locate kernel schedule function in L1 Memory"
791 If enabled, the frequently called kernel schedule is linked
792 into L1 instruction memory. (less latency)
794 config ARITHMETIC_OPS_L1
795 bool "Locate kernel owned arithmetic functions in L1 Memory"
799 If enabled, arithmetic functions are linked
800 into L1 instruction memory. (less latency)
803 bool "Locate access_ok function in L1 Memory"
807 If enabled, the access_ok function is linked
808 into L1 instruction memory. (less latency)
811 bool "Locate memset function in L1 Memory"
815 If enabled, the memset function is linked
816 into L1 instruction memory. (less latency)
819 bool "Locate memcpy function in L1 Memory"
823 If enabled, the memcpy function is linked
824 into L1 instruction memory. (less latency)
827 bool "locate strcmp function in L1 Memory"
831 If enabled, the strcmp function is linked
832 into L1 instruction memory (less latency).
835 bool "locate strncmp function in L1 Memory"
839 If enabled, the strncmp function is linked
840 into L1 instruction memory (less latency).
843 bool "locate strcpy function in L1 Memory"
847 If enabled, the strcpy function is linked
848 into L1 instruction memory (less latency).
851 bool "locate strncpy function in L1 Memory"
855 If enabled, the strncpy function is linked
856 into L1 instruction memory (less latency).
858 config SYS_BFIN_SPINLOCK_L1
859 bool "Locate sys_bfin_spinlock function in L1 Memory"
863 If enabled, sys_bfin_spinlock function is linked
864 into L1 instruction memory. (less latency)
866 config IP_CHECKSUM_L1
867 bool "Locate IP Checksum function in L1 Memory"
871 If enabled, the IP Checksum function is linked
872 into L1 instruction memory. (less latency)
874 config CACHELINE_ALIGNED_L1
875 bool "Locate cacheline_aligned data to L1 Data Memory"
878 depends on !SMP && !BF531 && !CRC32
880 If enabled, cacheline_aligned data is linked
881 into L1 data memory. (less latency)
883 config SYSCALL_TAB_L1
884 bool "Locate Syscall Table L1 Data Memory"
886 depends on !SMP && !BF531
888 If enabled, the Syscall LUT is linked
889 into L1 data memory. (less latency)
891 config CPLB_SWITCH_TAB_L1
892 bool "Locate CPLB Switch Tables L1 Data Memory"
894 depends on !SMP && !BF531
896 If enabled, the CPLB Switch Tables are linked
897 into L1 data memory. (less latency)
899 config ICACHE_FLUSH_L1
900 bool "Locate icache flush funcs in L1 Inst Memory"
903 If enabled, the Blackfin icache flushing functions are linked
904 into L1 instruction memory.
906 Note that this might be required to address anomalies, but
907 these functions are pretty small, so it shouldn't be too bad.
908 If you are using a processor affected by an anomaly, the build
909 system will double check for you and prevent it.
911 config DCACHE_FLUSH_L1
912 bool "Locate dcache flush funcs in L1 Inst Memory"
916 If enabled, the Blackfin dcache flushing functions are linked
917 into L1 instruction memory.
920 bool "Support locating application stack in L1 Scratch Memory"
924 If enabled the application stack can be located in L1
925 scratch memory (less latency).
927 Currently only works with FLAT binaries.
929 config EXCEPTION_L1_SCRATCH
930 bool "Locate exception stack in L1 Scratch Memory"
932 depends on !SMP && !APP_STACK_L1
934 Whenever an exception occurs, use the L1 Scratch memory for
935 stack storage. You cannot place the stacks of FLAT binaries
936 in L1 when using this option.
938 If you don't use L1 Scratch, then you should say Y here.
940 comment "Speed Optimizations"
941 config BFIN_INS_LOWOVERHEAD
942 bool "ins[bwl] low overhead, higher interrupt latency"
946 Reads on the Blackfin are speculative. In Blackfin terms, this means
947 they can be interrupted at any time (even after they have been issued
948 on to the external bus), and re-issued after the interrupt occurs.
949 For memory - this is not a big deal, since memory does not change if
952 If a FIFO is sitting on the end of the read, it will see two reads,
953 when the core only sees one since the FIFO receives both the read
954 which is cancelled (and not delivered to the core) and the one which
955 is re-issued (which is delivered to the core).
957 To solve this, interrupts are turned off before reads occur to
958 I/O space. This option controls which the overhead/latency of
959 controlling interrupts during this time
960 "n" turns interrupts off every read
961 (higher overhead, but lower interrupt latency)
962 "y" turns interrupts off every loop
963 (low overhead, but longer interrupt latency)
965 default behavior is to leave this set to on (type "Y"). If you are experiencing
966 interrupt latency issues, it is safe and OK to turn this off.
971 prompt "Kernel executes from"
973 Choose the memory type that the kernel will be running in.
978 The kernel will be resident in RAM when running.
983 The kernel will be resident in FLASH/ROM when running.
987 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
996 tristate "Enable Blackfin General Purpose Timers API"
999 Enable support for the General Purpose Timers API. If you
1002 To compile this driver as a module, choose M here: the module
1003 will be called gptimers.
1006 prompt "Uncached DMA region"
1007 default DMA_UNCACHED_1M
1008 config DMA_UNCACHED_32M
1009 bool "Enable 32M DMA region"
1010 config DMA_UNCACHED_16M
1011 bool "Enable 16M DMA region"
1012 config DMA_UNCACHED_8M
1013 bool "Enable 8M DMA region"
1014 config DMA_UNCACHED_4M
1015 bool "Enable 4M DMA region"
1016 config DMA_UNCACHED_2M
1017 bool "Enable 2M DMA region"
1018 config DMA_UNCACHED_1M
1019 bool "Enable 1M DMA region"
1020 config DMA_UNCACHED_512K
1021 bool "Enable 512K DMA region"
1022 config DMA_UNCACHED_256K
1023 bool "Enable 256K DMA region"
1024 config DMA_UNCACHED_128K
1025 bool "Enable 128K DMA region"
1026 config DMA_UNCACHED_NONE
1027 bool "Disable DMA region"
1031 comment "Cache Support"
1034 bool "Enable ICACHE"
1036 config BFIN_EXTMEM_ICACHEABLE
1037 bool "Enable ICACHE for external memory"
1038 depends on BFIN_ICACHE
1040 config BFIN_L2_ICACHEABLE
1041 bool "Enable ICACHE for L2 SRAM"
1042 depends on BFIN_ICACHE
1043 depends on (BF54x || BF561 || BF60x) && !SMP
1047 bool "Enable DCACHE"
1049 config BFIN_DCACHE_BANKA
1050 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1051 depends on BFIN_DCACHE && !BF531
1053 config BFIN_EXTMEM_DCACHEABLE
1054 bool "Enable DCACHE for external memory"
1055 depends on BFIN_DCACHE
1058 prompt "External memory DCACHE policy"
1059 depends on BFIN_EXTMEM_DCACHEABLE
1060 default BFIN_EXTMEM_WRITEBACK if !SMP
1061 default BFIN_EXTMEM_WRITETHROUGH if SMP
1062 config BFIN_EXTMEM_WRITEBACK
1067 Cached data will be written back to SDRAM only when needed.
1068 This can give a nice increase in performance, but beware of
1069 broken drivers that do not properly invalidate/flush their
1072 Write Through Policy:
1073 Cached data will always be written back to SDRAM when the
1074 cache is updated. This is a completely safe setting, but
1075 performance is worse than Write Back.
1077 If you are unsure of the options and you want to be safe,
1078 then go with Write Through.
1080 config BFIN_EXTMEM_WRITETHROUGH
1081 bool "Write through"
1084 Cached data will be written back to SDRAM only when needed.
1085 This can give a nice increase in performance, but beware of
1086 broken drivers that do not properly invalidate/flush their
1089 Write Through Policy:
1090 Cached data will always be written back to SDRAM when the
1091 cache is updated. This is a completely safe setting, but
1092 performance is worse than Write Back.
1094 If you are unsure of the options and you want to be safe,
1095 then go with Write Through.
1099 config BFIN_L2_DCACHEABLE
1100 bool "Enable DCACHE for L2 SRAM"
1101 depends on BFIN_DCACHE
1102 depends on (BF54x || BF561 || BF60x) && !SMP
1105 prompt "L2 SRAM DCACHE policy"
1106 depends on BFIN_L2_DCACHEABLE
1107 default BFIN_L2_WRITEBACK
1108 config BFIN_L2_WRITEBACK
1111 config BFIN_L2_WRITETHROUGH
1112 bool "Write through"
1116 comment "Memory Protection Unit"
1118 bool "Enable the memory protection unit"
1121 Use the processor's MPU to protect applications from accessing
1122 memory they do not own. This comes at a performance penalty
1123 and is recommended only for debugging.
1125 comment "Asynchronous Memory Configuration"
1127 menu "EBIU_AMGCTL Global Control"
1130 bool "Enable CLKOUT"
1134 bool "DMA has priority over core for ext. accesses"
1139 bool "Bank 0 16 bit packing enable"
1144 bool "Bank 1 16 bit packing enable"
1149 bool "Bank 2 16 bit packing enable"
1154 bool "Bank 3 16 bit packing enable"
1158 prompt "Enable Asynchronous Memory Banks"
1162 bool "Disable All Banks"
1165 bool "Enable Bank 0"
1167 config C_AMBEN_B0_B1
1168 bool "Enable Bank 0 & 1"
1170 config C_AMBEN_B0_B1_B2
1171 bool "Enable Bank 0 & 1 & 2"
1174 bool "Enable All Banks"
1178 menu "EBIU_AMBCTL Control"
1181 hex "Bank 0 (AMBCTL0.L)"
1184 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1185 used to control the Asynchronous Memory Bank 0 settings.
1188 hex "Bank 1 (AMBCTL0.H)"
1190 default 0x5558 if BF54x
1192 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1193 used to control the Asynchronous Memory Bank 1 settings.
1196 hex "Bank 2 (AMBCTL1.L)"
1199 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1200 used to control the Asynchronous Memory Bank 2 settings.
1203 hex "Bank 3 (AMBCTL1.H)"
1206 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1207 used to control the Asynchronous Memory Bank 3 settings.
1211 config EBIU_MBSCTLVAL
1212 hex "EBIU Bank Select Control Register"
1217 hex "Flash Memory Mode Control Register"
1222 hex "Flash Memory Bank Control Register"
1227 #############################################################################
1228 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1234 Support for PCI bus.
1236 source "drivers/pci/Kconfig"
1238 source "drivers/pcmcia/Kconfig"
1240 source "drivers/pci/hotplug/Kconfig"
1244 menu "Executable file formats"
1246 source "fs/Kconfig.binfmt"
1250 menu "Power management options"
1252 source "kernel/power/Kconfig"
1254 config ARCH_SUSPEND_POSSIBLE
1258 prompt "Standby Power Saving Mode"
1259 depends on PM && !BF60x
1260 default PM_BFIN_SLEEP_DEEPER
1261 config PM_BFIN_SLEEP_DEEPER
1264 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1265 power dissipation by disabling the clock to the processor core (CCLK).
1266 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1267 to 0.85 V to provide the greatest power savings, while preserving the
1269 The PLL and system clock (SCLK) continue to operate at a very low
1270 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1271 the SDRAM is put into Self Refresh Mode. Typically an external event
1272 such as GPIO interrupt or RTC activity wakes up the processor.
1273 Various Peripherals such as UART, SPORT, PPI may not function as
1274 normal during Sleep Deeper, due to the reduced SCLK frequency.
1275 When in the sleep mode, system DMA access to L1 memory is not supported.
1277 If unsure, select "Sleep Deeper".
1279 config PM_BFIN_SLEEP
1282 Sleep Mode (High Power Savings) - The sleep mode reduces power
1283 dissipation by disabling the clock to the processor core (CCLK).
1284 The PLL and system clock (SCLK), however, continue to operate in
1285 this mode. Typically an external event or RTC activity will wake
1286 up the processor. When in the sleep mode, system DMA access to L1
1287 memory is not supported.
1289 If unsure, select "Sleep Deeper".
1292 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1295 config PM_BFIN_WAKE_PH6
1296 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1297 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1300 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1302 config PM_BFIN_WAKE_GP
1303 bool "Allow Wake-Up from GPIOs"
1304 depends on PM && BF54x
1307 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1308 (all processors, except ADSP-BF549). This option sets
1309 the general-purpose wake-up enable (GPWE) control bit to enable
1310 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1311 On ADSP-BF549 this option enables the same functionality on the
1312 /MRXON pin also PH7.
1314 config PM_BFIN_WAKE_PA15
1315 bool "Allow Wake-Up from PA15"
1316 depends on PM && BF60x
1321 config PM_BFIN_WAKE_PA15_POL
1322 int "Wake-up priority"
1323 depends on PM_BFIN_WAKE_PA15
1326 Wake-Up priority 0(low) 1(high)
1328 config PM_BFIN_WAKE_PB15
1329 bool "Allow Wake-Up from PB15"
1330 depends on PM && BF60x
1335 config PM_BFIN_WAKE_PB15_POL
1336 int "Wake-up priority"
1337 depends on PM_BFIN_WAKE_PB15
1340 Wake-Up priority 0(low) 1(high)
1342 config PM_BFIN_WAKE_PC15
1343 bool "Allow Wake-Up from PC15"
1344 depends on PM && BF60x
1349 config PM_BFIN_WAKE_PC15_POL
1350 int "Wake-up priority"
1351 depends on PM_BFIN_WAKE_PC15
1354 Wake-Up priority 0(low) 1(high)
1356 config PM_BFIN_WAKE_PD06
1357 bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1358 depends on PM && BF60x
1361 Enable PD06(ETH0_PHYINT) Wake-up
1363 config PM_BFIN_WAKE_PD06_POL
1364 int "Wake-up priority"
1365 depends on PM_BFIN_WAKE_PD06
1368 Wake-Up priority 0(low) 1(high)
1370 config PM_BFIN_WAKE_PE12
1371 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1372 depends on PM && BF60x
1375 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1377 config PM_BFIN_WAKE_PE12_POL
1378 int "Wake-up priority"
1379 depends on PM_BFIN_WAKE_PE12
1382 Wake-Up priority 0(low) 1(high)
1384 config PM_BFIN_WAKE_PG04
1385 bool "Allow Wake-Up from PG04(CAN0_RX)"
1386 depends on PM && BF60x
1389 Enable PG04(CAN0_RX) Wake-up
1391 config PM_BFIN_WAKE_PG04_POL
1392 int "Wake-up priority"
1393 depends on PM_BFIN_WAKE_PG04
1396 Wake-Up priority 0(low) 1(high)
1398 config PM_BFIN_WAKE_PG13
1399 bool "Allow Wake-Up from PG13"
1400 depends on PM && BF60x
1405 config PM_BFIN_WAKE_PG13_POL
1406 int "Wake-up priority"
1407 depends on PM_BFIN_WAKE_PG13
1410 Wake-Up priority 0(low) 1(high)
1412 config PM_BFIN_WAKE_USB
1413 bool "Allow Wake-Up from (USB)"
1414 depends on PM && BF60x
1417 Enable (USB) Wake-up
1419 config PM_BFIN_WAKE_USB_POL
1420 int "Wake-up priority"
1421 depends on PM_BFIN_WAKE_USB
1424 Wake-Up priority 0(low) 1(high)
1428 menu "CPU Frequency scaling"
1430 source "drivers/cpufreq/Kconfig"
1432 config BFIN_CPU_FREQ
1435 select CPU_FREQ_TABLE
1439 bool "CPU Voltage scaling"
1443 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1444 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1445 manuals. There is a theoretical risk that during VDDINT transitions
1450 source "net/Kconfig"
1452 source "drivers/Kconfig"
1454 source "drivers/firmware/Kconfig"
1458 source "arch/blackfin/Kconfig.debug"
1460 source "security/Kconfig"
1462 source "crypto/Kconfig"
1464 source "lib/Kconfig"