2 * bfin_serial.h - Blackfin UART/Serial definitions
4 * Copyright 2006-2010 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #ifndef __BFIN_ASM_SERIAL_H__
10 #define __BFIN_ASM_SERIAL_H__
12 #include <linux/serial_core.h>
13 #include <linux/spinlock.h>
14 #include <mach/anomaly.h>
15 #include <mach/bfin_serial.h>
17 #if defined(CONFIG_BFIN_UART0_CTSRTS) || \
18 defined(CONFIG_BFIN_UART1_CTSRTS) || \
19 defined(CONFIG_BFIN_UART2_CTSRTS) || \
20 defined(CONFIG_BFIN_UART3_CTSRTS)
21 # if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
22 # define CONFIG_SERIAL_BFIN_HARD_CTSRTS
24 # define CONFIG_SERIAL_BFIN_CTSRTS
32 struct bfin_serial_port {
33 struct uart_port port;
34 unsigned int old_status;
38 #ifndef BFIN_UART_BF54X_STYLE
41 #ifdef CONFIG_SERIAL_BFIN_DMA
44 struct circ_buf rx_dma_buf;
45 struct timer_list rx_dma_timer;
48 unsigned int tx_dma_channel;
49 unsigned int rx_dma_channel;
50 struct work_struct tx_dma_workqueue;
51 #elif ANOMALY_05000363
52 unsigned int anomaly_threshold;
54 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
55 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
61 #ifdef BFIN_UART_BF60X_STYLE
64 #define UCEN 0x1 /* Enable UARTx Clocks */
65 #define LOOP_ENA 0x2 /* Loopback Mode Enable */
66 #define UMOD_MDB 0x10 /* Enable MDB Mode */
67 #define UMOD_IRDA 0x20 /* Enable IrDA Mode */
68 #define UMOD_MASK 0x30 /* Uart Mode Mask */
69 #define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */
70 #define WLS_MASK 0x300 /* Word length Select Mask */
71 #define STB 0x1000 /* Stop Bits */
72 #define STBH 0x2000 /* Half Stop Bits */
73 #define PEN 0x4000 /* Parity Enable */
74 #define EPS 0x8000 /* Even Parity Select */
75 #define STP 0x10000 /* Stick Parity */
76 #define FPE 0x20000 /* Force Parity Error On Transmit */
77 #define FFE 0x40000 /* Force Framing Error On Transmit */
78 #define SB 0x80000 /* Set Break */
79 #define LCR_MASK (STP | EPS | PEN | STB | WLS_MASK)
80 #define FCPOL 0x400000 /* Flow Control Pin Polarity */
81 #define RPOLC 0x800000 /* IrDA RX Polarity Change */
82 #define TPOLC 0x1000000 /* IrDA TX Polarity Change */
83 #define MRTS 0x2000000 /* Manual Request To Send */
84 #define XOFF 0x4000000 /* Transmitter Off */
85 #define ARTS 0x8000000 /* Automatic Request To Send */
86 #define ACTS 0x10000000 /* Automatic Clear To Send */
87 #define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */
88 #define RFRT 0x40000000 /* Receive FIFO RTS Threshold */
91 #define DR 0x01 /* Data Ready */
92 #define OE 0x02 /* Overrun Error */
93 #define PE 0x04 /* Parity Error */
94 #define FE 0x08 /* Framing Error */
95 #define BI 0x10 /* Break Interrupt */
96 #define THRE 0x20 /* THR Empty */
97 #define TEMT 0x80 /* TSR and UART_THR Empty */
98 #define TFI 0x100 /* Transmission Finished Indicator */
100 #define ASTKY 0x200 /* Address Sticky */
101 #define ADDR 0x400 /* Address bit status */
102 #define RO 0x800 /* Reception Ongoing */
103 #define SCTS 0x1000 /* Sticky CTS */
104 #define CTS 0x10000 /* Clear To Send */
105 #define RFCS 0x20000 /* Receive FIFO Count Status */
107 /* UART_CLOCK Masks */
108 #define EDBO 0x80000000 /* Enable Devide by One */
110 #else /* BFIN_UART_BF60X_STYLE */
113 #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
114 #define WLS_MASK 0x03 /* Word length Select Mask */
115 #define STB 0x04 /* Stop Bits */
116 #define PEN 0x08 /* Parity Enable */
117 #define EPS 0x10 /* Even Parity Select */
118 #define STP 0x20 /* Stick Parity */
119 #define SB 0x40 /* Set Break */
120 #define DLAB 0x80 /* Divisor Latch Access */
121 #define LCR_MASK (STP | EPS | PEN | STB | WLS_MASK)
124 #define DR 0x01 /* Data Ready */
125 #define OE 0x02 /* Overrun Error */
126 #define PE 0x04 /* Parity Error */
127 #define FE 0x08 /* Framing Error */
128 #define BI 0x10 /* Break Interrupt */
129 #define THRE 0x20 /* THR Empty */
130 #define TEMT 0x40 /* TSR and UART_THR Empty */
131 #define TFI 0x80 /* Transmission Finished Indicator */
134 #define XOFF 0x01 /* Transmitter Off */
135 #define MRTS 0x02 /* Manual Request To Send */
136 #define RFIT 0x04 /* Receive FIFO IRQ Threshold */
137 #define RFRT 0x08 /* Receive FIFO RTS Threshold */
138 #define LOOP_ENA 0x10 /* Loopback Mode Enable */
139 #define FCPOL 0x20 /* Flow Control Pin Polarity */
140 #define ARTS 0x40 /* Automatic Request To Send */
141 #define ACTS 0x80 /* Automatic Clear To Send */
144 #define SCTS 0x01 /* Sticky CTS */
145 #define CTS 0x10 /* Clear To Send */
146 #define RFCS 0x20 /* Receive FIFO Count Status */
148 /* UART_GCTL Masks */
149 #define UCEN 0x01 /* Enable UARTx Clocks */
150 #define UMOD_IRDA 0x02 /* Enable IrDA Mode */
151 #define UMOD_MASK 0x02 /* Uart Mode Mask */
152 #define TPOLC 0x04 /* IrDA TX Polarity Change */
153 #define RPOLC 0x08 /* IrDA RX Polarity Change */
154 #define FPE 0x10 /* Force Parity Error On Transmit */
155 #define FFE 0x20 /* Force Framing Error On Transmit */
157 #endif /* BFIN_UART_BF60X_STYLE */
160 #define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
161 #define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
162 #define ELSI 0x04 /* Enable RX Status Interrupt */
163 #define EDSSI 0x08 /* Enable Modem Status Interrupt */
164 #define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
165 #define ETFI 0x20 /* Enable Transmission Finished Interrupt */
166 #define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
168 #if defined(BFIN_UART_BF60X_STYLE)
169 # define OFFSET_REDIV 0x00 /* Version ID Register */
170 # define OFFSET_CTL 0x04 /* Control Register */
171 # define OFFSET_STAT 0x08 /* Status Register */
172 # define OFFSET_SCR 0x0C /* SCR Scratch Register */
173 # define OFFSET_CLK 0x10 /* Clock Rate Register */
174 # define OFFSET_IER 0x14 /* Interrupt Enable Register */
175 # define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */
176 # define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */
177 # define OFFSET_RBR 0x20 /* Receive Buffer register */
178 # define OFFSET_THR 0x24 /* Transmit Holding register */
179 #elif defined(BFIN_UART_BF54X_STYLE)
180 # define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
181 # define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
182 # define OFFSET_GCTL 0x08 /* Global Control Register */
183 # define OFFSET_LCR 0x0C /* Line Control Register */
184 # define OFFSET_MCR 0x10 /* Modem Control Register */
185 # define OFFSET_LSR 0x14 /* Line Status Register */
186 # define OFFSET_MSR 0x18 /* Modem Status Register */
187 # define OFFSET_SCR 0x1C /* SCR Scratch Register */
188 # define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
189 # define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
190 # define OFFSET_THR 0x28 /* Transmit Holding register */
191 # define OFFSET_RBR 0x2C /* Receive Buffer register */
192 #else /* BF533 style */
193 # define OFFSET_THR 0x00 /* Transmit Holding register */
194 # define OFFSET_RBR 0x00 /* Receive Buffer register */
195 # define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
196 # define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
197 # define OFFSET_IER 0x04 /* Interrupt Enable Register */
198 # define OFFSET_IIR 0x08 /* Interrupt Identification Register */
199 # define OFFSET_LCR 0x0C /* Line Control Register */
200 # define OFFSET_MCR 0x10 /* Modem Control Register */
201 # define OFFSET_LSR 0x14 /* Line Status Register */
202 # define OFFSET_MSR 0x18 /* Modem Status Register */
203 # define OFFSET_SCR 0x1C /* SCR Scratch Register */
204 # define OFFSET_GCTL 0x24 /* Global Control Register */
205 /* code should not need IIR, so force build error if they use it */
210 * All Blackfin system MMRs are padded to 32bits even if the register
211 * itself is only 16bits. So use a helper macro to streamline this.
213 #define __BFP(m) u16 m; u16 __pad_##m
214 struct bfin_uart_regs {
215 #if defined(BFIN_UART_BF60X_STYLE)
231 #elif defined(BFIN_UART_BF54X_STYLE)
268 #define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
272 # define port_membase(p) 0
275 #ifdef BFIN_UART_BF60X_STYLE
277 #define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR)
278 #define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK)
279 #define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL)
280 #define UART_GET_GCTL(p) UART_GET_CTL(p)
281 #define UART_GET_LCR(p) UART_GET_CTL(p)
282 #define UART_GET_MCR(p) UART_GET_CTL(p)
283 #define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT)
284 #define UART_GET_MSR(p) UART_GET_STAT(p)
286 #define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v)
287 #define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v)
288 #define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v)
289 #define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v)
290 #define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v)
291 #define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v)
292 #define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v)
294 #define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
295 #define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER)
296 #define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
298 #define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */
299 #define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */
301 #define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1)
302 #define UART_GET_LSR(p) UART_GET_STAT(p)
303 #define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v)
305 /* This handles hard CTS/RTS */
306 #define BFIN_UART_CTSRTS_HARD
307 #define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS)
308 #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
309 #define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
310 #define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
311 #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
312 #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
314 #else /* BFIN_UART_BF60X_STYLE */
316 #define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
317 #define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
318 #define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
319 #define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
320 #define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
321 #define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
322 #define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
323 #define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
325 #define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
326 #define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
327 #define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
328 #define UART_PUT_CLK(p, v) do \
330 UART_PUT_DLL(p, v & 0xFF); \
331 UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
333 #define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
334 #define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
335 #define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
337 #ifdef BFIN_UART_BF54X_STYLE
339 #define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
340 #define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
341 #define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
343 #define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
344 #define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
346 #define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
347 #define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
348 #define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
350 /* This handles hard CTS/RTS */
351 #define BFIN_UART_CTSRTS_HARD
352 #define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
353 #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
354 #define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
355 #define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
356 #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
357 #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
359 #else /* BF533 style */
361 #define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
362 #define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
363 #define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
364 #define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v))
366 #define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
367 #define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
369 #define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
370 #define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
373 #ifndef put_lsr_cache
374 # define put_lsr_cache(p, v)
376 #ifndef get_lsr_cache
377 # define get_lsr_cache(p) 0
381 /* The hardware clears the LSR bits upon read, so we need to cache
382 * some of the more fun bits in software so they don't get lost
383 * when checking the LSR in other code paths (TX).
385 static inline void UART_CLEAR_LSR(void *p)
388 bfin_write16(port_membase(p) + OFFSET_LSR, -1);
390 static inline unsigned int UART_GET_LSR(void *p)
392 unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
393 put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
394 return lsr | get_lsr_cache(p);
396 static inline void UART_PUT_LSR(void *p, uint16_t val)
398 put_lsr_cache(p, get_lsr_cache(p) & ~val);
401 /* This handles soft CTS/RTS */
402 #define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
403 #define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
404 #define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
405 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
406 #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
408 #endif /* BFIN_UART_BF54X_STYLE */
410 #endif /* BFIN_UART_BF60X_STYLE */
412 #ifndef BFIN_UART_TX_FIFO_SIZE
413 # define BFIN_UART_TX_FIFO_SIZE 2
416 #endif /* __BFIN_ASM_SERIAL_H__ */