2 * dma.h - Blackfin DMA defines/structures/etc...
4 * Copyright 2004-2008 Analog Devices Inc.
5 * Licensed under the GPL-2 or later.
8 #ifndef _BLACKFIN_DMA_H_
9 #define _BLACKFIN_DMA_H_
11 #include <linux/interrupt.h>
13 #include <asm/atomic.h>
14 #include <asm/blackfin.h>
16 #include <asm-generic/dma.h>
18 /* DMA_CONFIG Masks */
19 #define DMAEN 0x0001 /* DMA Channel Enable */
20 #define WNR 0x0002 /* Channel Direction (W/R*) */
21 #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
22 #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
23 #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
24 #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
25 #define RESTART 0x0020 /* DMA Buffer Clear */
26 #define DI_SEL 0x0040 /* Data Interrupt Timing Select */
27 #define DI_EN 0x0080 /* Data Interrupt Enable */
28 #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
29 #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
30 #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
31 #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
32 #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
33 #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
34 #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
35 #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
36 #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
37 #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
38 #define NDSIZE 0x0f00 /* Next Descriptor Size */
39 #define DMAFLOW 0x7000 /* Flow Control */
40 #define DMAFLOW_STOP 0x0000 /* Stop Mode */
41 #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
42 #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
43 #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
44 #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
46 /* DMA_IRQ_STATUS Masks */
47 #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
48 #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
49 #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
50 #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
52 /*-------------------------
53 * config reg bits value
54 *-------------------------*/
56 #define DATA_SIZE_16 1
57 #define DATA_SIZE_32 2
59 #define DMA_FLOW_STOP 0
60 #define DMA_FLOW_AUTO 1
61 #define DMA_FLOW_ARRAY 4
62 #define DMA_FLOW_SMALL 6
63 #define DMA_FLOW_LARGE 7
65 #define DIMENSION_LINEAR 0
66 #define DIMENSION_2D 1
71 #define INTR_DISABLE 0
75 #define DMA_NOSYNC_KEEP_DMA_BUF 0
76 #define DMA_SYNC_RESTART 1
80 unsigned long start_addr;
82 unsigned short x_count;
84 unsigned short y_count;
86 } __attribute__((packed));
89 void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
90 unsigned long start_addr; /* DMA Start address register */
92 unsigned short cfg; /* DMA Configuration register */
93 unsigned short dummy1; /* DMA Configuration register */
95 unsigned long reserved;
97 unsigned short x_count; /* DMA x_count register */
98 unsigned short dummy2;
100 short x_modify; /* DMA x_modify register */
101 unsigned short dummy3;
103 unsigned short y_count; /* DMA y_count register */
104 unsigned short dummy4;
106 short y_modify; /* DMA y_modify register */
107 unsigned short dummy5;
109 void *curr_desc_ptr; /* DMA Current Descriptor Pointer
111 unsigned long curr_addr_ptr; /* DMA Current Address Pointer
113 unsigned short irq_status; /* DMA irq status register */
114 unsigned short dummy6;
116 unsigned short peripheral_map; /* DMA peripheral map register */
117 unsigned short dummy7;
119 unsigned short curr_x_count; /* DMA Current x-count register */
120 unsigned short dummy8;
122 unsigned long reserved2;
124 unsigned short curr_y_count; /* DMA Current y-count register */
125 unsigned short dummy9;
127 unsigned long reserved3;
132 const char *device_id;
133 atomic_t chan_status;
134 volatile struct dma_register *regs;
135 struct dmasg *sg; /* large mode descriptor */
139 unsigned short saved_peripheral_map;
144 int blackfin_dma_suspend(void);
145 void blackfin_dma_resume(void);
148 /*******************************************************************************
150 *******************************************************************************/
151 extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
152 extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS];
153 extern int channel2irq(unsigned int channel);
155 static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
157 dma_ch[channel].regs->start_addr = addr;
159 static inline void set_dma_next_desc_addr(unsigned int channel, void *addr)
161 dma_ch[channel].regs->next_desc_ptr = addr;
163 static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
165 dma_ch[channel].regs->curr_desc_ptr = addr;
167 static inline void set_dma_x_count(unsigned int channel, unsigned short x_count)
169 dma_ch[channel].regs->x_count = x_count;
171 static inline void set_dma_y_count(unsigned int channel, unsigned short y_count)
173 dma_ch[channel].regs->y_count = y_count;
175 static inline void set_dma_x_modify(unsigned int channel, short x_modify)
177 dma_ch[channel].regs->x_modify = x_modify;
179 static inline void set_dma_y_modify(unsigned int channel, short y_modify)
181 dma_ch[channel].regs->y_modify = y_modify;
183 static inline void set_dma_config(unsigned int channel, unsigned short config)
185 dma_ch[channel].regs->cfg = config;
187 static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
189 dma_ch[channel].regs->curr_addr_ptr = addr;
192 static inline unsigned short
193 set_bfin_dma_config(char direction, char flow_mode,
194 char intr_mode, char dma_mode, char width, char syncmode)
196 return (direction << 1) | (width << 2) | (dma_mode << 4) |
197 (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
200 static inline unsigned short get_dma_curr_irqstat(unsigned int channel)
202 return dma_ch[channel].regs->irq_status;
204 static inline unsigned short get_dma_curr_xcount(unsigned int channel)
206 return dma_ch[channel].regs->curr_x_count;
208 static inline unsigned short get_dma_curr_ycount(unsigned int channel)
210 return dma_ch[channel].regs->curr_y_count;
212 static inline void *get_dma_next_desc_ptr(unsigned int channel)
214 return dma_ch[channel].regs->next_desc_ptr;
216 static inline void *get_dma_curr_desc_ptr(unsigned int channel)
218 return dma_ch[channel].regs->curr_desc_ptr;
220 static inline unsigned short get_dma_config(unsigned int channel)
222 return dma_ch[channel].regs->cfg;
224 static inline unsigned long get_dma_curr_addr(unsigned int channel)
226 return dma_ch[channel].regs->curr_addr_ptr;
229 static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
231 /* Make sure the internal data buffers in the core are drained
232 * so that the DMA descriptors are completely written when the
233 * DMA engine goes to fetch them below.
237 dma_ch[channel].regs->next_desc_ptr = sg;
238 dma_ch[channel].regs->cfg =
239 (dma_ch[channel].regs->cfg & ~(0xf << 8)) |
240 ((ndsize & 0xf) << 8);
243 static inline int dma_channel_active(unsigned int channel)
245 return atomic_read(&dma_ch[channel].chan_status);
248 static inline void disable_dma(unsigned int channel)
250 dma_ch[channel].regs->cfg &= ~DMAEN;
253 static inline void enable_dma(unsigned int channel)
255 dma_ch[channel].regs->curr_x_count = 0;
256 dma_ch[channel].regs->curr_y_count = 0;
257 dma_ch[channel].regs->cfg |= DMAEN;
259 int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
261 static inline void dma_disable_irq(unsigned int channel)
263 disable_irq(dma_ch[channel].irq);
265 static inline void dma_disable_irq_nosync(unsigned int channel)
267 disable_irq_nosync(dma_ch[channel].irq);
269 static inline void dma_enable_irq(unsigned int channel)
271 enable_irq(dma_ch[channel].irq);
273 static inline void clear_dma_irqstat(unsigned int channel)
275 dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR;
278 void *dma_memcpy(void *dest, const void *src, size_t count);
279 void *dma_memcpy_nocache(void *dest, const void *src, size_t count);
280 void *safe_dma_memcpy(void *dest, const void *src, size_t count);
281 void blackfin_dma_early_init(void);
282 void early_dma_memcpy(void *dest, const void *src, size_t count);
283 void early_dma_memcpy_done(void);