2 * Copyright 2005-2010 Analog Devices Inc.
4 * Licensed under the GPL-2 or later.
7 #ifndef _MACH_COMMON_PLL_H
8 #define _MACH_COMMON_PLL_H
12 #include <asm/blackfin.h>
13 #include <asm/irqflags.h>
15 #ifndef bfin_iwr_restore
17 bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
20 bfin_write_SIC_IWR(iwr0);
22 bfin_write_SIC_IWR0(iwr0);
24 bfin_write_SIC_IWR1(iwr1);
27 bfin_write_SIC_IWR2(iwr2);
35 bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
36 unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
39 *iwr0 = bfin_read_SIC_IWR();
41 *iwr0 = bfin_read_SIC_IWR0();
43 *iwr1 = bfin_read_SIC_IWR1();
46 *iwr2 = bfin_read_SIC_IWR2();
49 bfin_iwr_restore(niwr0, niwr1, niwr2);
53 static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
55 unsigned long flags, iwr0, iwr1, iwr2;
57 if (val == bfin_read_PLL_CTL())
60 flags = hard_local_irq_save();
61 /* Enable the PLL Wakeup bit in SIC IWR */
62 bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
64 bfin_write16(addr, val);
68 bfin_iwr_restore(iwr0, iwr1, iwr2);
69 hard_local_irq_restore(flags);
72 /* Writing to PLL_CTL initiates a PLL relock sequence */
73 static inline void bfin_write_PLL_CTL(unsigned int val)
75 _bfin_write_pll_relock(PLL_CTL, val);
78 /* Writing to VR_CTL initiates a PLL relock sequence */
79 static inline void bfin_write_VR_CTL(unsigned int val)
81 _bfin_write_pll_relock(VR_CTL, val);