2 * Copyright 2005-2008 Analog Devices Inc.
4 * Licensed under the GPL-2 or later
10 #include <mach-common/irq.h>
12 #define NR_PERI_INTS 32
14 #define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
15 #define IRQ_DMA_ERROR 8 /* DMA Error (general) */
16 #define IRQ_GENERIC_ERROR 9 /* GENERIC Error Interrupt */
17 #define IRQ_RTC 10 /* RTC Interrupt */
18 #define IRQ_PPI 11 /* DMA0 Interrupt (PPI) */
19 #define IRQ_SPORT0_RX 12 /* DMA3 Interrupt (SPORT0 RX) */
20 #define IRQ_SPORT0_TX 13 /* DMA4 Interrupt (SPORT0 TX) */
21 #define IRQ_SPORT1_RX 14 /* DMA5 Interrupt (SPORT1 RX) */
22 #define IRQ_SPORT1_TX 15 /* DMA6 Interrupt (SPORT1 TX) */
23 #define IRQ_TWI 16 /* TWI Interrupt */
24 #define IRQ_SPI 17 /* DMA7 Interrupt (SPI) */
25 #define IRQ_UART0_RX 18 /* DMA8 Interrupt (UART0 RX) */
26 #define IRQ_UART0_TX 19 /* DMA9 Interrupt (UART0 TX) */
27 #define IRQ_UART1_RX 20 /* DMA10 Interrupt (UART1 RX) */
28 #define IRQ_UART1_TX 21 /* DMA11 Interrupt (UART1 TX) */
29 #define IRQ_CAN_RX 22 /* CAN Receive Interrupt */
30 #define IRQ_CAN_TX 23 /* CAN Transmit Interrupt */
31 #define IRQ_MAC_RX 24 /* DMA1 (Ethernet RX) Interrupt */
32 #define IRQ_MAC_TX 25 /* DMA2 (Ethernet TX) Interrupt */
33 #define IRQ_TIMER0 26 /* Timer 0 */
34 #define IRQ_TIMER1 27 /* Timer 1 */
35 #define IRQ_TIMER2 28 /* Timer 2 */
36 #define IRQ_TIMER3 29 /* Timer 3 */
37 #define IRQ_TIMER4 30 /* Timer 4 */
38 #define IRQ_TIMER5 31 /* Timer 5 */
39 #define IRQ_TIMER6 32 /* Timer 6 */
40 #define IRQ_TIMER7 33 /* Timer 7 */
41 #define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
42 #define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
43 #define IRQ_MEM_DMA0 36 /* (Memory DMA Stream 0) */
44 #define IRQ_MEM_DMA1 37 /* (Memory DMA Stream 1) */
45 #define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
46 #define IRQ_WATCH 38 /* Watch Dog Timer */
50 #define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
51 #define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
52 #define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
53 #define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
54 #define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
55 #define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
56 #define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
57 #define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
110 #define GPIO_IRQ_BASE IRQ_PF0
112 #define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
113 #define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
114 #define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
115 #define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
116 #define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
117 #define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
118 #define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
119 #define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
121 #define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
123 /* IAR0 BIT FIELDS */
124 #define IRQ_PLL_WAKEUP_POS 0
125 #define IRQ_DMA_ERROR_POS 4
126 #define IRQ_ERROR_POS 8
127 #define IRQ_RTC_POS 12
128 #define IRQ_PPI_POS 16
129 #define IRQ_SPORT0_RX_POS 20
130 #define IRQ_SPORT0_TX_POS 24
131 #define IRQ_SPORT1_RX_POS 28
133 /* IAR1 BIT FIELDS */
134 #define IRQ_SPORT1_TX_POS 0
135 #define IRQ_TWI_POS 4
136 #define IRQ_SPI_POS 8
137 #define IRQ_UART0_RX_POS 12
138 #define IRQ_UART0_TX_POS 16
139 #define IRQ_UART1_RX_POS 20
140 #define IRQ_UART1_TX_POS 24
141 #define IRQ_CAN_RX_POS 28
143 /* IAR2 BIT FIELDS */
144 #define IRQ_CAN_TX_POS 0
145 #define IRQ_MAC_RX_POS 4
146 #define IRQ_MAC_TX_POS 8
147 #define IRQ_TIMER0_POS 12
148 #define IRQ_TIMER1_POS 16
149 #define IRQ_TIMER2_POS 20
150 #define IRQ_TIMER3_POS 24
151 #define IRQ_TIMER4_POS 28
153 /* IAR3 BIT FIELDS */
154 #define IRQ_TIMER5_POS 0
155 #define IRQ_TIMER6_POS 4
156 #define IRQ_TIMER7_POS 8
157 #define IRQ_PROG_INTA_POS 12
158 #define IRQ_PORTG_INTB_POS 16
159 #define IRQ_MEM_DMA0_POS 20
160 #define IRQ_MEM_DMA1_POS 24
161 #define IRQ_WATCH_POS 28