arch/blackfin/mach-common/clocks-init.c

   1 /*
   2  * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory
   3  *
   4  * Copyright 2004-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/linkage.h>
  10 #include <linux/init.h>
  11 #include <asm/blackfin.h>
  12
  13 #include <asm/dma.h>
  14 #include <asm/clocks.h>
  15 #include <asm/mem_init.h>
  16 #include <asm/dpmc.h>
  17
  18 #define SDGCTL_WIDTH (1 << 31)  /* SDRAM external data path width */
  19 #define PLL_CTL_VAL \
  20         (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
  21          (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
  22
  23 __attribute__((l1_text))
  24 static void do_sync(void)
  25 {
  26         __builtin_bfin_ssync();
  27 }
  28
  29 __attribute__((l1_text))
  30 void init_clocks(void)
  31 {
  32         /* Kill any active DMAs as they may trigger external memory accesses
  33          * in the middle of reprogramming things, and that'll screw us up.
  34          * For example, any automatic DMAs left by U-Boot for splash screens.
  35          */
  36
  37 #if 0
  38         size_t i;
  39         for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
  40                 struct dma_register *dma = dma_io_base_addr[i];
  41                 dma->cfg = 0;
  42         }
  43
  44         do_sync();
  45
  46 #ifdef SIC_IWR0
  47         bfin_write_SIC_IWR0(IWR_ENABLE(0));
  48 # ifdef SIC_IWR1
  49         /* BF52x system reset does not properly reset SIC_IWR1 which
  50          * will screw up the bootrom as it relies on MDMA0/1 waking it
  51          * up from IDLE instructions.  See this report for more info:
  52          * http://blackfin.uclinux.org/gf/tracker/4323
  53          */
  54         if (ANOMALY_05000435)
  55                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
  56         else
  57                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
  58 # endif
  59 # ifdef SIC_IWR2
  60         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
  61 # endif
  62 #else
  63         bfin_write_SIC_IWR(IWR_ENABLE(0));
  64 #endif
  65         do_sync();
  66 #ifdef EBIU_SDGCTL
  67         bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
  68         do_sync();
  69 #endif
  70
  71 #ifdef CLKBUFOE
  72         bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
  73         do_sync();
  74         __asm__ __volatile__("IDLE;");
  75 #endif
  76         bfin_write_PLL_LOCKCNT(0x300);
  77         do_sync();
  78         /* We always write PLL_CTL thus avoiding Anomaly 05000242 */
  79         bfin_write16(PLL_CTL, PLL_CTL_VAL);
  80         __asm__ __volatile__("IDLE;");
  81         bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
  82 #ifdef EBIU_SDGCTL
  83         bfin_write_EBIU_SDRRC(mem_SDRRC);
  84         bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL);
  85 #else
  86         bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
  87         do_sync();
  88         bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
  89         bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
  90         bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
  91         bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
  92 #ifdef CONFIG_MEM_EBIU_DDRQUE
  93         bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
  94 #endif
  95 #endif
  96         do_sync();
  97         bfin_read16(0);
  98
  99 #endif
 100 }