2 * Set up the interrupt priorities
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
11 * Licensed under the GPL-2
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
18 #include <linux/sched.h>
20 #include <linux/ipipe.h>
22 #include <asm/traps.h>
23 #include <asm/blackfin.h>
25 #include <asm/irq_handler.h>
28 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
32 * - we have separated the physical Hardware interrupt from the
33 * levels that the LINUX kernel sees (see the description in irq.h)
38 /* Initialize this to an actual value to force it into the .data
39 * section so that we know it is properly initialized at entry into
40 * the kernel but before bss is initialized to zero (which is where
41 * it would live otherwise). The 0x1f magic represents the IRQs we
42 * cannot actually mask out in hardware.
44 unsigned long bfin_irq_flags = 0x1f;
45 EXPORT_SYMBOL(bfin_irq_flags);
49 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
54 /* irq number for request_irq, available in mach-bf5xx/irq.h */
56 /* corresponding bit in the SIC_ISR register */
58 } ivg_table[NR_PERI_INTS];
60 static struct ivg_slice {
61 /* position of first irq in ivg_table for given ivg */
64 } ivg7_13[IVG13 - IVG7 + 1];
68 * Search SIC_IAR and fill tables with the irqvalues
69 * and their positions in the SIC_ISR register.
71 static void __init search_IAR(void)
73 unsigned ivg, irq_pos = 0;
74 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
77 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
79 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
81 u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
82 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
83 defined(CONFIG_BF538) || defined(CONFIG_BF539)
84 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
90 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
91 int iar_shift = (irqn & 7) * 4;
92 if (ivg == (0xf & (iar >> iar_shift))) {
93 ivg_table[irq_pos].irqno = IVG7 + irqn;
94 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
104 * This is for core internal IRQs
107 void bfin_ack_noop(struct irq_data *d)
109 /* Dummy function. */
112 static void bfin_core_mask_irq(struct irq_data *d)
114 bfin_irq_flags &= ~(1 << d->irq);
115 if (!hard_irqs_disabled())
116 hard_local_irq_enable();
119 static void bfin_core_unmask_irq(struct irq_data *d)
121 bfin_irq_flags |= 1 << d->irq;
123 * If interrupts are enabled, IMASK must contain the same value
124 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
125 * are currently disabled we need not do anything; one of the
126 * callers will take care of setting IMASK to the proper value
127 * when reenabling interrupts.
128 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
131 if (!hard_irqs_disabled())
132 hard_local_irq_enable();
136 void bfin_internal_mask_irq(unsigned int irq)
138 unsigned long flags = hard_local_irq_save();
141 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
142 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
143 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
146 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
150 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
151 ~(1 << SIC_SYSIRQ(irq)));
154 hard_local_irq_restore(flags);
157 static void bfin_internal_mask_irq_chip(struct irq_data *d)
159 bfin_internal_mask_irq(d->irq);
163 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
164 const struct cpumask *affinity)
166 void bfin_internal_unmask_irq(unsigned int irq)
169 unsigned long flags = hard_local_irq_save();
172 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
173 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
175 if (cpumask_test_cpu(0, affinity))
177 bfin_write_SIC_IMASK(mask_bank,
178 bfin_read_SIC_IMASK(mask_bank) |
181 if (cpumask_test_cpu(1, affinity))
182 bfin_write_SICB_IMASK(mask_bank,
183 bfin_read_SICB_IMASK(mask_bank) |
187 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
188 (1 << SIC_SYSIRQ(irq)));
191 hard_local_irq_restore(flags);
195 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
197 bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
200 static int bfin_internal_set_affinity(struct irq_data *d,
201 const struct cpumask *mask, bool force)
203 bfin_internal_mask_irq(d->irq);
204 bfin_internal_unmask_irq_affinity(d->irq, mask);
209 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
211 bfin_internal_unmask_irq(d->irq);
216 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
218 u32 bank, bit, wakeup = 0;
220 bank = SIC_SYSIRQ(irq) / 32;
221 bit = SIC_SYSIRQ(irq) % 32;
253 flags = hard_local_irq_save();
256 bfin_sic_iwr[bank] |= (1 << bit);
260 bfin_sic_iwr[bank] &= ~(1 << bit);
261 vr_wakeup &= ~wakeup;
264 hard_local_irq_restore(flags);
269 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
271 return bfin_internal_set_wake(d->irq, state);
274 # define bfin_internal_set_wake_chip NULL
277 static struct irq_chip bfin_core_irqchip = {
279 .irq_ack = bfin_ack_noop,
280 .irq_mask = bfin_core_mask_irq,
281 .irq_unmask = bfin_core_unmask_irq,
284 static struct irq_chip bfin_internal_irqchip = {
286 .irq_ack = bfin_ack_noop,
287 .irq_mask = bfin_internal_mask_irq_chip,
288 .irq_unmask = bfin_internal_unmask_irq_chip,
289 .irq_mask_ack = bfin_internal_mask_irq_chip,
290 .irq_disable = bfin_internal_mask_irq_chip,
291 .irq_enable = bfin_internal_unmask_irq_chip,
293 .irq_set_affinity = bfin_internal_set_affinity,
295 .irq_set_wake = bfin_internal_set_wake_chip,
298 void bfin_handle_irq(unsigned irq)
301 struct pt_regs regs; /* Contents not used. */
302 ipipe_trace_irq_entry(irq);
303 __ipipe_handle_irq(irq, ®s);
304 ipipe_trace_irq_exit(irq);
305 #else /* !CONFIG_IPIPE */
306 generic_handle_irq(irq);
307 #endif /* !CONFIG_IPIPE */
310 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
311 static int mac_stat_int_mask;
313 static void bfin_mac_status_ack_irq(unsigned int irq)
317 bfin_write_EMAC_MMC_TIRQS(
318 bfin_read_EMAC_MMC_TIRQE() &
319 bfin_read_EMAC_MMC_TIRQS());
320 bfin_write_EMAC_MMC_RIRQS(
321 bfin_read_EMAC_MMC_RIRQE() &
322 bfin_read_EMAC_MMC_RIRQS());
324 case IRQ_MAC_RXFSINT:
325 bfin_write_EMAC_RX_STKY(
326 bfin_read_EMAC_RX_IRQE() &
327 bfin_read_EMAC_RX_STKY());
329 case IRQ_MAC_TXFSINT:
330 bfin_write_EMAC_TX_STKY(
331 bfin_read_EMAC_TX_IRQE() &
332 bfin_read_EMAC_TX_STKY());
334 case IRQ_MAC_WAKEDET:
335 bfin_write_EMAC_WKUP_CTL(
336 bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
339 /* These bits are W1C */
340 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
345 static void bfin_mac_status_mask_irq(struct irq_data *d)
347 unsigned int irq = d->irq;
349 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
353 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
359 if (!mac_stat_int_mask)
360 bfin_internal_mask_irq(IRQ_MAC_ERROR);
362 bfin_mac_status_ack_irq(irq);
365 static void bfin_mac_status_unmask_irq(struct irq_data *d)
367 unsigned int irq = d->irq;
372 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
378 if (!mac_stat_int_mask)
379 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
381 mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
385 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
388 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
390 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
394 # define bfin_mac_status_set_wake NULL
397 static struct irq_chip bfin_mac_status_irqchip = {
399 .irq_ack = bfin_ack_noop,
400 .irq_mask_ack = bfin_mac_status_mask_irq,
401 .irq_mask = bfin_mac_status_mask_irq,
402 .irq_unmask = bfin_mac_status_unmask_irq,
403 .irq_set_wake = bfin_mac_status_set_wake,
406 void bfin_demux_mac_status_irq(unsigned int int_err_irq,
407 struct irq_desc *inta_desc)
410 u32 status = bfin_read_EMAC_SYSTAT();
412 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
413 if (status & (1L << i)) {
414 irq = IRQ_MAC_PHYINT + i;
419 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
420 bfin_handle_irq(irq);
422 bfin_mac_status_ack_irq(irq);
424 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
429 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
430 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
431 "(EMAC_SYSTAT=0x%X)\n",
432 __func__, __FILE__, __LINE__, status);
436 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
439 handle = handle_level_irq;
441 __irq_set_handler_locked(irq, handle);
444 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
445 extern void bfin_gpio_irq_prepare(unsigned gpio);
447 #if !defined(CONFIG_BF54x)
449 static void bfin_gpio_ack_irq(struct irq_data *d)
451 /* AFAIK ack_irq in case mask_ack is provided
452 * get's only called for edge sense irqs
454 set_gpio_data(irq_to_gpio(d->irq), 0);
457 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
459 unsigned int irq = d->irq;
460 u32 gpionr = irq_to_gpio(irq);
462 if (!irqd_is_level_type(d))
463 set_gpio_data(gpionr, 0);
465 set_gpio_maska(gpionr, 0);
468 static void bfin_gpio_mask_irq(struct irq_data *d)
470 set_gpio_maska(irq_to_gpio(d->irq), 0);
473 static void bfin_gpio_unmask_irq(struct irq_data *d)
475 set_gpio_maska(irq_to_gpio(d->irq), 1);
478 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
480 u32 gpionr = irq_to_gpio(d->irq);
482 if (__test_and_set_bit(gpionr, gpio_enabled))
483 bfin_gpio_irq_prepare(gpionr);
485 bfin_gpio_unmask_irq(d);
490 static void bfin_gpio_irq_shutdown(struct irq_data *d)
492 u32 gpionr = irq_to_gpio(d->irq);
494 bfin_gpio_mask_irq(d);
495 __clear_bit(gpionr, gpio_enabled);
496 bfin_gpio_irq_free(gpionr);
499 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
501 unsigned int irq = d->irq;
504 u32 gpionr = irq_to_gpio(irq);
506 if (type == IRQ_TYPE_PROBE) {
507 /* only probe unenabled GPIO interrupt lines */
508 if (test_bit(gpionr, gpio_enabled))
510 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
513 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
514 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
516 snprintf(buf, 16, "gpio-irq%d", irq);
517 ret = bfin_gpio_irq_request(gpionr, buf);
521 if (__test_and_set_bit(gpionr, gpio_enabled))
522 bfin_gpio_irq_prepare(gpionr);
525 __clear_bit(gpionr, gpio_enabled);
529 set_gpio_inen(gpionr, 0);
530 set_gpio_dir(gpionr, 0);
532 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
533 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
534 set_gpio_both(gpionr, 1);
536 set_gpio_both(gpionr, 0);
538 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
539 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
541 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
543 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
544 set_gpio_edge(gpionr, 1);
545 set_gpio_inen(gpionr, 1);
546 set_gpio_data(gpionr, 0);
549 set_gpio_edge(gpionr, 0);
550 set_gpio_inen(gpionr, 1);
553 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
554 bfin_set_irq_handler(irq, handle_edge_irq);
556 bfin_set_irq_handler(irq, handle_level_irq);
562 int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
564 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
567 # define bfin_gpio_set_wake NULL
570 static void bfin_demux_gpio_irq(unsigned int inta_irq,
571 struct irq_desc *desc)
573 unsigned int i, gpio, mask, irq, search = 0;
576 #if defined(CONFIG_BF53x)
581 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
586 #elif defined(BF538_FAMILY)
590 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
600 #elif defined(CONFIG_BF561)
617 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
620 mask = get_gpiop_data(i) & get_gpiop_maska(i);
624 bfin_handle_irq(irq);
630 gpio = irq_to_gpio(irq);
631 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
635 bfin_handle_irq(irq);
643 #else /* CONFIG_BF54x */
645 #define NR_PINT_SYS_IRQS 4
646 #define NR_PINT_BITS 32
648 #define IRQ_NOT_AVAIL 0xFF
650 #define PINT_2_BANK(x) ((x) >> 5)
651 #define PINT_2_BIT(x) ((x) & 0x1F)
652 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
654 static unsigned char irq2pint_lut[NR_PINTS];
655 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
658 unsigned int mask_set;
659 unsigned int mask_clear;
660 unsigned int request;
662 unsigned int edge_set;
663 unsigned int edge_clear;
664 unsigned int invert_set;
665 unsigned int invert_clear;
666 unsigned int pinstate;
670 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
671 (struct pin_int_t *)PINT0_MASK_SET,
672 (struct pin_int_t *)PINT1_MASK_SET,
673 (struct pin_int_t *)PINT2_MASK_SET,
674 (struct pin_int_t *)PINT3_MASK_SET,
677 inline unsigned int get_irq_base(u32 bank, u8 bmap)
679 unsigned int irq_base;
681 if (bank < 2) { /*PA-PB */
682 irq_base = IRQ_PA0 + bmap * 16;
684 irq_base = IRQ_PC0 + bmap * 16;
690 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
691 void init_pint_lut(void)
693 u16 bank, bit, irq_base, bit_pos;
697 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
699 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
701 pint_assign = pint[bank]->assign;
703 for (bit = 0; bit < NR_PINT_BITS; bit++) {
705 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
707 irq_base = get_irq_base(bank, bmap);
709 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
710 bit_pos = bit + bank * NR_PINT_BITS;
712 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
713 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
718 static void bfin_gpio_ack_irq(struct irq_data *d)
720 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
721 u32 pintbit = PINT_BIT(pint_val);
722 u32 bank = PINT_2_BANK(pint_val);
724 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
725 if (pint[bank]->invert_set & pintbit)
726 pint[bank]->invert_clear = pintbit;
728 pint[bank]->invert_set = pintbit;
730 pint[bank]->request = pintbit;
734 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
736 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
737 u32 pintbit = PINT_BIT(pint_val);
738 u32 bank = PINT_2_BANK(pint_val);
740 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
741 if (pint[bank]->invert_set & pintbit)
742 pint[bank]->invert_clear = pintbit;
744 pint[bank]->invert_set = pintbit;
747 pint[bank]->request = pintbit;
748 pint[bank]->mask_clear = pintbit;
751 static void bfin_gpio_mask_irq(struct irq_data *d)
753 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
755 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
758 static void bfin_gpio_unmask_irq(struct irq_data *d)
760 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
761 u32 pintbit = PINT_BIT(pint_val);
762 u32 bank = PINT_2_BANK(pint_val);
764 pint[bank]->mask_set = pintbit;
767 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
769 unsigned int irq = d->irq;
770 u32 gpionr = irq_to_gpio(irq);
771 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
773 if (pint_val == IRQ_NOT_AVAIL) {
775 "GPIO IRQ %d :Not in PINT Assign table "
776 "Reconfigure Interrupt to Port Assignemt\n", irq);
780 if (__test_and_set_bit(gpionr, gpio_enabled))
781 bfin_gpio_irq_prepare(gpionr);
783 bfin_gpio_unmask_irq(d);
788 static void bfin_gpio_irq_shutdown(struct irq_data *d)
790 u32 gpionr = irq_to_gpio(d->irq);
792 bfin_gpio_mask_irq(d);
793 __clear_bit(gpionr, gpio_enabled);
794 bfin_gpio_irq_free(gpionr);
797 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
799 unsigned int irq = d->irq;
802 u32 gpionr = irq_to_gpio(irq);
803 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
804 u32 pintbit = PINT_BIT(pint_val);
805 u32 bank = PINT_2_BANK(pint_val);
807 if (pint_val == IRQ_NOT_AVAIL)
810 if (type == IRQ_TYPE_PROBE) {
811 /* only probe unenabled GPIO interrupt lines */
812 if (test_bit(gpionr, gpio_enabled))
814 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
817 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
818 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
820 snprintf(buf, 16, "gpio-irq%d", irq);
821 ret = bfin_gpio_irq_request(gpionr, buf);
825 if (__test_and_set_bit(gpionr, gpio_enabled))
826 bfin_gpio_irq_prepare(gpionr);
829 __clear_bit(gpionr, gpio_enabled);
833 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
834 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
836 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
838 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
839 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
840 if (gpio_get_value(gpionr))
841 pint[bank]->invert_set = pintbit;
843 pint[bank]->invert_clear = pintbit;
846 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
847 pint[bank]->edge_set = pintbit;
848 bfin_set_irq_handler(irq, handle_edge_irq);
850 pint[bank]->edge_clear = pintbit;
851 bfin_set_irq_handler(irq, handle_level_irq);
858 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
859 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
861 int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
864 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
865 u32 bank = PINT_2_BANK(pint_val);
866 u32 pintbit = PINT_BIT(pint_val);
870 pint_irq = IRQ_PINT0;
873 pint_irq = IRQ_PINT2;
876 pint_irq = IRQ_PINT3;
879 pint_irq = IRQ_PINT1;
885 bfin_internal_set_wake(pint_irq, state);
888 pint_wakeup_masks[bank] |= pintbit;
890 pint_wakeup_masks[bank] &= ~pintbit;
895 u32 bfin_pm_setup(void)
899 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
900 val = pint[i]->mask_clear;
901 pint_saved_masks[i] = val;
902 if (val ^ pint_wakeup_masks[i]) {
903 pint[i]->mask_clear = val;
904 pint[i]->mask_set = pint_wakeup_masks[i];
911 void bfin_pm_restore(void)
915 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
916 val = pint_saved_masks[i];
917 if (val ^ pint_wakeup_masks[i]) {
918 pint[i]->mask_clear = pint[i]->mask_clear;
919 pint[i]->mask_set = val;
924 # define bfin_gpio_set_wake NULL
927 static void bfin_demux_gpio_irq(unsigned int inta_irq,
928 struct irq_desc *desc)
950 pint_val = bank * NR_PINT_BITS;
952 request = pint[bank]->request;
956 irq = pint2irq_lut[pint_val] + SYS_IRQS;
957 bfin_handle_irq(irq);
966 static struct irq_chip bfin_gpio_irqchip = {
968 .irq_ack = bfin_gpio_ack_irq,
969 .irq_mask = bfin_gpio_mask_irq,
970 .irq_mask_ack = bfin_gpio_mask_ack_irq,
971 .irq_unmask = bfin_gpio_unmask_irq,
972 .irq_disable = bfin_gpio_mask_irq,
973 .irq_enable = bfin_gpio_unmask_irq,
974 .irq_set_type = bfin_gpio_irq_type,
975 .irq_startup = bfin_gpio_irq_startup,
976 .irq_shutdown = bfin_gpio_irq_shutdown,
977 .irq_set_wake = bfin_gpio_set_wake,
980 void __cpuinit init_exception_vectors(void)
982 /* cannot program in software:
983 * evt0 - emulation (jtag)
986 bfin_write_EVT2(evt_nmi);
987 bfin_write_EVT3(trap);
988 bfin_write_EVT5(evt_ivhw);
989 bfin_write_EVT6(evt_timer);
990 bfin_write_EVT7(evt_evt7);
991 bfin_write_EVT8(evt_evt8);
992 bfin_write_EVT9(evt_evt9);
993 bfin_write_EVT10(evt_evt10);
994 bfin_write_EVT11(evt_evt11);
995 bfin_write_EVT12(evt_evt12);
996 bfin_write_EVT13(evt_evt13);
997 bfin_write_EVT14(evt_evt14);
998 bfin_write_EVT15(evt_system_call);
1003 * This function should be called during kernel startup to initialize
1004 * the BFin IRQ handling routines.
1007 int __init init_arch_irq(void)
1010 unsigned long ilat = 0;
1012 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
1014 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1015 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1017 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1020 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1021 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1024 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1027 local_irq_disable();
1030 # ifdef CONFIG_PINTx_REASSIGN
1031 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1032 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1033 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1034 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1036 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1040 for (irq = 0; irq <= SYS_IRQS; irq++) {
1041 if (irq <= IRQ_CORETMR)
1042 irq_set_chip(irq, &bfin_core_irqchip);
1044 irq_set_chip(irq, &bfin_internal_irqchip);
1047 #if defined(CONFIG_BF53x)
1049 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1052 #elif defined(CONFIG_BF54x)
1057 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1058 case IRQ_PORTF_INTA:
1059 case IRQ_PORTG_INTA:
1060 case IRQ_PORTH_INTA:
1061 #elif defined(CONFIG_BF561)
1062 case IRQ_PROG0_INTA:
1063 case IRQ_PROG1_INTA:
1064 case IRQ_PROG2_INTA:
1065 #elif defined(BF538_FAMILY)
1066 case IRQ_PORTF_INTA:
1068 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1070 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1072 irq_set_chained_handler(irq,
1073 bfin_demux_mac_status_irq);
1079 irq_set_handler(irq, handle_percpu_irq);
1083 #ifdef CONFIG_TICKSOURCE_CORETMR
1086 irq_set_handler(irq, handle_percpu_irq);
1088 irq_set_handler(irq, handle_simple_irq);
1093 #ifdef CONFIG_TICKSOURCE_GPTMR0
1095 irq_set_handler(irq, handle_simple_irq);
1101 irq_set_handler(irq, handle_level_irq);
1103 irq_set_handler(irq, handle_simple_irq);
1111 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1112 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1113 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1116 /* if configured as edge, then will be changed to do_edge_IRQ */
1117 for (irq = GPIO_IRQ_BASE;
1118 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1119 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1122 bfin_write_IMASK(0);
1124 ilat = bfin_read_ILAT();
1126 bfin_write_ILAT(ilat);
1129 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1130 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1131 * local_irq_enable()
1134 /* Therefore it's better to setup IARs before interrupts enabled */
1137 /* Enable interrupts IVG7-15 */
1138 bfin_irq_flags |= IMASK_IVG15 |
1139 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1140 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1142 /* This implicitly covers ANOMALY_05000171
1143 * Boot-ROM code modifies SICA_IWRx wakeup registers
1146 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1148 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1149 * will screw up the bootrom as it relies on MDMA0/1 waking it
1150 * up from IDLE instructions. See this report for more info:
1151 * http://blackfin.uclinux.org/gf/tracker/4323
1153 if (ANOMALY_05000435)
1154 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1156 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1159 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1162 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1168 #ifdef CONFIG_DO_IRQ_L1
1169 __attribute__((l1_text))
1171 static int vec_to_irq(int vec)
1173 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1174 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1175 unsigned long sic_status[3];
1177 if (likely(vec == EVT_IVTMR_P))
1181 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1183 if (smp_processor_id()) {
1185 /* This will be optimized out in UP mode. */
1186 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1187 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1190 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1191 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1195 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1199 if (ivg >= ivg_stop)
1202 if (sic_status[0] & ivg->isrflag)
1204 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1210 #ifdef CONFIG_DO_IRQ_L1
1211 __attribute__((l1_text))
1213 void do_irq(int vec, struct pt_regs *fp)
1215 int irq = vec_to_irq(vec);
1218 asm_do_IRQ(irq, fp);
1223 int __ipipe_get_irq_priority(unsigned irq)
1227 if (irq <= IRQ_CORETMR)
1230 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1231 struct ivgx *ivg = ivg_table + ient;
1232 if (ivg->irqno == irq) {
1233 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1234 if (ivg7_13[prio].ifirst <= ivg &&
1235 ivg7_13[prio].istop > ivg)
1244 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1245 #ifdef CONFIG_DO_IRQ_L1
1246 __attribute__((l1_text))
1248 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1250 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1251 struct ipipe_domain *this_domain = __ipipe_current_domain;
1252 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1253 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1256 irq = vec_to_irq(vec);
1260 if (irq == IRQ_SYSTMR) {
1261 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1262 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1264 /* This is basically what we need from the register frame. */
1265 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1266 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1267 if (this_domain != ipipe_root_domain)
1268 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1270 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1274 * We don't want Linux interrupt handlers to run at the
1275 * current core priority level (i.e. < EVT15), since this
1276 * might delay other interrupts handled by a high priority
1277 * domain. Here is what we do instead:
1279 * - we raise the SYNCDEFER bit to prevent
1280 * __ipipe_handle_irq() to sync the pipeline for the root
1281 * stage for the incoming interrupt. Upon return, that IRQ is
1282 * pending in the interrupt log.
1284 * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1285 * that _schedule_and_signal_from_int will eventually sync the
1286 * pipeline from EVT15.
1288 if (this_domain == ipipe_root_domain) {
1289 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1293 ipipe_trace_irq_entry(irq);
1294 __ipipe_handle_irq(irq, regs);
1295 ipipe_trace_irq_exit(irq);
1297 if (user_mode(regs) &&
1298 !ipipe_test_foreign_stack() &&
1299 (current->ipipe_flags & PF_EVTRET) != 0) {
1301 * Testing for user_regs() does NOT fully eliminate
1302 * foreign stack contexts, because of the forged
1303 * interrupt returns we do through
1304 * __ipipe_call_irqtail. In that case, we might have
1305 * preempted a foreign stack context in a high
1306 * priority domain, with a single interrupt level now
1307 * pending after the irqtail unwinding is done. In
1308 * which case user_mode() is now true, and the event
1309 * gets dispatched spuriously.
1311 current->ipipe_flags &= ~PF_EVTRET;
1312 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1315 if (this_domain == ipipe_root_domain) {
1316 set_thread_flag(TIF_IRQ_SYNC);
1318 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1319 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1326 #endif /* CONFIG_IPIPE */