2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/compiler.h>
33 #include <linux/acpi.h>
34 #include <linux/module.h>
35 #include <linux/sysdev.h>
40 #include <asm/timer.h>
41 #include <asm/i8259.h>
43 #include <mach_apic.h>
47 int (*ioapic_renumber_irq)(int ioapic, int irq);
48 atomic_t irq_mis_count;
50 static DEFINE_SPINLOCK(ioapic_lock);
53 * Is the SiS APIC rmw bug present ?
54 * -1 = don't know, 0 = no, 1 = yes
56 int sis_apic_bug = -1;
59 * # of IRQ routing registers
61 int nr_ioapic_registers[MAX_IO_APICS];
63 int disable_timer_pin_1 __initdata;
66 * Rough estimation of how many shared IRQs there are, can
69 #define MAX_PLUS_SHARED_IRQS NR_IRQS
70 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
73 * This is performance-critical, we want to do it O(1)
75 * the indexing order of this array favors 1:1 mappings
76 * between pins and IRQs.
79 static struct irq_pin_list {
81 } irq_2_pin[PIN_MAP_SIZE];
83 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
85 #define vector_to_irq(vector) \
86 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
88 #define vector_to_irq(vector) (vector)
92 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
93 * shared ISA-space IRQs, so we have to support them. We are super
94 * fast in the common case, and fast for shared ISA-space IRQs.
96 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
98 static int first_free_entry = NR_IRQS;
99 struct irq_pin_list *entry = irq_2_pin + irq;
102 entry = irq_2_pin + entry->next;
104 if (entry->pin != -1) {
105 entry->next = first_free_entry;
106 entry = irq_2_pin + entry->next;
107 if (++first_free_entry >= PIN_MAP_SIZE)
108 panic("io_apic.c: whoops");
115 * Reroute an IRQ to a different pin.
117 static void __init replace_pin_at_irq(unsigned int irq,
118 int oldapic, int oldpin,
119 int newapic, int newpin)
121 struct irq_pin_list *entry = irq_2_pin + irq;
124 if (entry->apic == oldapic && entry->pin == oldpin) {
125 entry->apic = newapic;
130 entry = irq_2_pin + entry->next;
134 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
136 struct irq_pin_list *entry = irq_2_pin + irq;
137 unsigned int pin, reg;
143 reg = io_apic_read(entry->apic, 0x10 + pin*2);
146 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
149 entry = irq_2_pin + entry->next;
154 static void __mask_IO_APIC_irq (unsigned int irq)
156 __modify_IO_APIC_irq(irq, 0x00010000, 0);
160 static void __unmask_IO_APIC_irq (unsigned int irq)
162 __modify_IO_APIC_irq(irq, 0, 0x00010000);
165 /* mask = 1, trigger = 0 */
166 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
168 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
171 /* mask = 0, trigger = 1 */
172 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
174 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
177 static void mask_IO_APIC_irq (unsigned int irq)
181 spin_lock_irqsave(&ioapic_lock, flags);
182 __mask_IO_APIC_irq(irq);
183 spin_unlock_irqrestore(&ioapic_lock, flags);
186 static void unmask_IO_APIC_irq (unsigned int irq)
190 spin_lock_irqsave(&ioapic_lock, flags);
191 __unmask_IO_APIC_irq(irq);
192 spin_unlock_irqrestore(&ioapic_lock, flags);
195 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
197 struct IO_APIC_route_entry entry;
200 /* Check delivery_mode to be sure we're not clearing an SMI pin */
201 spin_lock_irqsave(&ioapic_lock, flags);
202 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
203 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
204 spin_unlock_irqrestore(&ioapic_lock, flags);
205 if (entry.delivery_mode == dest_SMI)
209 * Disable it in the IO-APIC irq-routing table:
211 memset(&entry, 0, sizeof(entry));
213 spin_lock_irqsave(&ioapic_lock, flags);
214 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
215 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
216 spin_unlock_irqrestore(&ioapic_lock, flags);
219 static void clear_IO_APIC (void)
223 for (apic = 0; apic < nr_ioapics; apic++)
224 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
225 clear_IO_APIC_pin(apic, pin);
229 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
233 struct irq_pin_list *entry = irq_2_pin + irq;
234 unsigned int apicid_value;
237 cpus_and(tmp, cpumask, cpu_online_map);
241 cpus_and(cpumask, tmp, CPU_MASK_ALL);
243 apicid_value = cpu_mask_to_apicid(cpumask);
244 /* Prepare to do the io_apic_write */
245 apicid_value = apicid_value << 24;
246 spin_lock_irqsave(&ioapic_lock, flags);
251 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
254 entry = irq_2_pin + entry->next;
256 set_irq_info(irq, cpumask);
257 spin_unlock_irqrestore(&ioapic_lock, flags);
260 #if defined(CONFIG_IRQBALANCE)
261 # include <asm/processor.h> /* kernel_thread() */
262 # include <linux/kernel_stat.h> /* kstat */
263 # include <linux/slab.h> /* kmalloc() */
264 # include <linux/timer.h> /* time_after() */
266 # ifdef CONFIG_BALANCED_IRQ_DEBUG
267 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
268 # define Dprintk(x...) do { TDprintk(x); } while (0)
270 # define TDprintk(x...)
271 # define Dprintk(x...)
275 #define IRQBALANCE_CHECK_ARCH -999
276 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
277 static int physical_balance = 0;
279 static struct irq_cpu_info {
280 unsigned long * last_irq;
281 unsigned long * irq_delta;
283 } irq_cpu_data[NR_CPUS];
285 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
286 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
287 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
289 #define IDLE_ENOUGH(cpu,now) \
290 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
292 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
294 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
296 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
297 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
298 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
299 #define BALANCED_IRQ_LESS_DELTA (HZ)
301 static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
303 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
304 unsigned long now, int direction)
312 if (unlikely(cpu == curr_cpu))
315 if (direction == 1) {
324 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
325 (search_idle && !IDLE_ENOUGH(cpu,now)));
330 static inline void balance_irq(int cpu, int irq)
332 unsigned long now = jiffies;
333 cpumask_t allowed_mask;
334 unsigned int new_cpu;
336 if (irqbalance_disabled)
339 cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
340 new_cpu = move(cpu, allowed_mask, now, 1);
341 if (cpu != new_cpu) {
342 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
346 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
349 Dprintk("Rotating IRQs among CPUs.\n");
350 for (i = 0; i < NR_CPUS; i++) {
351 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
352 if (!irq_desc[j].action)
354 /* Is it a significant load ? */
355 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
356 useful_load_threshold)
361 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
362 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
366 static void do_irq_balance(void)
369 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
370 unsigned long move_this_load = 0;
371 int max_loaded = 0, min_loaded = 0;
373 unsigned long useful_load_threshold = balanced_irq_interval + 10;
375 int tmp_loaded, first_attempt = 1;
376 unsigned long tmp_cpu_irq;
377 unsigned long imbalance = 0;
378 cpumask_t allowed_mask, target_cpu_mask, tmp;
380 for (i = 0; i < NR_CPUS; i++) {
385 package_index = CPU_TO_PACKAGEINDEX(i);
386 for (j = 0; j < NR_IRQS; j++) {
387 unsigned long value_now, delta;
388 /* Is this an active IRQ? */
389 if (!irq_desc[j].action)
391 if ( package_index == i )
392 IRQ_DELTA(package_index,j) = 0;
393 /* Determine the total count per processor per IRQ */
394 value_now = (unsigned long) kstat_cpu(i).irqs[j];
396 /* Determine the activity per processor per IRQ */
397 delta = value_now - LAST_CPU_IRQ(i,j);
399 /* Update last_cpu_irq[][] for the next time */
400 LAST_CPU_IRQ(i,j) = value_now;
402 /* Ignore IRQs whose rate is less than the clock */
403 if (delta < useful_load_threshold)
405 /* update the load for the processor or package total */
406 IRQ_DELTA(package_index,j) += delta;
408 /* Keep track of the higher numbered sibling as well */
409 if (i != package_index)
412 * We have sibling A and sibling B in the package
414 * cpu_irq[A] = load for cpu A + load for cpu B
415 * cpu_irq[B] = load for cpu B
417 CPU_IRQ(package_index) += delta;
420 /* Find the least loaded processor package */
421 for (i = 0; i < NR_CPUS; i++) {
424 if (i != CPU_TO_PACKAGEINDEX(i))
426 if (min_cpu_irq > CPU_IRQ(i)) {
427 min_cpu_irq = CPU_IRQ(i);
431 max_cpu_irq = ULONG_MAX;
434 /* Look for heaviest loaded processor.
435 * We may come back to get the next heaviest loaded processor.
436 * Skip processors with trivial loads.
440 for (i = 0; i < NR_CPUS; i++) {
443 if (i != CPU_TO_PACKAGEINDEX(i))
445 if (max_cpu_irq <= CPU_IRQ(i))
447 if (tmp_cpu_irq < CPU_IRQ(i)) {
448 tmp_cpu_irq = CPU_IRQ(i);
453 if (tmp_loaded == -1) {
454 /* In the case of small number of heavy interrupt sources,
455 * loading some of the cpus too much. We use Ingo's original
456 * approach to rotate them around.
458 if (!first_attempt && imbalance >= useful_load_threshold) {
459 rotate_irqs_among_cpus(useful_load_threshold);
462 goto not_worth_the_effort;
465 first_attempt = 0; /* heaviest search */
466 max_cpu_irq = tmp_cpu_irq; /* load */
467 max_loaded = tmp_loaded; /* processor */
468 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
470 Dprintk("max_loaded cpu = %d\n", max_loaded);
471 Dprintk("min_loaded cpu = %d\n", min_loaded);
472 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
473 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
474 Dprintk("load imbalance = %lu\n", imbalance);
476 /* if imbalance is less than approx 10% of max load, then
477 * observe diminishing returns action. - quit
479 if (imbalance < (max_cpu_irq >> 3)) {
480 Dprintk("Imbalance too trivial\n");
481 goto not_worth_the_effort;
485 /* if we select an IRQ to move that can't go where we want, then
486 * see if there is another one to try.
490 for (j = 0; j < NR_IRQS; j++) {
491 /* Is this an active IRQ? */
492 if (!irq_desc[j].action)
494 if (imbalance <= IRQ_DELTA(max_loaded,j))
496 /* Try to find the IRQ that is closest to the imbalance
497 * without going over.
499 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
500 move_this_load = IRQ_DELTA(max_loaded,j);
504 if (selected_irq == -1) {
508 imbalance = move_this_load;
510 /* For physical_balance case, we accumlated both load
511 * values in the one of the siblings cpu_irq[],
512 * to use the same code for physical and logical processors
513 * as much as possible.
515 * NOTE: the cpu_irq[] array holds the sum of the load for
516 * sibling A and sibling B in the slot for the lowest numbered
517 * sibling (A), _AND_ the load for sibling B in the slot for
518 * the higher numbered sibling.
520 * We seek the least loaded sibling by making the comparison
523 load = CPU_IRQ(min_loaded) >> 1;
524 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
525 if (load > CPU_IRQ(j)) {
526 /* This won't change cpu_sibling_map[min_loaded] */
532 cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
533 target_cpu_mask = cpumask_of_cpu(min_loaded);
534 cpus_and(tmp, target_cpu_mask, allowed_mask);
536 if (!cpus_empty(tmp)) {
538 Dprintk("irq = %d moved to cpu = %d\n",
539 selected_irq, min_loaded);
540 /* mark for change destination */
541 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
543 /* Since we made a change, come back sooner to
544 * check for more variation.
546 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
547 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
552 not_worth_the_effort:
554 * if we did not find an IRQ to move, then adjust the time interval
557 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
558 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
559 Dprintk("IRQ worth rotating not found\n");
563 static int balanced_irq(void *unused)
566 unsigned long prev_balance_time = jiffies;
567 long time_remaining = balanced_irq_interval;
571 /* push everything to CPU 0 to give us a starting point. */
572 for (i = 0 ; i < NR_IRQS ; i++) {
573 pending_irq_cpumask[i] = cpumask_of_cpu(0);
574 set_pending_irq(i, cpumask_of_cpu(0));
578 time_remaining = schedule_timeout_interruptible(time_remaining);
580 if (time_after(jiffies,
581 prev_balance_time+balanced_irq_interval)) {
584 prev_balance_time = jiffies;
585 time_remaining = balanced_irq_interval;
592 static int __init balanced_irq_init(void)
595 struct cpuinfo_x86 *c;
598 cpus_shift_right(tmp, cpu_online_map, 2);
600 /* When not overwritten by the command line ask subarchitecture. */
601 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
602 irqbalance_disabled = NO_BALANCE_IRQ;
603 if (irqbalance_disabled)
606 /* disable irqbalance completely if there is only one processor online */
607 if (num_online_cpus() < 2) {
608 irqbalance_disabled = 1;
612 * Enable physical balance only if more than 1 physical processor
615 if (smp_num_siblings > 1 && !cpus_empty(tmp))
616 physical_balance = 1;
618 for (i = 0; i < NR_CPUS; i++) {
621 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
622 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
623 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
624 printk(KERN_ERR "balanced_irq_init: out of memory");
627 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
628 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
631 printk(KERN_INFO "Starting balanced_irq\n");
632 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
635 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
637 for (i = 0; i < NR_CPUS; i++) {
638 kfree(irq_cpu_data[i].irq_delta);
639 kfree(irq_cpu_data[i].last_irq);
644 int __init irqbalance_disable(char *str)
646 irqbalance_disabled = 1;
650 __setup("noirqbalance", irqbalance_disable);
652 late_initcall(balanced_irq_init);
653 #endif /* CONFIG_IRQBALANCE */
654 #endif /* CONFIG_SMP */
657 void fastcall send_IPI_self(int vector)
664 apic_wait_icr_idle();
665 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
667 * Send the IPI. The write to APIC_ICR fires this off.
669 apic_write_around(APIC_ICR, cfg);
671 #endif /* !CONFIG_SMP */
675 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
676 * specific CPU-side IRQs.
680 static int pirq_entries [MAX_PIRQS];
681 static int pirqs_enabled;
682 int skip_ioapic_setup;
684 static int __init ioapic_setup(char *str)
686 skip_ioapic_setup = 1;
690 __setup("noapic", ioapic_setup);
692 static int __init ioapic_pirq_setup(char *str)
695 int ints[MAX_PIRQS+1];
697 get_options(str, ARRAY_SIZE(ints), ints);
699 for (i = 0; i < MAX_PIRQS; i++)
700 pirq_entries[i] = -1;
703 apic_printk(APIC_VERBOSE, KERN_INFO
704 "PIRQ redirection, working around broken MP-BIOS.\n");
706 if (ints[0] < MAX_PIRQS)
709 for (i = 0; i < max; i++) {
710 apic_printk(APIC_VERBOSE, KERN_DEBUG
711 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
713 * PIRQs are mapped upside down, usually.
715 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
720 __setup("pirq=", ioapic_pirq_setup);
723 * Find the IRQ entry number of a certain pin.
725 static int find_irq_entry(int apic, int pin, int type)
729 for (i = 0; i < mp_irq_entries; i++)
730 if (mp_irqs[i].mpc_irqtype == type &&
731 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
732 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
733 mp_irqs[i].mpc_dstirq == pin)
740 * Find the pin to which IRQ[irq] (ISA) is connected
742 static int find_isa_irq_pin(int irq, int type)
746 for (i = 0; i < mp_irq_entries; i++) {
747 int lbus = mp_irqs[i].mpc_srcbus;
749 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
750 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
751 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
752 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
754 (mp_irqs[i].mpc_irqtype == type) &&
755 (mp_irqs[i].mpc_srcbusirq == irq))
757 return mp_irqs[i].mpc_dstirq;
763 * Find a specific PCI IRQ entry.
764 * Not an __init, possibly needed by modules
766 static int pin_2_irq(int idx, int apic, int pin);
768 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
770 int apic, i, best_guess = -1;
772 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
773 "slot:%d, pin:%d.\n", bus, slot, pin);
774 if (mp_bus_id_to_pci_bus[bus] == -1) {
775 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
778 for (i = 0; i < mp_irq_entries; i++) {
779 int lbus = mp_irqs[i].mpc_srcbus;
781 for (apic = 0; apic < nr_ioapics; apic++)
782 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
783 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
786 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
787 !mp_irqs[i].mpc_irqtype &&
789 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
790 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
792 if (!(apic || IO_APIC_IRQ(irq)))
795 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
798 * Use the first all-but-pin matching entry as a
799 * best-guess fuzzy result for broken mptables.
807 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
810 * This function currently is only a helper for the i386 smp boot process where
811 * we need to reprogram the ioredtbls to cater for the cpus which have come online
812 * so mask in all cases should simply be TARGET_CPUS
815 void __init setup_ioapic_dest(void)
817 int pin, ioapic, irq, irq_entry;
819 if (skip_ioapic_setup == 1)
822 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
823 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
824 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
827 irq = pin_2_irq(irq_entry, ioapic, pin);
828 set_ioapic_affinity_irq(irq, TARGET_CPUS);
836 * EISA Edge/Level control register, ELCR
838 static int EISA_ELCR(unsigned int irq)
841 unsigned int port = 0x4d0 + (irq >> 3);
842 return (inb(port) >> (irq & 7)) & 1;
844 apic_printk(APIC_VERBOSE, KERN_INFO
845 "Broken MPtable reports ISA irq %d\n", irq);
849 /* EISA interrupts are always polarity zero and can be edge or level
850 * trigger depending on the ELCR value. If an interrupt is listed as
851 * EISA conforming in the MP table, that means its trigger type must
852 * be read in from the ELCR */
854 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
855 #define default_EISA_polarity(idx) (0)
857 /* ISA interrupts are always polarity zero edge triggered,
858 * when listed as conforming in the MP table. */
860 #define default_ISA_trigger(idx) (0)
861 #define default_ISA_polarity(idx) (0)
863 /* PCI interrupts are always polarity one level triggered,
864 * when listed as conforming in the MP table. */
866 #define default_PCI_trigger(idx) (1)
867 #define default_PCI_polarity(idx) (1)
869 /* MCA interrupts are always polarity zero level triggered,
870 * when listed as conforming in the MP table. */
872 #define default_MCA_trigger(idx) (1)
873 #define default_MCA_polarity(idx) (0)
875 /* NEC98 interrupts are always polarity zero edge triggered,
876 * when listed as conforming in the MP table. */
878 #define default_NEC98_trigger(idx) (0)
879 #define default_NEC98_polarity(idx) (0)
881 static int __init MPBIOS_polarity(int idx)
883 int bus = mp_irqs[idx].mpc_srcbus;
887 * Determine IRQ line polarity (high active or low active):
889 switch (mp_irqs[idx].mpc_irqflag & 3)
891 case 0: /* conforms, ie. bus-type dependent polarity */
893 switch (mp_bus_id_to_type[bus])
895 case MP_BUS_ISA: /* ISA pin */
897 polarity = default_ISA_polarity(idx);
900 case MP_BUS_EISA: /* EISA pin */
902 polarity = default_EISA_polarity(idx);
905 case MP_BUS_PCI: /* PCI pin */
907 polarity = default_PCI_polarity(idx);
910 case MP_BUS_MCA: /* MCA pin */
912 polarity = default_MCA_polarity(idx);
915 case MP_BUS_NEC98: /* NEC 98 pin */
917 polarity = default_NEC98_polarity(idx);
922 printk(KERN_WARNING "broken BIOS!!\n");
929 case 1: /* high active */
934 case 2: /* reserved */
936 printk(KERN_WARNING "broken BIOS!!\n");
940 case 3: /* low active */
945 default: /* invalid */
947 printk(KERN_WARNING "broken BIOS!!\n");
955 static int MPBIOS_trigger(int idx)
957 int bus = mp_irqs[idx].mpc_srcbus;
961 * Determine IRQ trigger mode (edge or level sensitive):
963 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
965 case 0: /* conforms, ie. bus-type dependent */
967 switch (mp_bus_id_to_type[bus])
969 case MP_BUS_ISA: /* ISA pin */
971 trigger = default_ISA_trigger(idx);
974 case MP_BUS_EISA: /* EISA pin */
976 trigger = default_EISA_trigger(idx);
979 case MP_BUS_PCI: /* PCI pin */
981 trigger = default_PCI_trigger(idx);
984 case MP_BUS_MCA: /* MCA pin */
986 trigger = default_MCA_trigger(idx);
989 case MP_BUS_NEC98: /* NEC 98 pin */
991 trigger = default_NEC98_trigger(idx);
996 printk(KERN_WARNING "broken BIOS!!\n");
1008 case 2: /* reserved */
1010 printk(KERN_WARNING "broken BIOS!!\n");
1019 default: /* invalid */
1021 printk(KERN_WARNING "broken BIOS!!\n");
1029 static inline int irq_polarity(int idx)
1031 return MPBIOS_polarity(idx);
1034 static inline int irq_trigger(int idx)
1036 return MPBIOS_trigger(idx);
1039 static int pin_2_irq(int idx, int apic, int pin)
1042 int bus = mp_irqs[idx].mpc_srcbus;
1045 * Debugging check, we are in big trouble if this message pops up!
1047 if (mp_irqs[idx].mpc_dstirq != pin)
1048 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1050 switch (mp_bus_id_to_type[bus])
1052 case MP_BUS_ISA: /* ISA pin */
1057 irq = mp_irqs[idx].mpc_srcbusirq;
1060 case MP_BUS_PCI: /* PCI pin */
1063 * PCI IRQs are mapped in order
1067 irq += nr_ioapic_registers[i++];
1071 * For MPS mode, so far only needed by ES7000 platform
1073 if (ioapic_renumber_irq)
1074 irq = ioapic_renumber_irq(apic, irq);
1080 printk(KERN_ERR "unknown bus type %d.\n",bus);
1087 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1089 if ((pin >= 16) && (pin <= 23)) {
1090 if (pirq_entries[pin-16] != -1) {
1091 if (!pirq_entries[pin-16]) {
1092 apic_printk(APIC_VERBOSE, KERN_DEBUG
1093 "disabling PIRQ%d\n", pin-16);
1095 irq = pirq_entries[pin-16];
1096 apic_printk(APIC_VERBOSE, KERN_DEBUG
1097 "using PIRQ%d -> IRQ %d\n",
1105 static inline int IO_APIC_irq_trigger(int irq)
1109 for (apic = 0; apic < nr_ioapics; apic++) {
1110 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1111 idx = find_irq_entry(apic,pin,mp_INT);
1112 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1113 return irq_trigger(idx);
1117 * nonexistent IRQs are edge default
1122 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1123 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1125 int assign_irq_vector(int irq)
1127 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1129 BUG_ON(irq >= NR_IRQ_VECTORS);
1130 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1131 return IO_APIC_VECTOR(irq);
1133 current_vector += 8;
1134 if (current_vector == SYSCALL_VECTOR)
1137 if (current_vector >= FIRST_SYSTEM_VECTOR) {
1141 current_vector = FIRST_DEVICE_VECTOR + offset;
1144 vector_irq[current_vector] = irq;
1145 if (irq != AUTO_ASSIGN)
1146 IO_APIC_VECTOR(irq) = current_vector;
1148 return current_vector;
1151 static struct hw_interrupt_type ioapic_level_type;
1152 static struct hw_interrupt_type ioapic_edge_type;
1154 #define IOAPIC_AUTO -1
1155 #define IOAPIC_EDGE 0
1156 #define IOAPIC_LEVEL 1
1158 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1160 if (use_pci_vector() && !platform_legacy_irq(irq)) {
1161 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1162 trigger == IOAPIC_LEVEL)
1163 irq_desc[vector].handler = &ioapic_level_type;
1165 irq_desc[vector].handler = &ioapic_edge_type;
1166 set_intr_gate(vector, interrupt[vector]);
1168 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1169 trigger == IOAPIC_LEVEL)
1170 irq_desc[irq].handler = &ioapic_level_type;
1172 irq_desc[irq].handler = &ioapic_edge_type;
1173 set_intr_gate(vector, interrupt[irq]);
1177 static void __init setup_IO_APIC_irqs(void)
1179 struct IO_APIC_route_entry entry;
1180 int apic, pin, idx, irq, first_notcon = 1, vector;
1181 unsigned long flags;
1183 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1185 for (apic = 0; apic < nr_ioapics; apic++) {
1186 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1189 * add it to the IO-APIC irq-routing table:
1191 memset(&entry,0,sizeof(entry));
1193 entry.delivery_mode = INT_DELIVERY_MODE;
1194 entry.dest_mode = INT_DEST_MODE;
1195 entry.mask = 0; /* enable IRQ */
1196 entry.dest.logical.logical_dest =
1197 cpu_mask_to_apicid(TARGET_CPUS);
1199 idx = find_irq_entry(apic,pin,mp_INT);
1202 apic_printk(APIC_VERBOSE, KERN_DEBUG
1203 " IO-APIC (apicid-pin) %d-%d",
1204 mp_ioapics[apic].mpc_apicid,
1208 apic_printk(APIC_VERBOSE, ", %d-%d",
1209 mp_ioapics[apic].mpc_apicid, pin);
1213 entry.trigger = irq_trigger(idx);
1214 entry.polarity = irq_polarity(idx);
1216 if (irq_trigger(idx)) {
1221 irq = pin_2_irq(idx, apic, pin);
1223 * skip adding the timer int on secondary nodes, which causes
1224 * a small but painful rift in the time-space continuum
1226 if (multi_timer_check(apic, irq))
1229 add_pin_to_irq(irq, apic, pin);
1231 if (!apic && !IO_APIC_IRQ(irq))
1234 if (IO_APIC_IRQ(irq)) {
1235 vector = assign_irq_vector(irq);
1236 entry.vector = vector;
1237 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1239 if (!apic && (irq < 16))
1240 disable_8259A_irq(irq);
1242 spin_lock_irqsave(&ioapic_lock, flags);
1243 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1244 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1245 set_native_irq_info(irq, TARGET_CPUS);
1246 spin_unlock_irqrestore(&ioapic_lock, flags);
1251 apic_printk(APIC_VERBOSE, " not connected.\n");
1255 * Set up the 8259A-master output pin:
1257 static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1259 struct IO_APIC_route_entry entry;
1260 unsigned long flags;
1262 memset(&entry,0,sizeof(entry));
1264 disable_8259A_irq(0);
1267 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1270 * We use logical delivery to get the timer IRQ
1273 entry.dest_mode = INT_DEST_MODE;
1274 entry.mask = 0; /* unmask IRQ now */
1275 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1276 entry.delivery_mode = INT_DELIVERY_MODE;
1279 entry.vector = vector;
1282 * The timer IRQ doesn't have to know that behind the
1283 * scene we have a 8259A-master in AEOI mode ...
1285 irq_desc[0].handler = &ioapic_edge_type;
1288 * Add it to the IO-APIC irq-routing table:
1290 spin_lock_irqsave(&ioapic_lock, flags);
1291 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1292 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1293 spin_unlock_irqrestore(&ioapic_lock, flags);
1295 enable_8259A_irq(0);
1298 static inline void UNEXPECTED_IO_APIC(void)
1302 void __init print_IO_APIC(void)
1305 union IO_APIC_reg_00 reg_00;
1306 union IO_APIC_reg_01 reg_01;
1307 union IO_APIC_reg_02 reg_02;
1308 union IO_APIC_reg_03 reg_03;
1309 unsigned long flags;
1311 if (apic_verbosity == APIC_QUIET)
1314 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1315 for (i = 0; i < nr_ioapics; i++)
1316 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1317 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1320 * We are a bit conservative about what we expect. We have to
1321 * know about every hardware change ASAP.
1323 printk(KERN_INFO "testing the IO APIC.......................\n");
1325 for (apic = 0; apic < nr_ioapics; apic++) {
1327 spin_lock_irqsave(&ioapic_lock, flags);
1328 reg_00.raw = io_apic_read(apic, 0);
1329 reg_01.raw = io_apic_read(apic, 1);
1330 if (reg_01.bits.version >= 0x10)
1331 reg_02.raw = io_apic_read(apic, 2);
1332 if (reg_01.bits.version >= 0x20)
1333 reg_03.raw = io_apic_read(apic, 3);
1334 spin_unlock_irqrestore(&ioapic_lock, flags);
1336 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1337 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1338 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1339 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1340 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1341 if (reg_00.bits.ID >= get_physical_broadcast())
1342 UNEXPECTED_IO_APIC();
1343 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1344 UNEXPECTED_IO_APIC();
1346 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1347 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1348 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1349 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1350 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1351 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1352 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1353 (reg_01.bits.entries != 0x2E) &&
1354 (reg_01.bits.entries != 0x3F)
1356 UNEXPECTED_IO_APIC();
1358 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1359 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1360 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1361 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1362 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1363 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1364 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1366 UNEXPECTED_IO_APIC();
1367 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1368 UNEXPECTED_IO_APIC();
1371 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1372 * but the value of reg_02 is read as the previous read register
1373 * value, so ignore it if reg_02 == reg_01.
1375 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1376 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1377 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1378 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1379 UNEXPECTED_IO_APIC();
1383 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1384 * or reg_03, but the value of reg_0[23] is read as the previous read
1385 * register value, so ignore it if reg_03 == reg_0[12].
1387 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1388 reg_03.raw != reg_01.raw) {
1389 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1390 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1391 if (reg_03.bits.__reserved_1)
1392 UNEXPECTED_IO_APIC();
1395 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1397 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1398 " Stat Dest Deli Vect: \n");
1400 for (i = 0; i <= reg_01.bits.entries; i++) {
1401 struct IO_APIC_route_entry entry;
1403 spin_lock_irqsave(&ioapic_lock, flags);
1404 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1405 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1406 spin_unlock_irqrestore(&ioapic_lock, flags);
1408 printk(KERN_DEBUG " %02x %03X %02X ",
1410 entry.dest.logical.logical_dest,
1411 entry.dest.physical.physical_dest
1414 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1419 entry.delivery_status,
1421 entry.delivery_mode,
1426 if (use_pci_vector())
1427 printk(KERN_INFO "Using vector-based indexing\n");
1428 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1429 for (i = 0; i < NR_IRQS; i++) {
1430 struct irq_pin_list *entry = irq_2_pin + i;
1433 if (use_pci_vector() && !platform_legacy_irq(i))
1434 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1436 printk(KERN_DEBUG "IRQ%d ", i);
1438 printk("-> %d:%d", entry->apic, entry->pin);
1441 entry = irq_2_pin + entry->next;
1446 printk(KERN_INFO ".................................... done.\n");
1453 static void print_APIC_bitfield (int base)
1458 if (apic_verbosity == APIC_QUIET)
1461 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1462 for (i = 0; i < 8; i++) {
1463 v = apic_read(base + i*0x10);
1464 for (j = 0; j < 32; j++) {
1474 void /*__init*/ print_local_APIC(void * dummy)
1476 unsigned int v, ver, maxlvt;
1478 if (apic_verbosity == APIC_QUIET)
1481 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1482 smp_processor_id(), hard_smp_processor_id());
1483 v = apic_read(APIC_ID);
1484 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1485 v = apic_read(APIC_LVR);
1486 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1487 ver = GET_APIC_VERSION(v);
1488 maxlvt = get_maxlvt();
1490 v = apic_read(APIC_TASKPRI);
1491 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1493 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1494 v = apic_read(APIC_ARBPRI);
1495 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1496 v & APIC_ARBPRI_MASK);
1497 v = apic_read(APIC_PROCPRI);
1498 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1501 v = apic_read(APIC_EOI);
1502 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1503 v = apic_read(APIC_RRR);
1504 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1505 v = apic_read(APIC_LDR);
1506 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1507 v = apic_read(APIC_DFR);
1508 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1509 v = apic_read(APIC_SPIV);
1510 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1512 printk(KERN_DEBUG "... APIC ISR field:\n");
1513 print_APIC_bitfield(APIC_ISR);
1514 printk(KERN_DEBUG "... APIC TMR field:\n");
1515 print_APIC_bitfield(APIC_TMR);
1516 printk(KERN_DEBUG "... APIC IRR field:\n");
1517 print_APIC_bitfield(APIC_IRR);
1519 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1520 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1521 apic_write(APIC_ESR, 0);
1522 v = apic_read(APIC_ESR);
1523 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1526 v = apic_read(APIC_ICR);
1527 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1528 v = apic_read(APIC_ICR2);
1529 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1531 v = apic_read(APIC_LVTT);
1532 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1534 if (maxlvt > 3) { /* PC is LVT#4. */
1535 v = apic_read(APIC_LVTPC);
1536 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1538 v = apic_read(APIC_LVT0);
1539 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1540 v = apic_read(APIC_LVT1);
1541 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1543 if (maxlvt > 2) { /* ERR is LVT#3. */
1544 v = apic_read(APIC_LVTERR);
1545 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1548 v = apic_read(APIC_TMICT);
1549 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1550 v = apic_read(APIC_TMCCT);
1551 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1552 v = apic_read(APIC_TDCR);
1553 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1557 void print_all_local_APICs (void)
1559 on_each_cpu(print_local_APIC, NULL, 1, 1);
1562 void /*__init*/ print_PIC(void)
1565 unsigned long flags;
1567 if (apic_verbosity == APIC_QUIET)
1570 printk(KERN_DEBUG "\nprinting PIC contents\n");
1572 spin_lock_irqsave(&i8259A_lock, flags);
1574 v = inb(0xa1) << 8 | inb(0x21);
1575 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1577 v = inb(0xa0) << 8 | inb(0x20);
1578 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1582 v = inb(0xa0) << 8 | inb(0x20);
1586 spin_unlock_irqrestore(&i8259A_lock, flags);
1588 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1590 v = inb(0x4d1) << 8 | inb(0x4d0);
1591 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1596 static void __init enable_IO_APIC(void)
1598 union IO_APIC_reg_01 reg_01;
1600 unsigned long flags;
1602 for (i = 0; i < PIN_MAP_SIZE; i++) {
1603 irq_2_pin[i].pin = -1;
1604 irq_2_pin[i].next = 0;
1607 for (i = 0; i < MAX_PIRQS; i++)
1608 pirq_entries[i] = -1;
1611 * The number of IO-APIC IRQ registers (== #pins):
1613 for (i = 0; i < nr_ioapics; i++) {
1614 spin_lock_irqsave(&ioapic_lock, flags);
1615 reg_01.raw = io_apic_read(i, 1);
1616 spin_unlock_irqrestore(&ioapic_lock, flags);
1617 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1621 * Do not trust the IO-APIC being empty at bootup
1627 * Not an __init, needed by the reboot code
1629 void disable_IO_APIC(void)
1633 * Clear the IO-APIC before rebooting:
1638 * If the i8259 is routed through an IOAPIC
1639 * Put that IOAPIC in virtual wire mode
1640 * so legacy interrupts can be delivered.
1642 pin = find_isa_irq_pin(0, mp_ExtINT);
1644 struct IO_APIC_route_entry entry;
1645 unsigned long flags;
1647 memset(&entry, 0, sizeof(entry));
1648 entry.mask = 0; /* Enabled */
1649 entry.trigger = 0; /* Edge */
1651 entry.polarity = 0; /* High */
1652 entry.delivery_status = 0;
1653 entry.dest_mode = 0; /* Physical */
1654 entry.delivery_mode = 7; /* ExtInt */
1656 entry.dest.physical.physical_dest = 0;
1660 * Add it to the IO-APIC irq-routing table:
1662 spin_lock_irqsave(&ioapic_lock, flags);
1663 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1664 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1665 spin_unlock_irqrestore(&ioapic_lock, flags);
1667 disconnect_bsp_APIC(pin != -1);
1671 * function to set the IO-APIC physical IDs based on the
1672 * values stored in the MPC table.
1674 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1677 #ifndef CONFIG_X86_NUMAQ
1678 static void __init setup_ioapic_ids_from_mpc(void)
1680 union IO_APIC_reg_00 reg_00;
1681 physid_mask_t phys_id_present_map;
1684 unsigned char old_id;
1685 unsigned long flags;
1688 * Don't check I/O APIC IDs for xAPIC systems. They have
1689 * no meaning without the serial APIC bus.
1691 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 < 15))
1694 * This is broken; anything with a real cpu count has to
1695 * circumvent this idiocy regardless.
1697 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1700 * Set the IOAPIC ID to the value stored in the MPC table.
1702 for (apic = 0; apic < nr_ioapics; apic++) {
1704 /* Read the register 0 value */
1705 spin_lock_irqsave(&ioapic_lock, flags);
1706 reg_00.raw = io_apic_read(apic, 0);
1707 spin_unlock_irqrestore(&ioapic_lock, flags);
1709 old_id = mp_ioapics[apic].mpc_apicid;
1711 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1712 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1713 apic, mp_ioapics[apic].mpc_apicid);
1714 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1716 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1720 * Sanity check, is the ID really free? Every APIC in a
1721 * system must have a unique ID or we get lots of nice
1722 * 'stuck on smp_invalidate_needed IPI wait' messages.
1724 if (check_apicid_used(phys_id_present_map,
1725 mp_ioapics[apic].mpc_apicid)) {
1726 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1727 apic, mp_ioapics[apic].mpc_apicid);
1728 for (i = 0; i < get_physical_broadcast(); i++)
1729 if (!physid_isset(i, phys_id_present_map))
1731 if (i >= get_physical_broadcast())
1732 panic("Max APIC ID exceeded!\n");
1733 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1735 physid_set(i, phys_id_present_map);
1736 mp_ioapics[apic].mpc_apicid = i;
1739 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1740 apic_printk(APIC_VERBOSE, "Setting %d in the "
1741 "phys_id_present_map\n",
1742 mp_ioapics[apic].mpc_apicid);
1743 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1748 * We need to adjust the IRQ routing table
1749 * if the ID changed.
1751 if (old_id != mp_ioapics[apic].mpc_apicid)
1752 for (i = 0; i < mp_irq_entries; i++)
1753 if (mp_irqs[i].mpc_dstapic == old_id)
1754 mp_irqs[i].mpc_dstapic
1755 = mp_ioapics[apic].mpc_apicid;
1758 * Read the right value from the MPC table and
1759 * write it into the ID register.
1761 apic_printk(APIC_VERBOSE, KERN_INFO
1762 "...changing IO-APIC physical APIC ID to %d ...",
1763 mp_ioapics[apic].mpc_apicid);
1765 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1766 spin_lock_irqsave(&ioapic_lock, flags);
1767 io_apic_write(apic, 0, reg_00.raw);
1768 spin_unlock_irqrestore(&ioapic_lock, flags);
1773 spin_lock_irqsave(&ioapic_lock, flags);
1774 reg_00.raw = io_apic_read(apic, 0);
1775 spin_unlock_irqrestore(&ioapic_lock, flags);
1776 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1777 printk("could not set ID!\n");
1779 apic_printk(APIC_VERBOSE, " ok.\n");
1783 static void __init setup_ioapic_ids_from_mpc(void) { }
1787 * There is a nasty bug in some older SMP boards, their mptable lies
1788 * about the timer IRQ. We do the following to work around the situation:
1790 * - timer IRQ defaults to IO-APIC IRQ
1791 * - if this function detects that timer IRQs are defunct, then we fall
1792 * back to ISA timer IRQs
1794 static int __init timer_irq_works(void)
1796 unsigned long t1 = jiffies;
1799 /* Let ten ticks pass... */
1800 mdelay((10 * 1000) / HZ);
1803 * Expect a few ticks at least, to be sure some possible
1804 * glue logic does not lock up after one or two first
1805 * ticks in a non-ExtINT mode. Also the local APIC
1806 * might have cached one ExtINT interrupt. Finally, at
1807 * least one tick may be lost due to delays.
1809 if (jiffies - t1 > 4)
1816 * In the SMP+IOAPIC case it might happen that there are an unspecified
1817 * number of pending IRQ events unhandled. These cases are very rare,
1818 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1819 * better to do it this way as thus we do not have to be aware of
1820 * 'pending' interrupts in the IRQ path, except at this point.
1823 * Edge triggered needs to resend any interrupt
1824 * that was delayed but this is now handled in the device
1829 * Starting up a edge-triggered IO-APIC interrupt is
1830 * nasty - we need to make sure that we get the edge.
1831 * If it is already asserted for some reason, we need
1832 * return 1 to indicate that is was pending.
1834 * This is not complete - we should be able to fake
1835 * an edge even if it isn't on the 8259A...
1837 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1839 int was_pending = 0;
1840 unsigned long flags;
1842 spin_lock_irqsave(&ioapic_lock, flags);
1844 disable_8259A_irq(irq);
1845 if (i8259A_irq_pending(irq))
1848 __unmask_IO_APIC_irq(irq);
1849 spin_unlock_irqrestore(&ioapic_lock, flags);
1855 * Once we have recorded IRQ_PENDING already, we can mask the
1856 * interrupt for real. This prevents IRQ storms from unhandled
1859 static void ack_edge_ioapic_irq(unsigned int irq)
1862 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1863 == (IRQ_PENDING | IRQ_DISABLED))
1864 mask_IO_APIC_irq(irq);
1869 * Level triggered interrupts can just be masked,
1870 * and shutting down and starting up the interrupt
1871 * is the same as enabling and disabling them -- except
1872 * with a startup need to return a "was pending" value.
1874 * Level triggered interrupts are special because we
1875 * do not touch any IO-APIC register while handling
1876 * them. We ack the APIC in the end-IRQ handler, not
1877 * in the start-IRQ-handler. Protection against reentrance
1878 * from the same interrupt is still provided, both by the
1879 * generic IRQ layer and by the fact that an unacked local
1880 * APIC does not accept IRQs.
1882 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1884 unmask_IO_APIC_irq(irq);
1886 return 0; /* don't check for pending */
1889 static void end_level_ioapic_irq (unsigned int irq)
1896 * It appears there is an erratum which affects at least version 0x11
1897 * of I/O APIC (that's the 82093AA and cores integrated into various
1898 * chipsets). Under certain conditions a level-triggered interrupt is
1899 * erroneously delivered as edge-triggered one but the respective IRR
1900 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1901 * message but it will never arrive and further interrupts are blocked
1902 * from the source. The exact reason is so far unknown, but the
1903 * phenomenon was observed when two consecutive interrupt requests
1904 * from a given source get delivered to the same CPU and the source is
1905 * temporarily disabled in between.
1907 * A workaround is to simulate an EOI message manually. We achieve it
1908 * by setting the trigger mode to edge and then to level when the edge
1909 * trigger mode gets detected in the TMR of a local APIC for a
1910 * level-triggered interrupt. We mask the source for the time of the
1911 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1912 * The idea is from Manfred Spraul. --macro
1914 i = IO_APIC_VECTOR(irq);
1916 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1920 if (!(v & (1 << (i & 0x1f)))) {
1921 atomic_inc(&irq_mis_count);
1922 spin_lock(&ioapic_lock);
1923 __mask_and_edge_IO_APIC_irq(irq);
1924 __unmask_and_level_IO_APIC_irq(irq);
1925 spin_unlock(&ioapic_lock);
1929 #ifdef CONFIG_PCI_MSI
1930 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1932 int irq = vector_to_irq(vector);
1934 return startup_edge_ioapic_irq(irq);
1937 static void ack_edge_ioapic_vector(unsigned int vector)
1939 int irq = vector_to_irq(vector);
1942 ack_edge_ioapic_irq(irq);
1945 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1947 int irq = vector_to_irq(vector);
1949 return startup_level_ioapic_irq (irq);
1952 static void end_level_ioapic_vector (unsigned int vector)
1954 int irq = vector_to_irq(vector);
1957 end_level_ioapic_irq(irq);
1960 static void mask_IO_APIC_vector (unsigned int vector)
1962 int irq = vector_to_irq(vector);
1964 mask_IO_APIC_irq(irq);
1967 static void unmask_IO_APIC_vector (unsigned int vector)
1969 int irq = vector_to_irq(vector);
1971 unmask_IO_APIC_irq(irq);
1975 static void set_ioapic_affinity_vector (unsigned int vector,
1978 int irq = vector_to_irq(vector);
1980 set_native_irq_info(vector, cpu_mask);
1981 set_ioapic_affinity_irq(irq, cpu_mask);
1987 * Level and edge triggered IO-APIC interrupts need different handling,
1988 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1989 * handled with the level-triggered descriptor, but that one has slightly
1990 * more overhead. Level-triggered interrupts cannot be handled with the
1991 * edge-triggered handler, without risking IRQ storms and other ugly
1994 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1995 .typename = "IO-APIC-edge",
1996 .startup = startup_edge_ioapic,
1997 .shutdown = shutdown_edge_ioapic,
1998 .enable = enable_edge_ioapic,
1999 .disable = disable_edge_ioapic,
2000 .ack = ack_edge_ioapic,
2001 .end = end_edge_ioapic,
2003 .set_affinity = set_ioapic_affinity,
2007 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2008 .typename = "IO-APIC-level",
2009 .startup = startup_level_ioapic,
2010 .shutdown = shutdown_level_ioapic,
2011 .enable = enable_level_ioapic,
2012 .disable = disable_level_ioapic,
2013 .ack = mask_and_ack_level_ioapic,
2014 .end = end_level_ioapic,
2016 .set_affinity = set_ioapic_affinity,
2020 static inline void init_IO_APIC_traps(void)
2025 * NOTE! The local APIC isn't very good at handling
2026 * multiple interrupts at the same interrupt level.
2027 * As the interrupt level is determined by taking the
2028 * vector number and shifting that right by 4, we
2029 * want to spread these out a bit so that they don't
2030 * all fall in the same interrupt level.
2032 * Also, we've got to be careful not to trash gate
2033 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2035 for (irq = 0; irq < NR_IRQS ; irq++) {
2037 if (use_pci_vector()) {
2038 if (!platform_legacy_irq(tmp))
2039 if ((tmp = vector_to_irq(tmp)) == -1)
2042 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2044 * Hmm.. We don't have an entry for this,
2045 * so default to an old-fashioned 8259
2046 * interrupt if we can..
2049 make_8259A_irq(irq);
2051 /* Strange. Oh, well.. */
2052 irq_desc[irq].handler = &no_irq_type;
2057 static void enable_lapic_irq (unsigned int irq)
2061 v = apic_read(APIC_LVT0);
2062 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2065 static void disable_lapic_irq (unsigned int irq)
2069 v = apic_read(APIC_LVT0);
2070 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2073 static void ack_lapic_irq (unsigned int irq)
2078 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2080 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2081 .typename = "local-APIC-edge",
2082 .startup = NULL, /* startup_irq() not used for IRQ0 */
2083 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
2084 .enable = enable_lapic_irq,
2085 .disable = disable_lapic_irq,
2086 .ack = ack_lapic_irq,
2087 .end = end_lapic_irq
2090 static void setup_nmi (void)
2093 * Dirty trick to enable the NMI watchdog ...
2094 * We put the 8259A master into AEOI mode and
2095 * unmask on all local APICs LVT0 as NMI.
2097 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2098 * is from Maciej W. Rozycki - so we do not have to EOI from
2099 * the NMI handler or the timer interrupt.
2101 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2103 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2105 apic_printk(APIC_VERBOSE, " done.\n");
2109 * This looks a bit hackish but it's about the only one way of sending
2110 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2111 * not support the ExtINT mode, unfortunately. We need to send these
2112 * cycles as some i82489DX-based boards have glue logic that keeps the
2113 * 8259A interrupt line asserted until INTA. --macro
2115 static inline void unlock_ExtINT_logic(void)
2118 struct IO_APIC_route_entry entry0, entry1;
2119 unsigned char save_control, save_freq_select;
2120 unsigned long flags;
2122 pin = find_isa_irq_pin(8, mp_INT);
2126 spin_lock_irqsave(&ioapic_lock, flags);
2127 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2128 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2129 spin_unlock_irqrestore(&ioapic_lock, flags);
2130 clear_IO_APIC_pin(0, pin);
2132 memset(&entry1, 0, sizeof(entry1));
2134 entry1.dest_mode = 0; /* physical delivery */
2135 entry1.mask = 0; /* unmask IRQ now */
2136 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2137 entry1.delivery_mode = dest_ExtINT;
2138 entry1.polarity = entry0.polarity;
2142 spin_lock_irqsave(&ioapic_lock, flags);
2143 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2144 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2145 spin_unlock_irqrestore(&ioapic_lock, flags);
2147 save_control = CMOS_READ(RTC_CONTROL);
2148 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2149 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2151 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2156 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2160 CMOS_WRITE(save_control, RTC_CONTROL);
2161 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2162 clear_IO_APIC_pin(0, pin);
2164 spin_lock_irqsave(&ioapic_lock, flags);
2165 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2166 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2167 spin_unlock_irqrestore(&ioapic_lock, flags);
2171 * This code may look a bit paranoid, but it's supposed to cooperate with
2172 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2173 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2174 * fanatically on his truly buggy board.
2176 static inline void check_timer(void)
2182 * get/set the timer IRQ vector:
2184 disable_8259A_irq(0);
2185 vector = assign_irq_vector(0);
2186 set_intr_gate(vector, interrupt[0]);
2189 * Subtle, code in do_timer_interrupt() expects an AEOI
2190 * mode for the 8259A whenever interrupts are routed
2191 * through I/O APICs. Also IRQ0 has to be enabled in
2192 * the 8259A which implies the virtual wire has to be
2193 * disabled in the local APIC.
2195 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2198 enable_8259A_irq(0);
2200 pin1 = find_isa_irq_pin(0, mp_INT);
2201 pin2 = find_isa_irq_pin(0, mp_ExtINT);
2203 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2207 * Ok, does IRQ0 through the IOAPIC work?
2209 unmask_IO_APIC_irq(0);
2210 if (timer_irq_works()) {
2211 if (nmi_watchdog == NMI_IO_APIC) {
2212 disable_8259A_irq(0);
2214 enable_8259A_irq(0);
2216 if (disable_timer_pin_1 > 0)
2217 clear_IO_APIC_pin(0, pin1);
2220 clear_IO_APIC_pin(0, pin1);
2221 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2224 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2226 printk("\n..... (found pin %d) ...", pin2);
2228 * legacy devices should be connected to IO APIC #0
2230 setup_ExtINT_IRQ0_pin(pin2, vector);
2231 if (timer_irq_works()) {
2234 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2236 add_pin_to_irq(0, 0, pin2);
2237 if (nmi_watchdog == NMI_IO_APIC) {
2243 * Cleanup, just in case ...
2245 clear_IO_APIC_pin(0, pin2);
2247 printk(" failed.\n");
2249 if (nmi_watchdog == NMI_IO_APIC) {
2250 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2254 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2256 disable_8259A_irq(0);
2257 irq_desc[0].handler = &lapic_irq_type;
2258 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2259 enable_8259A_irq(0);
2261 if (timer_irq_works()) {
2262 printk(" works.\n");
2265 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2266 printk(" failed.\n");
2268 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2273 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2275 unlock_ExtINT_logic();
2277 if (timer_irq_works()) {
2278 printk(" works.\n");
2281 printk(" failed :(.\n");
2282 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2283 "report. Then try booting with the 'noapic' option");
2288 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2289 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2290 * Linux doesn't really care, as it's not actually used
2291 * for any interrupt handling anyway.
2293 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2295 void __init setup_IO_APIC(void)
2300 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2302 io_apic_irqs = ~PIC_IRQS;
2304 printk("ENABLING IO-APIC IRQs\n");
2307 * Set up IO-APIC IRQ routing.
2310 setup_ioapic_ids_from_mpc();
2312 setup_IO_APIC_irqs();
2313 init_IO_APIC_traps();
2320 * Called after all the initialization is done. If we didnt find any
2321 * APIC bugs then we can allow the modify fast path
2324 static int __init io_apic_bug_finalize(void)
2326 if(sis_apic_bug == -1)
2331 late_initcall(io_apic_bug_finalize);
2333 struct sysfs_ioapic_data {
2334 struct sys_device dev;
2335 struct IO_APIC_route_entry entry[0];
2337 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2339 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2341 struct IO_APIC_route_entry *entry;
2342 struct sysfs_ioapic_data *data;
2343 unsigned long flags;
2346 data = container_of(dev, struct sysfs_ioapic_data, dev);
2347 entry = data->entry;
2348 spin_lock_irqsave(&ioapic_lock, flags);
2349 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2350 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2351 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2353 spin_unlock_irqrestore(&ioapic_lock, flags);
2358 static int ioapic_resume(struct sys_device *dev)
2360 struct IO_APIC_route_entry *entry;
2361 struct sysfs_ioapic_data *data;
2362 unsigned long flags;
2363 union IO_APIC_reg_00 reg_00;
2366 data = container_of(dev, struct sysfs_ioapic_data, dev);
2367 entry = data->entry;
2369 spin_lock_irqsave(&ioapic_lock, flags);
2370 reg_00.raw = io_apic_read(dev->id, 0);
2371 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2372 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2373 io_apic_write(dev->id, 0, reg_00.raw);
2375 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2376 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2377 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2379 spin_unlock_irqrestore(&ioapic_lock, flags);
2384 static struct sysdev_class ioapic_sysdev_class = {
2385 set_kset_name("ioapic"),
2386 .suspend = ioapic_suspend,
2387 .resume = ioapic_resume,
2390 static int __init ioapic_init_sysfs(void)
2392 struct sys_device * dev;
2393 int i, size, error = 0;
2395 error = sysdev_class_register(&ioapic_sysdev_class);
2399 for (i = 0; i < nr_ioapics; i++ ) {
2400 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2401 * sizeof(struct IO_APIC_route_entry);
2402 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2403 if (!mp_ioapic_data[i]) {
2404 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2407 memset(mp_ioapic_data[i], 0, size);
2408 dev = &mp_ioapic_data[i]->dev;
2410 dev->cls = &ioapic_sysdev_class;
2411 error = sysdev_register(dev);
2413 kfree(mp_ioapic_data[i]);
2414 mp_ioapic_data[i] = NULL;
2415 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2423 device_initcall(ioapic_init_sysfs);
2425 /* --------------------------------------------------------------------------
2426 ACPI-based IOAPIC Configuration
2427 -------------------------------------------------------------------------- */
2431 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2433 union IO_APIC_reg_00 reg_00;
2434 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2436 unsigned long flags;
2440 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2441 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2442 * supports up to 16 on one shared APIC bus.
2444 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2445 * advantage of new APIC bus architecture.
2448 if (physids_empty(apic_id_map))
2449 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2451 spin_lock_irqsave(&ioapic_lock, flags);
2452 reg_00.raw = io_apic_read(ioapic, 0);
2453 spin_unlock_irqrestore(&ioapic_lock, flags);
2455 if (apic_id >= get_physical_broadcast()) {
2456 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2457 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2458 apic_id = reg_00.bits.ID;
2462 * Every APIC in a system must have a unique ID or we get lots of nice
2463 * 'stuck on smp_invalidate_needed IPI wait' messages.
2465 if (check_apicid_used(apic_id_map, apic_id)) {
2467 for (i = 0; i < get_physical_broadcast(); i++) {
2468 if (!check_apicid_used(apic_id_map, i))
2472 if (i == get_physical_broadcast())
2473 panic("Max apic_id exceeded!\n");
2475 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2476 "trying %d\n", ioapic, apic_id, i);
2481 tmp = apicid_to_cpu_present(apic_id);
2482 physids_or(apic_id_map, apic_id_map, tmp);
2484 if (reg_00.bits.ID != apic_id) {
2485 reg_00.bits.ID = apic_id;
2487 spin_lock_irqsave(&ioapic_lock, flags);
2488 io_apic_write(ioapic, 0, reg_00.raw);
2489 reg_00.raw = io_apic_read(ioapic, 0);
2490 spin_unlock_irqrestore(&ioapic_lock, flags);
2493 if (reg_00.bits.ID != apic_id)
2494 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2497 apic_printk(APIC_VERBOSE, KERN_INFO
2498 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2504 int __init io_apic_get_version (int ioapic)
2506 union IO_APIC_reg_01 reg_01;
2507 unsigned long flags;
2509 spin_lock_irqsave(&ioapic_lock, flags);
2510 reg_01.raw = io_apic_read(ioapic, 1);
2511 spin_unlock_irqrestore(&ioapic_lock, flags);
2513 return reg_01.bits.version;
2517 int __init io_apic_get_redir_entries (int ioapic)
2519 union IO_APIC_reg_01 reg_01;
2520 unsigned long flags;
2522 spin_lock_irqsave(&ioapic_lock, flags);
2523 reg_01.raw = io_apic_read(ioapic, 1);
2524 spin_unlock_irqrestore(&ioapic_lock, flags);
2526 return reg_01.bits.entries;
2530 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2532 struct IO_APIC_route_entry entry;
2533 unsigned long flags;
2535 if (!IO_APIC_IRQ(irq)) {
2536 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2542 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2543 * Note that we mask (disable) IRQs now -- these get enabled when the
2544 * corresponding device driver registers for this IRQ.
2547 memset(&entry,0,sizeof(entry));
2549 entry.delivery_mode = INT_DELIVERY_MODE;
2550 entry.dest_mode = INT_DEST_MODE;
2551 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2552 entry.trigger = edge_level;
2553 entry.polarity = active_high_low;
2557 * IRQs < 16 are already in the irq_2_pin[] map
2560 add_pin_to_irq(irq, ioapic, pin);
2562 entry.vector = assign_irq_vector(irq);
2564 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2565 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2566 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2567 edge_level, active_high_low);
2569 ioapic_register_intr(irq, entry.vector, edge_level);
2571 if (!ioapic && (irq < 16))
2572 disable_8259A_irq(irq);
2574 spin_lock_irqsave(&ioapic_lock, flags);
2575 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2576 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2577 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2578 spin_unlock_irqrestore(&ioapic_lock, flags);
2583 #endif /* CONFIG_ACPI */