2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/init.h>
39 #include <linux/kernel.h>
42 #include <linux/sched.h>
43 #include <linux/kernel_stat.h>
44 #include <linux/smp_lock.h>
45 #include <linux/irq.h>
46 #include <linux/bootmem.h>
47 #include <linux/notifier.h>
48 #include <linux/cpu.h>
49 #include <linux/percpu.h>
51 #include <linux/delay.h>
52 #include <linux/mc146818rtc.h>
53 #include <asm/tlbflush.h>
55 #include <asm/arch_hooks.h>
57 #include <mach_apic.h>
58 #include <mach_wakecpu.h>
59 #include <smpboot_hooks.h>
61 /* Set if we find a B stepping CPU */
62 static int __initdata smp_b_stepping;
64 /* Number of siblings per CPU package */
65 int smp_num_siblings = 1;
67 EXPORT_SYMBOL(smp_num_siblings);
70 /* Package ID of each logical CPU */
71 int phys_proc_id[NR_CPUS] = {[0 ... NR_CPUS-1] = BAD_APICID};
72 EXPORT_SYMBOL(phys_proc_id);
74 /* Core ID of each logical CPU */
75 int cpu_core_id[NR_CPUS] = {[0 ... NR_CPUS-1] = BAD_APICID};
76 EXPORT_SYMBOL(cpu_core_id);
78 cpumask_t cpu_sibling_map[NR_CPUS];
79 EXPORT_SYMBOL(cpu_sibling_map);
81 cpumask_t cpu_core_map[NR_CPUS];
82 EXPORT_SYMBOL(cpu_core_map);
84 /* bitmap of online cpus */
85 cpumask_t cpu_online_map;
86 EXPORT_SYMBOL(cpu_online_map);
88 cpumask_t cpu_callin_map;
89 cpumask_t cpu_callout_map;
90 EXPORT_SYMBOL(cpu_callout_map);
91 static cpumask_t smp_commenced_mask;
93 /* Per CPU bogomips and other parameters */
94 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
95 EXPORT_SYMBOL(cpu_data);
97 u8 x86_cpu_to_apicid[NR_CPUS] =
98 { [0 ... NR_CPUS-1] = 0xff };
99 EXPORT_SYMBOL(x86_cpu_to_apicid);
102 * Trampoline 80x86 program as an array.
105 extern unsigned char trampoline_data [];
106 extern unsigned char trampoline_end [];
107 static unsigned char *trampoline_base;
108 static int trampoline_exec;
110 static void map_cpu_to_logical_apicid(void);
112 /* State of each CPU. */
113 DEFINE_PER_CPU(int, cpu_state) = { 0 };
116 * Currently trivial. Write the real->protected mode
117 * bootstrap into the page concerned. The caller
118 * has made sure it's suitably aligned.
121 static unsigned long __init setup_trampoline(void)
123 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
124 return virt_to_phys(trampoline_base);
128 * We are called very early to get the low memory for the
129 * SMP bootup trampoline page.
131 void __init smp_alloc_memory(void)
133 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
135 * Has to be in very low memory so we can execute
138 if (__pa(trampoline_base) >= 0x9F000)
141 * Make the SMP trampoline executable:
143 trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
147 * The bootstrap kernel entry code has set these up. Save them for
151 static void __init smp_store_cpu_info(int id)
153 struct cpuinfo_x86 *c = cpu_data + id;
159 * Mask B, Pentium, but not Pentium MMX
161 if (c->x86_vendor == X86_VENDOR_INTEL &&
163 c->x86_mask >= 1 && c->x86_mask <= 4 &&
166 * Remember we have B step Pentia with bugs
171 * Certain Athlons might work (for various values of 'work') in SMP
172 * but they are not certified as MP capable.
174 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
176 /* Athlon 660/661 is valid. */
177 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
180 /* Duron 670 is valid */
181 if ((c->x86_model==7) && (c->x86_mask==0))
185 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
186 * It's worth noting that the A5 stepping (662) of some Athlon XP's
187 * have the MP bit set.
188 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
190 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
191 ((c->x86_model==7) && (c->x86_mask>=1)) ||
196 /* If we get here, it's not a certified SMP capable AMD system. */
197 tainted |= TAINT_UNSAFE_SMP;
205 * TSC synchronization.
207 * We first check whether all CPUs have their TSC's synchronized,
208 * then we print a warning if not, and always resync.
211 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
212 static atomic_t tsc_count_start = ATOMIC_INIT(0);
213 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
214 static unsigned long long tsc_values[NR_CPUS];
218 static void __init synchronize_tsc_bp (void)
221 unsigned long long t0;
222 unsigned long long sum, avg;
224 unsigned int one_usec;
227 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus());
229 /* convert from kcyc/sec to cyc/usec */
230 one_usec = cpu_khz / 1000;
232 atomic_set(&tsc_start_flag, 1);
236 * We loop a few times to get a primed instruction cache,
237 * then the last pass is more or less synchronized and
238 * the BP and APs set their cycle counters to zero all at
239 * once. This reduces the chance of having random offsets
240 * between the processors, and guarantees that the maximum
241 * delay between the cycle counters is never bigger than
242 * the latency of information-passing (cachelines) between
245 for (i = 0; i < NR_LOOPS; i++) {
247 * all APs synchronize but they loop on '== num_cpus'
249 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1)
251 atomic_set(&tsc_count_stop, 0);
254 * this lets the APs save their current TSC:
256 atomic_inc(&tsc_count_start);
258 rdtscll(tsc_values[smp_processor_id()]);
260 * We clear the TSC in the last loop:
266 * Wait for all APs to leave the synchronization point:
268 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1)
270 atomic_set(&tsc_count_start, 0);
272 atomic_inc(&tsc_count_stop);
276 for (i = 0; i < NR_CPUS; i++) {
277 if (cpu_isset(i, cpu_callout_map)) {
283 do_div(avg, num_booting_cpus());
286 for (i = 0; i < NR_CPUS; i++) {
287 if (!cpu_isset(i, cpu_callout_map))
289 delta = tsc_values[i] - avg;
293 * We report bigger than 2 microseconds clock differences.
295 if (delta > 2*one_usec) {
302 do_div(realdelta, one_usec);
303 if (tsc_values[i] < avg)
304 realdelta = -realdelta;
306 printk(KERN_INFO "CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta);
315 static void __init synchronize_tsc_ap (void)
320 * Not every cpu is online at the time
321 * this gets called, so we first wait for the BP to
322 * finish SMP initialization:
324 while (!atomic_read(&tsc_start_flag)) mb();
326 for (i = 0; i < NR_LOOPS; i++) {
327 atomic_inc(&tsc_count_start);
328 while (atomic_read(&tsc_count_start) != num_booting_cpus())
331 rdtscll(tsc_values[smp_processor_id()]);
335 atomic_inc(&tsc_count_stop);
336 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
341 extern void calibrate_delay(void);
343 static atomic_t init_deasserted;
345 static void __init smp_callin(void)
348 unsigned long timeout;
351 * If waken up by an INIT in an 82489DX configuration
352 * we may get here before an INIT-deassert IPI reaches
353 * our local APIC. We have to wait for the IPI or we'll
354 * lock up on an APIC access.
356 wait_for_init_deassert(&init_deasserted);
359 * (This works even if the APIC is not enabled.)
361 phys_id = GET_APIC_ID(apic_read(APIC_ID));
362 cpuid = smp_processor_id();
363 if (cpu_isset(cpuid, cpu_callin_map)) {
364 printk("huh, phys CPU#%d, CPU#%d already present??\n",
368 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
371 * STARTUP IPIs are fragile beasts as they might sometimes
372 * trigger some glue motherboard logic. Complete APIC bus
373 * silence for 1 second, this overestimates the time the
374 * boot CPU is spending to send the up to 2 STARTUP IPIs
375 * by a factor of two. This should be enough.
379 * Waiting 2s total for startup (udelay is not yet working)
381 timeout = jiffies + 2*HZ;
382 while (time_before(jiffies, timeout)) {
384 * Has the boot CPU finished it's STARTUP sequence?
386 if (cpu_isset(cpuid, cpu_callout_map))
391 if (!time_before(jiffies, timeout)) {
392 printk("BUG: CPU%d started up but did not get a callout!\n",
398 * the boot CPU has finished the init stage and is spinning
399 * on callin_map until we finish. We are free to set up this
400 * CPU, first the APIC. (this is probably redundant on most
404 Dprintk("CALLIN, before setup_local_APIC().\n");
405 smp_callin_clear_local_apic();
407 map_cpu_to_logical_apicid();
413 Dprintk("Stack at about %p\n",&cpuid);
416 * Save our processor parameters
418 smp_store_cpu_info(cpuid);
420 disable_APIC_timer();
423 * Allow the master to continue.
425 cpu_set(cpuid, cpu_callin_map);
428 * Synchronize the TSC with the BP
430 if (cpu_has_tsc && cpu_khz)
431 synchronize_tsc_ap();
437 set_cpu_sibling_map(int cpu)
441 if (smp_num_siblings > 1) {
442 for (i = 0; i < NR_CPUS; i++) {
443 if (!cpu_isset(i, cpu_callout_map))
445 if (cpu_core_id[cpu] == cpu_core_id[i]) {
446 cpu_set(i, cpu_sibling_map[cpu]);
447 cpu_set(cpu, cpu_sibling_map[i]);
451 cpu_set(cpu, cpu_sibling_map[cpu]);
454 if (current_cpu_data.x86_num_cores > 1) {
455 for (i = 0; i < NR_CPUS; i++) {
456 if (!cpu_isset(i, cpu_callout_map))
458 if (phys_proc_id[cpu] == phys_proc_id[i]) {
459 cpu_set(i, cpu_core_map[cpu]);
460 cpu_set(cpu, cpu_core_map[i]);
464 cpu_core_map[cpu] = cpu_sibling_map[cpu];
469 * Activate a secondary processor.
471 static void __init start_secondary(void *unused)
474 * Dont put anything before smp_callin(), SMP
475 * booting is too fragile that we want to limit the
476 * things done here to the most necessary things.
480 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
482 setup_secondary_APIC_clock();
483 if (nmi_watchdog == NMI_IO_APIC) {
484 disable_8259A_irq(0);
485 enable_NMI_through_LVT0(NULL);
490 * low-memory mappings have been cleared, flush them from
491 * the local TLBs too.
495 /* This must be done before setting cpu_online_map */
496 set_cpu_sibling_map(raw_smp_processor_id());
500 * We need to hold call_lock, so there is no inconsistency
501 * between the time smp_call_function() determines number of
502 * IPI receipients, and the time when the determination is made
503 * for which cpus receive the IPI. Holding this
504 * lock helps us to not include this cpu in a currently in progress
505 * smp_call_function().
507 lock_ipi_call_lock();
508 cpu_set(smp_processor_id(), cpu_online_map);
509 unlock_ipi_call_lock();
511 /* We can take interrupts now: we're officially "up". */
519 * Everything has been set up for the secondary
520 * CPUs - they just need to reload everything
521 * from the task structure
522 * This function must not return.
524 void __init initialize_secondary(void)
527 * We don't actually need to load the full TSS,
528 * basically just the stack pointer and the eip.
535 :"r" (current->thread.esp),"r" (current->thread.eip));
545 /* which logical CPUs are on which nodes */
546 cpumask_t node_2_cpu_mask[MAX_NUMNODES] =
547 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
548 /* which node each logical CPU is on */
549 int cpu_2_node[NR_CPUS] = { [0 ... NR_CPUS-1] = 0 };
550 EXPORT_SYMBOL(cpu_2_node);
552 /* set up a mapping between cpu and node. */
553 static inline void map_cpu_to_node(int cpu, int node)
555 printk("Mapping cpu %d to node %d\n", cpu, node);
556 cpu_set(cpu, node_2_cpu_mask[node]);
557 cpu_2_node[cpu] = node;
560 /* undo a mapping between cpu and node. */
561 static inline void unmap_cpu_to_node(int cpu)
565 printk("Unmapping cpu %d from all nodes\n", cpu);
566 for (node = 0; node < MAX_NUMNODES; node ++)
567 cpu_clear(cpu, node_2_cpu_mask[node]);
570 #else /* !CONFIG_NUMA */
572 #define map_cpu_to_node(cpu, node) ({})
573 #define unmap_cpu_to_node(cpu) ({})
575 #endif /* CONFIG_NUMA */
577 u8 cpu_2_logical_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
579 static void map_cpu_to_logical_apicid(void)
581 int cpu = smp_processor_id();
582 int apicid = logical_smp_processor_id();
584 cpu_2_logical_apicid[cpu] = apicid;
585 map_cpu_to_node(cpu, apicid_to_node(apicid));
588 static void unmap_cpu_to_logical_apicid(int cpu)
590 cpu_2_logical_apicid[cpu] = BAD_APICID;
591 unmap_cpu_to_node(cpu);
595 static inline void __inquire_remote_apic(int apicid)
597 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
598 char *names[] = { "ID", "VERSION", "SPIV" };
601 printk("Inquiring remote APIC #%d...\n", apicid);
603 for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
604 printk("... APIC #%d %s: ", apicid, names[i]);
609 apic_wait_icr_idle();
611 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
612 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
617 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
618 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
621 case APIC_ICR_RR_VALID:
622 status = apic_read(APIC_RRR);
623 printk("%08x\n", status);
632 #ifdef WAKE_SECONDARY_VIA_NMI
634 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
635 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
636 * won't ... remember to clear down the APIC, etc later.
639 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
641 unsigned long send_status = 0, accept_status = 0;
645 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
647 /* Boot on the stack */
648 /* Kick the second */
649 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
651 Dprintk("Waiting for send to finish...\n");
656 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
657 } while (send_status && (timeout++ < 1000));
660 * Give the other CPU some time to accept the IPI.
664 * Due to the Pentium erratum 3AP.
666 maxlvt = get_maxlvt();
668 apic_read_around(APIC_SPIV);
669 apic_write(APIC_ESR, 0);
671 accept_status = (apic_read(APIC_ESR) & 0xEF);
672 Dprintk("NMI sent.\n");
675 printk("APIC never delivered???\n");
677 printk("APIC delivery error (%lx).\n", accept_status);
679 return (send_status | accept_status);
681 #endif /* WAKE_SECONDARY_VIA_NMI */
683 #ifdef WAKE_SECONDARY_VIA_INIT
685 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
687 unsigned long send_status = 0, accept_status = 0;
688 int maxlvt, timeout, num_starts, j;
691 * Be paranoid about clearing APIC errors.
693 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
694 apic_read_around(APIC_SPIV);
695 apic_write(APIC_ESR, 0);
699 Dprintk("Asserting INIT.\n");
702 * Turn INIT on target chip
704 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
709 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
712 Dprintk("Waiting for send to finish...\n");
717 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
718 } while (send_status && (timeout++ < 1000));
722 Dprintk("Deasserting INIT.\n");
725 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
728 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
730 Dprintk("Waiting for send to finish...\n");
735 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
736 } while (send_status && (timeout++ < 1000));
738 atomic_set(&init_deasserted, 1);
741 * Should we send STARTUP IPIs ?
743 * Determine this based on the APIC version.
744 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
746 if (APIC_INTEGRATED(apic_version[phys_apicid]))
752 * Run STARTUP IPI loop.
754 Dprintk("#startup loops: %d.\n", num_starts);
756 maxlvt = get_maxlvt();
758 for (j = 1; j <= num_starts; j++) {
759 Dprintk("Sending STARTUP #%d.\n",j);
760 apic_read_around(APIC_SPIV);
761 apic_write(APIC_ESR, 0);
763 Dprintk("After apic_write.\n");
770 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
772 /* Boot on the stack */
773 /* Kick the second */
774 apic_write_around(APIC_ICR, APIC_DM_STARTUP
775 | (start_eip >> 12));
778 * Give the other CPU some time to accept the IPI.
782 Dprintk("Startup point 1.\n");
784 Dprintk("Waiting for send to finish...\n");
789 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
790 } while (send_status && (timeout++ < 1000));
793 * Give the other CPU some time to accept the IPI.
797 * Due to the Pentium erratum 3AP.
800 apic_read_around(APIC_SPIV);
801 apic_write(APIC_ESR, 0);
803 accept_status = (apic_read(APIC_ESR) & 0xEF);
804 if (send_status || accept_status)
807 Dprintk("After Startup.\n");
810 printk("APIC never delivered???\n");
812 printk("APIC delivery error (%lx).\n", accept_status);
814 return (send_status | accept_status);
816 #endif /* WAKE_SECONDARY_VIA_INIT */
818 extern cpumask_t cpu_initialized;
820 static int __init do_boot_cpu(int apicid)
822 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
823 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
824 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
827 struct task_struct *idle;
828 unsigned long boot_error;
830 unsigned long start_eip;
831 unsigned short nmi_high = 0, nmi_low = 0;
835 * We can't use kernel_thread since we must avoid to
836 * reschedule the child.
838 idle = fork_idle(cpu);
840 panic("failed fork for CPU %d", cpu);
841 idle->thread.eip = (unsigned long) start_secondary;
842 /* start_eip had better be page-aligned! */
843 start_eip = setup_trampoline();
845 /* So we see what's up */
846 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
847 /* Stack for startup_32 can be just as for start_secondary onwards */
848 stack_start.esp = (void *) idle->thread.esp;
853 * This grunge runs the startup process for
854 * the targeted processor.
857 atomic_set(&init_deasserted, 0);
859 Dprintk("Setting warm reset code and vector.\n");
861 store_NMI_vector(&nmi_high, &nmi_low);
863 smpboot_setup_warm_reset_vector(start_eip);
866 * Starting actual IPI sequence...
868 boot_error = wakeup_secondary_cpu(apicid, start_eip);
872 * allow APs to start initializing.
874 Dprintk("Before Callout %d.\n", cpu);
875 cpu_set(cpu, cpu_callout_map);
876 Dprintk("After Callout %d.\n", cpu);
879 * Wait 5s total for a response
881 for (timeout = 0; timeout < 50000; timeout++) {
882 if (cpu_isset(cpu, cpu_callin_map))
883 break; /* It has booted */
887 if (cpu_isset(cpu, cpu_callin_map)) {
888 /* number CPUs logically, starting from 1 (BSP is 0) */
890 printk("CPU%d: ", cpu);
891 print_cpu_info(&cpu_data[cpu]);
892 Dprintk("CPU has booted.\n");
895 if (*((volatile unsigned char *)trampoline_base)
897 /* trampoline started but...? */
898 printk("Stuck ??\n");
900 /* trampoline code not run */
901 printk("Not responding.\n");
902 inquire_remote_apic(apicid);
905 x86_cpu_to_apicid[cpu] = apicid;
907 /* Try to put things back the way they were before ... */
908 unmap_cpu_to_logical_apicid(cpu);
909 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
910 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
914 /* mark "stuck" area as not stuck */
915 *((volatile unsigned long *)trampoline_base) = 0;
920 static void smp_tune_scheduling (void)
922 unsigned long cachesize; /* kB */
923 unsigned long bandwidth = 350; /* MB/s */
925 * Rough estimation for SMP scheduling, this is the number of
926 * cycles it takes for a fully memory-limited process to flush
927 * the SMP-local cache.
929 * (For a P5 this pretty much means we will choose another idle
930 * CPU almost always at wakeup time (this is due to the small
931 * L1 cache), on PIIs it's around 50-100 usecs, depending on
937 * this basically disables processor-affinity
938 * scheduling on SMP without a TSC.
942 cachesize = boot_cpu_data.x86_cache_size;
943 if (cachesize == -1) {
944 cachesize = 16; /* Pentiums, 2x8kB cache */
951 * Cycle through the processors sending APIC IPIs to boot each.
954 static int boot_cpu_logical_apicid;
955 /* Where the IO area was mapped on multiquad, always 0 otherwise */
957 #ifdef CONFIG_X86_NUMAQ
958 EXPORT_SYMBOL(xquad_portio);
961 static void __init smp_boot_cpus(unsigned int max_cpus)
963 int apicid, cpu, bit, kicked;
964 unsigned long bogosum = 0;
967 * Setup boot CPU information
969 smp_store_cpu_info(0); /* Final full version of the data */
970 printk("CPU%d: ", 0);
971 print_cpu_info(&cpu_data[0]);
973 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
974 boot_cpu_logical_apicid = logical_smp_processor_id();
975 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
977 current_thread_info()->cpu = 0;
978 smp_tune_scheduling();
979 cpus_clear(cpu_sibling_map[0]);
980 cpu_set(0, cpu_sibling_map[0]);
982 cpus_clear(cpu_core_map[0]);
983 cpu_set(0, cpu_core_map[0]);
986 * If we couldn't find an SMP configuration at boot time,
987 * get out of here now!
989 if (!smp_found_config && !acpi_lapic) {
990 printk(KERN_NOTICE "SMP motherboard not detected.\n");
991 smpboot_clear_io_apic_irqs();
992 phys_cpu_present_map = physid_mask_of_physid(0);
993 if (APIC_init_uniprocessor())
994 printk(KERN_NOTICE "Local APIC not detected."
995 " Using dummy APIC emulation.\n");
996 map_cpu_to_logical_apicid();
997 cpu_set(0, cpu_sibling_map[0]);
998 cpu_set(0, cpu_core_map[0]);
1003 * Should not be necessary because the MP table should list the boot
1004 * CPU too, but we do it for the sake of robustness anyway.
1005 * Makes no sense to do this check in clustered apic mode, so skip it
1007 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1008 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1009 boot_cpu_physical_apicid);
1010 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1014 * If we couldn't find a local APIC, then get out of here now!
1016 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1017 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1018 boot_cpu_physical_apicid);
1019 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1020 smpboot_clear_io_apic_irqs();
1021 phys_cpu_present_map = physid_mask_of_physid(0);
1022 cpu_set(0, cpu_sibling_map[0]);
1023 cpu_set(0, cpu_core_map[0]);
1027 verify_local_APIC();
1030 * If SMP should be disabled, then really disable it!
1033 smp_found_config = 0;
1034 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1035 smpboot_clear_io_apic_irqs();
1036 phys_cpu_present_map = physid_mask_of_physid(0);
1037 cpu_set(0, cpu_sibling_map[0]);
1038 cpu_set(0, cpu_core_map[0]);
1044 map_cpu_to_logical_apicid();
1047 setup_portio_remap();
1050 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1052 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1053 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1054 * clustered apic ID.
1056 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1059 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
1060 apicid = cpu_present_to_apicid(bit);
1062 * Don't even attempt to start the boot CPU!
1064 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
1067 if (!check_apicid_present(bit))
1069 if (max_cpus <= cpucount+1)
1072 if (do_boot_cpu(apicid))
1073 printk("CPU #%d not responding - cannot use it.\n",
1080 * Cleanup possible dangling ends...
1082 smpboot_restore_warm_reset_vector();
1085 * Allow the user to impress friends.
1087 Dprintk("Before bogomips.\n");
1088 for (cpu = 0; cpu < NR_CPUS; cpu++)
1089 if (cpu_isset(cpu, cpu_callout_map))
1090 bogosum += cpu_data[cpu].loops_per_jiffy;
1092 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1094 bogosum/(500000/HZ),
1095 (bogosum/(5000/HZ))%100);
1097 Dprintk("Before bogocount - setting activated=1.\n");
1100 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1103 * Don't taint if we are running SMP kernel on a single non-MP
1106 if (tainted & TAINT_UNSAFE_SMP) {
1108 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1110 tainted &= ~TAINT_UNSAFE_SMP;
1113 Dprintk("Boot done.\n");
1116 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1119 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1120 cpus_clear(cpu_sibling_map[cpu]);
1121 cpus_clear(cpu_core_map[cpu]);
1124 cpu_set(0, cpu_sibling_map[0]);
1125 cpu_set(0, cpu_core_map[0]);
1127 smpboot_setup_io_apic();
1129 setup_boot_APIC_clock();
1132 * Synchronize the TSC with the AP
1134 if (cpu_has_tsc && cpucount && cpu_khz)
1135 synchronize_tsc_bp();
1138 /* These are wrappers to interface to the new boot process. Someone
1139 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1140 void __init smp_prepare_cpus(unsigned int max_cpus)
1142 smp_commenced_mask = cpumask_of_cpu(0);
1143 cpu_callin_map = cpumask_of_cpu(0);
1145 smp_boot_cpus(max_cpus);
1148 void __devinit smp_prepare_boot_cpu(void)
1150 cpu_set(smp_processor_id(), cpu_online_map);
1151 cpu_set(smp_processor_id(), cpu_callout_map);
1154 #ifdef CONFIG_HOTPLUG_CPU
1156 /* must be called with the cpucontrol mutex held */
1157 static int __devinit cpu_enable(unsigned int cpu)
1159 /* get the target out of its holding state */
1160 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1163 /* wait for the processor to ack it. timeout? */
1164 while (!cpu_online(cpu))
1167 fixup_irqs(cpu_online_map);
1168 /* counter the disable in fixup_irqs() */
1173 int __cpu_disable(void)
1175 cpumask_t map = cpu_online_map;
1176 int cpu = smp_processor_id();
1179 * Perhaps use cpufreq to drop frequency, but that could go
1180 * into generic code.
1182 * We won't take down the boot processor on i386 due to some
1183 * interrupts only being able to be serviced by the BSP.
1184 * Especially so if we're not using an IOAPIC -zwane
1189 /* We enable the timer again on the exit path of the death loop */
1190 disable_APIC_timer();
1191 /* Allow any queued timer interrupts to get serviced */
1194 local_irq_disable();
1196 cpu_clear(cpu, map);
1198 /* It's now safe to remove this processor from the online map */
1199 cpu_clear(cpu, cpu_online_map);
1203 void __cpu_die(unsigned int cpu)
1205 /* We don't do anything here: idle task is faking death itself. */
1208 for (i = 0; i < 10; i++) {
1209 /* They ack this in play_dead by setting CPU_DEAD */
1210 if (per_cpu(cpu_state, cpu) == CPU_DEAD)
1212 current->state = TASK_UNINTERRUPTIBLE;
1213 schedule_timeout(HZ/10);
1215 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1217 #else /* ... !CONFIG_HOTPLUG_CPU */
1218 int __cpu_disable(void)
1223 void __cpu_die(unsigned int cpu)
1225 /* We said "no" in __cpu_disable */
1228 #endif /* CONFIG_HOTPLUG_CPU */
1230 int __devinit __cpu_up(unsigned int cpu)
1232 /* In case one didn't come up */
1233 if (!cpu_isset(cpu, cpu_callin_map)) {
1234 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1239 #ifdef CONFIG_HOTPLUG_CPU
1240 /* Already up, and in cpu_quiescent now? */
1241 if (cpu_isset(cpu, smp_commenced_mask)) {
1248 /* Unleash the CPU! */
1249 cpu_set(cpu, smp_commenced_mask);
1250 while (!cpu_isset(cpu, cpu_online_map))
1255 void __init smp_cpus_done(unsigned int max_cpus)
1257 #ifdef CONFIG_X86_IO_APIC
1258 setup_ioapic_dest();
1262 * Disable executability of the SMP trampoline:
1264 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1267 void __init smp_intr_init(void)
1270 * IRQ0 must be given a fixed assignment and initialized,
1271 * because it's used before the IO-APIC is set up.
1273 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1276 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1277 * IPI, driven by wakeup.
1279 set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1281 /* IPI for invalidation */
1282 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1284 /* IPI for generic function call */
1285 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);