2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/init.h>
39 #include <linux/kernel.h>
42 #include <linux/sched.h>
43 #include <linux/kernel_stat.h>
44 #include <linux/smp_lock.h>
45 #include <linux/bootmem.h>
46 #include <linux/notifier.h>
47 #include <linux/cpu.h>
48 #include <linux/percpu.h>
50 #include <linux/delay.h>
51 #include <linux/mc146818rtc.h>
52 #include <asm/tlbflush.h>
54 #include <asm/arch_hooks.h>
56 #include <mach_apic.h>
57 #include <mach_wakecpu.h>
58 #include <smpboot_hooks.h>
60 /* Set if we find a B stepping CPU */
61 static int __devinitdata smp_b_stepping;
63 /* Number of siblings per CPU package */
64 int smp_num_siblings = 1;
66 EXPORT_SYMBOL(smp_num_siblings);
69 /* Package ID of each logical CPU */
70 int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
71 EXPORT_SYMBOL(phys_proc_id);
73 /* Core ID of each logical CPU */
74 int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
75 EXPORT_SYMBOL(cpu_core_id);
77 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
78 EXPORT_SYMBOL(cpu_sibling_map);
80 cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
81 EXPORT_SYMBOL(cpu_core_map);
83 /* bitmap of online cpus */
84 cpumask_t cpu_online_map __read_mostly;
85 EXPORT_SYMBOL(cpu_online_map);
87 cpumask_t cpu_callin_map;
88 cpumask_t cpu_callout_map;
89 EXPORT_SYMBOL(cpu_callout_map);
90 #ifdef CONFIG_HOTPLUG_CPU
91 cpumask_t cpu_possible_map = CPU_MASK_ALL;
93 cpumask_t cpu_possible_map;
95 EXPORT_SYMBOL(cpu_possible_map);
96 static cpumask_t smp_commenced_mask;
98 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
99 * is no way to resync one AP against BP. TBD: for prescott and above, we
100 * should use IA64's algorithm
102 static int __devinitdata tsc_sync_disabled;
104 /* Per CPU bogomips and other parameters */
105 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
106 EXPORT_SYMBOL(cpu_data);
108 u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
109 { [0 ... NR_CPUS-1] = 0xff };
110 EXPORT_SYMBOL(x86_cpu_to_apicid);
113 * Trampoline 80x86 program as an array.
116 extern unsigned char trampoline_data [];
117 extern unsigned char trampoline_end [];
118 static unsigned char *trampoline_base;
119 static int trampoline_exec;
121 static void map_cpu_to_logical_apicid(void);
123 /* State of each CPU. */
124 DEFINE_PER_CPU(int, cpu_state) = { 0 };
127 * Currently trivial. Write the real->protected mode
128 * bootstrap into the page concerned. The caller
129 * has made sure it's suitably aligned.
132 static unsigned long __devinit setup_trampoline(void)
134 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
135 return virt_to_phys(trampoline_base);
139 * We are called very early to get the low memory for the
140 * SMP bootup trampoline page.
142 void __init smp_alloc_memory(void)
144 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
146 * Has to be in very low memory so we can execute
149 if (__pa(trampoline_base) >= 0x9F000)
152 * Make the SMP trampoline executable:
154 trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
158 * The bootstrap kernel entry code has set these up. Save them for
162 static void __devinit smp_store_cpu_info(int id)
164 struct cpuinfo_x86 *c = cpu_data + id;
170 * Mask B, Pentium, but not Pentium MMX
172 if (c->x86_vendor == X86_VENDOR_INTEL &&
174 c->x86_mask >= 1 && c->x86_mask <= 4 &&
177 * Remember we have B step Pentia with bugs
182 * Certain Athlons might work (for various values of 'work') in SMP
183 * but they are not certified as MP capable.
185 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
187 /* Athlon 660/661 is valid. */
188 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
191 /* Duron 670 is valid */
192 if ((c->x86_model==7) && (c->x86_mask==0))
196 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
197 * It's worth noting that the A5 stepping (662) of some Athlon XP's
198 * have the MP bit set.
199 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
201 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
202 ((c->x86_model==7) && (c->x86_mask>=1)) ||
207 /* If we get here, it's not a certified SMP capable AMD system. */
208 add_taint(TAINT_UNSAFE_SMP);
216 * TSC synchronization.
218 * We first check whether all CPUs have their TSC's synchronized,
219 * then we print a warning if not, and always resync.
222 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
223 static atomic_t tsc_count_start = ATOMIC_INIT(0);
224 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
225 static unsigned long long tsc_values[NR_CPUS];
229 static void __init synchronize_tsc_bp (void)
232 unsigned long long t0;
233 unsigned long long sum, avg;
235 unsigned int one_usec;
238 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus());
240 /* convert from kcyc/sec to cyc/usec */
241 one_usec = cpu_khz / 1000;
243 atomic_set(&tsc_start_flag, 1);
247 * We loop a few times to get a primed instruction cache,
248 * then the last pass is more or less synchronized and
249 * the BP and APs set their cycle counters to zero all at
250 * once. This reduces the chance of having random offsets
251 * between the processors, and guarantees that the maximum
252 * delay between the cycle counters is never bigger than
253 * the latency of information-passing (cachelines) between
256 for (i = 0; i < NR_LOOPS; i++) {
258 * all APs synchronize but they loop on '== num_cpus'
260 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1)
262 atomic_set(&tsc_count_stop, 0);
265 * this lets the APs save their current TSC:
267 atomic_inc(&tsc_count_start);
269 rdtscll(tsc_values[smp_processor_id()]);
271 * We clear the TSC in the last loop:
277 * Wait for all APs to leave the synchronization point:
279 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1)
281 atomic_set(&tsc_count_start, 0);
283 atomic_inc(&tsc_count_stop);
287 for (i = 0; i < NR_CPUS; i++) {
288 if (cpu_isset(i, cpu_callout_map)) {
294 do_div(avg, num_booting_cpus());
297 for (i = 0; i < NR_CPUS; i++) {
298 if (!cpu_isset(i, cpu_callout_map))
300 delta = tsc_values[i] - avg;
304 * We report bigger than 2 microseconds clock differences.
306 if (delta > 2*one_usec) {
313 do_div(realdelta, one_usec);
314 if (tsc_values[i] < avg)
315 realdelta = -realdelta;
317 printk(KERN_INFO "CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta);
326 static void __init synchronize_tsc_ap (void)
331 * Not every cpu is online at the time
332 * this gets called, so we first wait for the BP to
333 * finish SMP initialization:
335 while (!atomic_read(&tsc_start_flag)) mb();
337 for (i = 0; i < NR_LOOPS; i++) {
338 atomic_inc(&tsc_count_start);
339 while (atomic_read(&tsc_count_start) != num_booting_cpus())
342 rdtscll(tsc_values[smp_processor_id()]);
346 atomic_inc(&tsc_count_stop);
347 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
352 extern void calibrate_delay(void);
354 static atomic_t init_deasserted;
356 static void __devinit smp_callin(void)
359 unsigned long timeout;
362 * If waken up by an INIT in an 82489DX configuration
363 * we may get here before an INIT-deassert IPI reaches
364 * our local APIC. We have to wait for the IPI or we'll
365 * lock up on an APIC access.
367 wait_for_init_deassert(&init_deasserted);
370 * (This works even if the APIC is not enabled.)
372 phys_id = GET_APIC_ID(apic_read(APIC_ID));
373 cpuid = smp_processor_id();
374 if (cpu_isset(cpuid, cpu_callin_map)) {
375 printk("huh, phys CPU#%d, CPU#%d already present??\n",
379 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
382 * STARTUP IPIs are fragile beasts as they might sometimes
383 * trigger some glue motherboard logic. Complete APIC bus
384 * silence for 1 second, this overestimates the time the
385 * boot CPU is spending to send the up to 2 STARTUP IPIs
386 * by a factor of two. This should be enough.
390 * Waiting 2s total for startup (udelay is not yet working)
392 timeout = jiffies + 2*HZ;
393 while (time_before(jiffies, timeout)) {
395 * Has the boot CPU finished it's STARTUP sequence?
397 if (cpu_isset(cpuid, cpu_callout_map))
402 if (!time_before(jiffies, timeout)) {
403 printk("BUG: CPU%d started up but did not get a callout!\n",
409 * the boot CPU has finished the init stage and is spinning
410 * on callin_map until we finish. We are free to set up this
411 * CPU, first the APIC. (this is probably redundant on most
415 Dprintk("CALLIN, before setup_local_APIC().\n");
416 smp_callin_clear_local_apic();
418 map_cpu_to_logical_apicid();
424 Dprintk("Stack at about %p\n",&cpuid);
427 * Save our processor parameters
429 smp_store_cpu_info(cpuid);
431 disable_APIC_timer();
434 * Allow the master to continue.
436 cpu_set(cpuid, cpu_callin_map);
439 * Synchronize the TSC with the BP
441 if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled)
442 synchronize_tsc_ap();
448 set_cpu_sibling_map(int cpu)
452 if (smp_num_siblings > 1) {
453 for (i = 0; i < NR_CPUS; i++) {
454 if (!cpu_isset(i, cpu_callout_map))
456 if (cpu_core_id[cpu] == cpu_core_id[i]) {
457 cpu_set(i, cpu_sibling_map[cpu]);
458 cpu_set(cpu, cpu_sibling_map[i]);
462 cpu_set(cpu, cpu_sibling_map[cpu]);
465 if (current_cpu_data.x86_num_cores > 1) {
466 for (i = 0; i < NR_CPUS; i++) {
467 if (!cpu_isset(i, cpu_callout_map))
469 if (phys_proc_id[cpu] == phys_proc_id[i]) {
470 cpu_set(i, cpu_core_map[cpu]);
471 cpu_set(cpu, cpu_core_map[i]);
475 cpu_core_map[cpu] = cpu_sibling_map[cpu];
480 * Activate a secondary processor.
482 static void __devinit start_secondary(void *unused)
485 * Dont put anything before smp_callin(), SMP
486 * booting is too fragile that we want to limit the
487 * things done here to the most necessary things.
491 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
493 setup_secondary_APIC_clock();
494 if (nmi_watchdog == NMI_IO_APIC) {
495 disable_8259A_irq(0);
496 enable_NMI_through_LVT0(NULL);
501 * low-memory mappings have been cleared, flush them from
502 * the local TLBs too.
506 /* This must be done before setting cpu_online_map */
507 set_cpu_sibling_map(raw_smp_processor_id());
511 * We need to hold call_lock, so there is no inconsistency
512 * between the time smp_call_function() determines number of
513 * IPI receipients, and the time when the determination is made
514 * for which cpus receive the IPI. Holding this
515 * lock helps us to not include this cpu in a currently in progress
516 * smp_call_function().
518 lock_ipi_call_lock();
519 cpu_set(smp_processor_id(), cpu_online_map);
520 unlock_ipi_call_lock();
521 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
523 /* We can take interrupts now: we're officially "up". */
531 * Everything has been set up for the secondary
532 * CPUs - they just need to reload everything
533 * from the task structure
534 * This function must not return.
536 void __devinit initialize_secondary(void)
539 * We don't actually need to load the full TSS,
540 * basically just the stack pointer and the eip.
547 :"r" (current->thread.esp),"r" (current->thread.eip));
557 /* which logical CPUs are on which nodes */
558 cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly =
559 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
560 /* which node each logical CPU is on */
561 int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
562 EXPORT_SYMBOL(cpu_2_node);
564 /* set up a mapping between cpu and node. */
565 static inline void map_cpu_to_node(int cpu, int node)
567 printk("Mapping cpu %d to node %d\n", cpu, node);
568 cpu_set(cpu, node_2_cpu_mask[node]);
569 cpu_2_node[cpu] = node;
572 /* undo a mapping between cpu and node. */
573 static inline void unmap_cpu_to_node(int cpu)
577 printk("Unmapping cpu %d from all nodes\n", cpu);
578 for (node = 0; node < MAX_NUMNODES; node ++)
579 cpu_clear(cpu, node_2_cpu_mask[node]);
582 #else /* !CONFIG_NUMA */
584 #define map_cpu_to_node(cpu, node) ({})
585 #define unmap_cpu_to_node(cpu) ({})
587 #endif /* CONFIG_NUMA */
589 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
591 static void map_cpu_to_logical_apicid(void)
593 int cpu = smp_processor_id();
594 int apicid = logical_smp_processor_id();
596 cpu_2_logical_apicid[cpu] = apicid;
597 map_cpu_to_node(cpu, apicid_to_node(apicid));
600 static void unmap_cpu_to_logical_apicid(int cpu)
602 cpu_2_logical_apicid[cpu] = BAD_APICID;
603 unmap_cpu_to_node(cpu);
607 static inline void __inquire_remote_apic(int apicid)
609 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
610 char *names[] = { "ID", "VERSION", "SPIV" };
613 printk("Inquiring remote APIC #%d...\n", apicid);
615 for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
616 printk("... APIC #%d %s: ", apicid, names[i]);
621 apic_wait_icr_idle();
623 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
624 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
629 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
630 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
633 case APIC_ICR_RR_VALID:
634 status = apic_read(APIC_RRR);
635 printk("%08x\n", status);
644 #ifdef WAKE_SECONDARY_VIA_NMI
646 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
647 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
648 * won't ... remember to clear down the APIC, etc later.
651 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
653 unsigned long send_status = 0, accept_status = 0;
657 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
659 /* Boot on the stack */
660 /* Kick the second */
661 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
663 Dprintk("Waiting for send to finish...\n");
668 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
669 } while (send_status && (timeout++ < 1000));
672 * Give the other CPU some time to accept the IPI.
676 * Due to the Pentium erratum 3AP.
678 maxlvt = get_maxlvt();
680 apic_read_around(APIC_SPIV);
681 apic_write(APIC_ESR, 0);
683 accept_status = (apic_read(APIC_ESR) & 0xEF);
684 Dprintk("NMI sent.\n");
687 printk("APIC never delivered???\n");
689 printk("APIC delivery error (%lx).\n", accept_status);
691 return (send_status | accept_status);
693 #endif /* WAKE_SECONDARY_VIA_NMI */
695 #ifdef WAKE_SECONDARY_VIA_INIT
697 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
699 unsigned long send_status = 0, accept_status = 0;
700 int maxlvt, timeout, num_starts, j;
703 * Be paranoid about clearing APIC errors.
705 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
706 apic_read_around(APIC_SPIV);
707 apic_write(APIC_ESR, 0);
711 Dprintk("Asserting INIT.\n");
714 * Turn INIT on target chip
716 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
721 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
724 Dprintk("Waiting for send to finish...\n");
729 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
730 } while (send_status && (timeout++ < 1000));
734 Dprintk("Deasserting INIT.\n");
737 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
740 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
742 Dprintk("Waiting for send to finish...\n");
747 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
748 } while (send_status && (timeout++ < 1000));
750 atomic_set(&init_deasserted, 1);
753 * Should we send STARTUP IPIs ?
755 * Determine this based on the APIC version.
756 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
758 if (APIC_INTEGRATED(apic_version[phys_apicid]))
764 * Run STARTUP IPI loop.
766 Dprintk("#startup loops: %d.\n", num_starts);
768 maxlvt = get_maxlvt();
770 for (j = 1; j <= num_starts; j++) {
771 Dprintk("Sending STARTUP #%d.\n",j);
772 apic_read_around(APIC_SPIV);
773 apic_write(APIC_ESR, 0);
775 Dprintk("After apic_write.\n");
782 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
784 /* Boot on the stack */
785 /* Kick the second */
786 apic_write_around(APIC_ICR, APIC_DM_STARTUP
787 | (start_eip >> 12));
790 * Give the other CPU some time to accept the IPI.
794 Dprintk("Startup point 1.\n");
796 Dprintk("Waiting for send to finish...\n");
801 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
802 } while (send_status && (timeout++ < 1000));
805 * Give the other CPU some time to accept the IPI.
809 * Due to the Pentium erratum 3AP.
812 apic_read_around(APIC_SPIV);
813 apic_write(APIC_ESR, 0);
815 accept_status = (apic_read(APIC_ESR) & 0xEF);
816 if (send_status || accept_status)
819 Dprintk("After Startup.\n");
822 printk("APIC never delivered???\n");
824 printk("APIC delivery error (%lx).\n", accept_status);
826 return (send_status | accept_status);
828 #endif /* WAKE_SECONDARY_VIA_INIT */
830 extern cpumask_t cpu_initialized;
831 static inline int alloc_cpu_id(void)
835 cpus_complement(tmp_map, cpu_present_map);
836 cpu = first_cpu(tmp_map);
842 #ifdef CONFIG_HOTPLUG_CPU
843 static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS];
844 static inline struct task_struct * alloc_idle_task(int cpu)
846 struct task_struct *idle;
848 if ((idle = cpu_idle_tasks[cpu]) != NULL) {
849 /* initialize thread_struct. we really want to avoid destroy
852 idle->thread.esp = (unsigned long)(((struct pt_regs *)
853 (THREAD_SIZE + (unsigned long) idle->thread_info)) - 1);
854 init_idle(idle, cpu);
857 idle = fork_idle(cpu);
860 cpu_idle_tasks[cpu] = idle;
864 #define alloc_idle_task(cpu) fork_idle(cpu)
867 static int __devinit do_boot_cpu(int apicid, int cpu)
869 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
870 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
871 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
874 struct task_struct *idle;
875 unsigned long boot_error;
877 unsigned long start_eip;
878 unsigned short nmi_high = 0, nmi_low = 0;
883 * We can't use kernel_thread since we must avoid to
884 * reschedule the child.
886 idle = alloc_idle_task(cpu);
888 panic("failed fork for CPU %d", cpu);
889 idle->thread.eip = (unsigned long) start_secondary;
890 /* start_eip had better be page-aligned! */
891 start_eip = setup_trampoline();
893 /* So we see what's up */
894 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
895 /* Stack for startup_32 can be just as for start_secondary onwards */
896 stack_start.esp = (void *) idle->thread.esp;
901 * This grunge runs the startup process for
902 * the targeted processor.
905 atomic_set(&init_deasserted, 0);
907 Dprintk("Setting warm reset code and vector.\n");
909 store_NMI_vector(&nmi_high, &nmi_low);
911 smpboot_setup_warm_reset_vector(start_eip);
914 * Starting actual IPI sequence...
916 boot_error = wakeup_secondary_cpu(apicid, start_eip);
920 * allow APs to start initializing.
922 Dprintk("Before Callout %d.\n", cpu);
923 cpu_set(cpu, cpu_callout_map);
924 Dprintk("After Callout %d.\n", cpu);
927 * Wait 5s total for a response
929 for (timeout = 0; timeout < 50000; timeout++) {
930 if (cpu_isset(cpu, cpu_callin_map))
931 break; /* It has booted */
935 if (cpu_isset(cpu, cpu_callin_map)) {
936 /* number CPUs logically, starting from 1 (BSP is 0) */
938 printk("CPU%d: ", cpu);
939 print_cpu_info(&cpu_data[cpu]);
940 Dprintk("CPU has booted.\n");
943 if (*((volatile unsigned char *)trampoline_base)
945 /* trampoline started but...? */
946 printk("Stuck ??\n");
948 /* trampoline code not run */
949 printk("Not responding.\n");
950 inquire_remote_apic(apicid);
955 /* Try to put things back the way they were before ... */
956 unmap_cpu_to_logical_apicid(cpu);
957 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
958 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
961 x86_cpu_to_apicid[cpu] = apicid;
962 cpu_set(cpu, cpu_present_map);
965 /* mark "stuck" area as not stuck */
966 *((volatile unsigned long *)trampoline_base) = 0;
971 #ifdef CONFIG_HOTPLUG_CPU
972 void cpu_exit_clear(void)
974 int cpu = raw_smp_processor_id();
982 cpu_clear(cpu, cpu_callout_map);
983 cpu_clear(cpu, cpu_callin_map);
984 cpu_clear(cpu, cpu_present_map);
986 cpu_clear(cpu, smp_commenced_mask);
987 unmap_cpu_to_logical_apicid(cpu);
990 struct warm_boot_cpu_info {
991 struct completion *complete;
996 static void __devinit do_warm_boot_cpu(void *p)
998 struct warm_boot_cpu_info *info = p;
999 do_boot_cpu(info->apicid, info->cpu);
1000 complete(info->complete);
1003 int __devinit smp_prepare_cpu(int cpu)
1005 DECLARE_COMPLETION(done);
1006 struct warm_boot_cpu_info info;
1007 struct work_struct task;
1011 apicid = x86_cpu_to_apicid[cpu];
1012 if (apicid == BAD_APICID) {
1017 info.complete = &done;
1018 info.apicid = apicid;
1020 INIT_WORK(&task, do_warm_boot_cpu, &info);
1022 tsc_sync_disabled = 1;
1024 /* init low mem mapping */
1025 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
1028 schedule_work(&task);
1029 wait_for_completion(&done);
1031 tsc_sync_disabled = 0;
1035 unlock_cpu_hotplug();
1040 static void smp_tune_scheduling (void)
1042 unsigned long cachesize; /* kB */
1043 unsigned long bandwidth = 350; /* MB/s */
1045 * Rough estimation for SMP scheduling, this is the number of
1046 * cycles it takes for a fully memory-limited process to flush
1047 * the SMP-local cache.
1049 * (For a P5 this pretty much means we will choose another idle
1050 * CPU almost always at wakeup time (this is due to the small
1051 * L1 cache), on PIIs it's around 50-100 usecs, depending on
1057 * this basically disables processor-affinity
1058 * scheduling on SMP without a TSC.
1062 cachesize = boot_cpu_data.x86_cache_size;
1063 if (cachesize == -1) {
1064 cachesize = 16; /* Pentiums, 2x8kB cache */
1071 * Cycle through the processors sending APIC IPIs to boot each.
1074 static int boot_cpu_logical_apicid;
1075 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1077 #ifdef CONFIG_X86_NUMAQ
1078 EXPORT_SYMBOL(xquad_portio);
1082 * Fall back to non SMP mode after errors.
1085 static __init void disable_smp(void)
1087 cpu_set(0, cpu_sibling_map[0]);
1088 cpu_set(0, cpu_core_map[0]);
1091 static void __init smp_boot_cpus(unsigned int max_cpus)
1093 int apicid, cpu, bit, kicked;
1094 unsigned long bogosum = 0;
1097 * Setup boot CPU information
1099 smp_store_cpu_info(0); /* Final full version of the data */
1100 printk("CPU%d: ", 0);
1101 print_cpu_info(&cpu_data[0]);
1103 boot_cpu_logical_apicid = logical_smp_processor_id();
1104 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1106 current_thread_info()->cpu = 0;
1107 smp_tune_scheduling();
1108 cpus_clear(cpu_sibling_map[0]);
1109 cpu_set(0, cpu_sibling_map[0]);
1111 cpus_clear(cpu_core_map[0]);
1112 cpu_set(0, cpu_core_map[0]);
1114 map_cpu_to_logical_apicid();
1117 * If we couldn't find an SMP configuration at boot time,
1118 * get out of here now!
1120 if (!smp_found_config && !acpi_lapic) {
1121 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1127 * If SMP should be disabled, then really disable it!
1129 if (!max_cpus || (enable_local_apic < 0)) {
1130 printk(KERN_INFO "SMP mode deactivated.\n");
1135 setup_portio_remap();
1138 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1140 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1141 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1142 * clustered apic ID.
1144 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1147 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
1148 apicid = cpu_present_to_apicid(bit);
1150 * Don't even attempt to start the boot CPU!
1152 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
1155 if (!check_apicid_present(bit))
1157 if (max_cpus <= cpucount+1)
1160 if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
1161 printk("CPU #%d not responding - cannot use it.\n",
1168 * Cleanup possible dangling ends...
1170 smpboot_restore_warm_reset_vector();
1173 * Allow the user to impress friends.
1175 Dprintk("Before bogomips.\n");
1176 for (cpu = 0; cpu < NR_CPUS; cpu++)
1177 if (cpu_isset(cpu, cpu_callout_map))
1178 bogosum += cpu_data[cpu].loops_per_jiffy;
1180 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1182 bogosum/(500000/HZ),
1183 (bogosum/(5000/HZ))%100);
1185 Dprintk("Before bogocount - setting activated=1.\n");
1188 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1191 * Don't taint if we are running SMP kernel on a single non-MP
1194 if (tainted & TAINT_UNSAFE_SMP) {
1196 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1198 tainted &= ~TAINT_UNSAFE_SMP;
1201 Dprintk("Boot done.\n");
1204 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1207 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1208 cpus_clear(cpu_sibling_map[cpu]);
1209 cpus_clear(cpu_core_map[cpu]);
1212 cpu_set(0, cpu_sibling_map[0]);
1213 cpu_set(0, cpu_core_map[0]);
1216 * Synchronize the TSC with the AP
1218 if (cpu_has_tsc && cpucount && cpu_khz)
1219 synchronize_tsc_bp();
1222 /* These are wrappers to interface to the new boot process. Someone
1223 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1224 void __init smp_prepare_cpus(unsigned int max_cpus)
1226 smp_commenced_mask = cpumask_of_cpu(0);
1227 cpu_callin_map = cpumask_of_cpu(0);
1229 smp_boot_cpus(max_cpus);
1232 void __devinit smp_prepare_boot_cpu(void)
1234 cpu_set(smp_processor_id(), cpu_online_map);
1235 cpu_set(smp_processor_id(), cpu_callout_map);
1236 cpu_set(smp_processor_id(), cpu_present_map);
1237 cpu_set(smp_processor_id(), cpu_possible_map);
1238 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
1241 #ifdef CONFIG_HOTPLUG_CPU
1243 remove_siblinginfo(int cpu)
1247 for_each_cpu_mask(sibling, cpu_sibling_map[cpu])
1248 cpu_clear(cpu, cpu_sibling_map[sibling]);
1249 for_each_cpu_mask(sibling, cpu_core_map[cpu])
1250 cpu_clear(cpu, cpu_core_map[sibling]);
1251 cpus_clear(cpu_sibling_map[cpu]);
1252 cpus_clear(cpu_core_map[cpu]);
1253 phys_proc_id[cpu] = BAD_APICID;
1254 cpu_core_id[cpu] = BAD_APICID;
1257 int __cpu_disable(void)
1259 cpumask_t map = cpu_online_map;
1260 int cpu = smp_processor_id();
1263 * Perhaps use cpufreq to drop frequency, but that could go
1264 * into generic code.
1266 * We won't take down the boot processor on i386 due to some
1267 * interrupts only being able to be serviced by the BSP.
1268 * Especially so if we're not using an IOAPIC -zwane
1273 /* We enable the timer again on the exit path of the death loop */
1274 disable_APIC_timer();
1275 /* Allow any queued timer interrupts to get serviced */
1278 local_irq_disable();
1280 remove_siblinginfo(cpu);
1282 cpu_clear(cpu, map);
1284 /* It's now safe to remove this processor from the online map */
1285 cpu_clear(cpu, cpu_online_map);
1289 void __cpu_die(unsigned int cpu)
1291 /* We don't do anything here: idle task is faking death itself. */
1294 for (i = 0; i < 10; i++) {
1295 /* They ack this in play_dead by setting CPU_DEAD */
1296 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1297 printk ("CPU %d is now offline\n", cpu);
1302 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1304 #else /* ... !CONFIG_HOTPLUG_CPU */
1305 int __cpu_disable(void)
1310 void __cpu_die(unsigned int cpu)
1312 /* We said "no" in __cpu_disable */
1315 #endif /* CONFIG_HOTPLUG_CPU */
1317 int __devinit __cpu_up(unsigned int cpu)
1319 /* In case one didn't come up */
1320 if (!cpu_isset(cpu, cpu_callin_map)) {
1321 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1327 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1328 /* Unleash the CPU! */
1329 cpu_set(cpu, smp_commenced_mask);
1330 while (!cpu_isset(cpu, cpu_online_map))
1335 void __init smp_cpus_done(unsigned int max_cpus)
1337 #ifdef CONFIG_X86_IO_APIC
1338 setup_ioapic_dest();
1341 #ifndef CONFIG_HOTPLUG_CPU
1343 * Disable executability of the SMP trampoline:
1345 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1349 void __init smp_intr_init(void)
1352 * IRQ0 must be given a fixed assignment and initialized,
1353 * because it's used before the IO-APIC is set up.
1355 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1358 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1359 * IPI, driven by wakeup.
1361 set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1363 /* IPI for invalidation */
1364 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1366 /* IPI for generic function call */
1367 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);