2 * SMP boot-related support
4 * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Copyright (C) 2001, 2004-2005 Intel Corp
7 * Rohit Seth <rohit.seth@intel.com>
8 * Suresh Siddha <suresh.b.siddha@intel.com>
9 * Gordon Jin <gordon.jin@intel.com>
10 * Ashok Raj <ashok.raj@intel.com>
12 * 01/05/16 Rohit Seth <rohit.seth@intel.com> Moved SMP booting functions from smp.c to here.
13 * 01/04/27 David Mosberger <davidm@hpl.hp.com> Added ITC synching code.
14 * 02/07/31 David Mosberger <davidm@hpl.hp.com> Switch over to hotplug-CPU boot-sequence.
15 * smp_boot_cpus()/smp_commence() is replaced by
16 * smp_prepare_cpus()/__cpu_up()/smp_cpus_done().
17 * 04/06/21 Ashok Raj <ashok.raj@intel.com> Added CPU Hotplug Support
18 * 04/12/26 Jin Gordon <gordon.jin@intel.com>
19 * 04/12/26 Rohit Seth <rohit.seth@intel.com>
20 * Add multi-threading and multi-core detection
21 * 05/01/30 Suresh Siddha <suresh.b.siddha@intel.com>
22 * Setup cpu_sibling_map and cpu_core_map
25 #include <linux/module.h>
26 #include <linux/acpi.h>
27 #include <linux/bootmem.h>
28 #include <linux/cpu.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/kernel.h>
34 #include <linux/kernel_stat.h>
36 #include <linux/notifier.h>
37 #include <linux/smp.h>
38 #include <linux/spinlock.h>
39 #include <linux/efi.h>
40 #include <linux/percpu.h>
41 #include <linux/bitops.h>
43 #include <linux/atomic.h>
44 #include <asm/cache.h>
45 #include <asm/current.h>
46 #include <asm/delay.h>
49 #include <asm/machvec.h>
52 #include <asm/paravirt.h>
53 #include <asm/pgalloc.h>
54 #include <asm/pgtable.h>
55 #include <asm/processor.h>
56 #include <asm/ptrace.h>
58 #include <asm/tlbflush.h>
59 #include <asm/unistd.h>
60 #include <asm/sn/arch.h>
65 #define Dprintk(x...) printk(x)
70 #ifdef CONFIG_HOTPLUG_CPU
71 #ifdef CONFIG_PERMIT_BSP_REMOVE
72 #define bsp_remove_ok 1
74 #define bsp_remove_ok 0
78 * Global array allocated for NR_CPUS at boot time
80 struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
83 * start_ap in head.S uses this to store current booting cpu
86 struct sal_to_os_boot *sal_state_for_booting_cpu = &sal_boot_rendez_state[0];
88 #define set_brendez_area(x) (sal_state_for_booting_cpu = &sal_boot_rendez_state[(x)]);
91 #define set_brendez_area(x)
96 * ITC synchronization related stuff:
99 #define SLAVE (SMP_CACHE_BYTES/8)
101 #define NUM_ROUNDS 64 /* magic value */
102 #define NUM_ITERS 5 /* likewise */
104 static DEFINE_SPINLOCK(itc_sync_lock);
105 static volatile unsigned long go[SLAVE + 1];
107 #define DEBUG_ITC_SYNC 0
109 extern void start_ap (void);
110 extern unsigned long ia64_iobase;
112 struct task_struct *task_for_booting_cpu;
117 DEFINE_PER_CPU(int, cpu_state);
119 cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
120 EXPORT_SYMBOL(cpu_core_map);
121 DEFINE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map);
122 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
124 int smp_num_siblings = 1;
126 /* which logical CPU number maps to which CPU (physical APIC ID) */
127 volatile int ia64_cpu_to_sapicid[NR_CPUS];
128 EXPORT_SYMBOL(ia64_cpu_to_sapicid);
130 static volatile cpumask_t cpu_callin_map;
132 struct smp_boot_data smp_boot_data __initdata;
134 unsigned long ap_wakeup_vector = -1; /* External Int use to wakeup APs */
136 char __initdata no_int_routing;
138 unsigned char smp_int_redirect; /* are INT and IPI redirectable by the chipset? */
140 #ifdef CONFIG_FORCE_CPEI_RETARGET
141 #define CPEI_OVERRIDE_DEFAULT (1)
143 #define CPEI_OVERRIDE_DEFAULT (0)
146 unsigned int force_cpei_retarget = CPEI_OVERRIDE_DEFAULT;
149 cmdl_force_cpei(char *str)
153 get_option (&str, &value);
154 force_cpei_retarget = value;
159 __setup("force_cpei=", cmdl_force_cpei);
162 nointroute (char *str)
165 printk ("no_int_routing on\n");
169 __setup("nointroute", nointroute);
171 static void fix_b0_for_bsp(void)
173 #ifdef CONFIG_HOTPLUG_CPU
175 static int fix_bsp_b0 = 1;
177 cpuid = smp_processor_id();
180 * Cache the b0 value on the first AP that comes up
182 if (!(fix_bsp_b0 && cpuid))
185 sal_boot_rendez_state[0].br[0] = sal_boot_rendez_state[cpuid].br[0];
186 printk ("Fixed BSP b0 value from CPU %d\n", cpuid);
193 sync_master (void *arg)
195 unsigned long flags, i;
199 local_irq_save(flags);
201 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) {
205 go[SLAVE] = ia64_get_itc();
208 local_irq_restore(flags);
212 * Return the number of cycles by which our itc differs from the itc on the master
213 * (time-keeper) CPU. A positive number indicates our itc is ahead of the master,
214 * negative that it is behind.
217 get_delta (long *rt, long *master)
219 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
220 unsigned long tcenter, t0, t1, tm;
223 for (i = 0; i < NUM_ITERS; ++i) {
226 while (!(tm = go[SLAVE]))
231 if (t1 - t0 < best_t1 - best_t0)
232 best_t0 = t0, best_t1 = t1, best_tm = tm;
235 *rt = best_t1 - best_t0;
236 *master = best_tm - best_t0;
238 /* average best_t0 and best_t1 without overflow: */
239 tcenter = (best_t0/2 + best_t1/2);
240 if (best_t0 % 2 + best_t1 % 2 == 2)
242 return tcenter - best_tm;
246 * Synchronize ar.itc of the current (slave) CPU with the ar.itc of the MASTER CPU
247 * (normally the time-keeper CPU). We use a closed loop to eliminate the possibility of
248 * unaccounted-for errors (such as getting a machine check in the middle of a calibration
249 * step). The basic idea is for the slave to ask the master what itc value it has and to
250 * read its own itc before and after the master responds. Each iteration gives us three
264 * The goal is to adjust the slave's ar.itc such that tm falls exactly half-way between t0
265 * and t1. If we achieve this, the clocks are synchronized provided the interconnect
266 * between the slave and the master is symmetric. Even if the interconnect were
267 * asymmetric, we would still know that the synchronization error is smaller than the
268 * roundtrip latency (t0 - t1).
270 * When the interconnect is quiet and symmetric, this lets us synchronize the itc to
271 * within one or two cycles. However, we can only *guarantee* that the synchronization is
272 * accurate to within a round-trip time, which is typically in the range of several
273 * hundred cycles (e.g., ~500 cycles). In practice, this means that the itc's are usually
274 * almost perfectly synchronized, but we shouldn't assume that the accuracy is much better
275 * than half a micro second or so.
278 ia64_sync_itc (unsigned int master)
280 long i, delta, adj, adjust_latency = 0, done = 0;
281 unsigned long flags, rt, master_time_stamp, bound;
284 long rt; /* roundtrip time */
285 long master; /* master's timestamp */
286 long diff; /* difference between midpoint and master's timestamp */
287 long lat; /* estimate of itc adjustment latency */
292 * Make sure local timer ticks are disabled while we sync. If
293 * they were enabled, we'd have to worry about nasty issues
294 * like setting the ITC ahead of (or a long time before) the
295 * next scheduled tick.
297 BUG_ON((ia64_get_itv() & (1 << 16)) == 0);
301 if (smp_call_function_single(master, sync_master, NULL, 0) < 0) {
302 printk(KERN_ERR "sync_itc: failed to get attention of CPU %u!\n", master);
307 cpu_relax(); /* wait for master to be ready */
309 spin_lock_irqsave(&itc_sync_lock, flags);
311 for (i = 0; i < NUM_ROUNDS; ++i) {
312 delta = get_delta(&rt, &master_time_stamp);
314 done = 1; /* let's lock on to this... */
320 adjust_latency += -delta;
321 adj = -delta + adjust_latency/4;
325 ia64_set_itc(ia64_get_itc() + adj);
329 t[i].master = master_time_stamp;
331 t[i].lat = adjust_latency/4;
335 spin_unlock_irqrestore(&itc_sync_lock, flags);
338 for (i = 0; i < NUM_ROUNDS; ++i)
339 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
340 t[i].rt, t[i].master, t[i].diff, t[i].lat);
343 printk(KERN_INFO "CPU %d: synchronized ITC with CPU %u (last diff %ld cycles, "
344 "maxerr %lu cycles)\n", smp_processor_id(), master, delta, rt);
348 * Ideally sets up per-cpu profiling hooks. Doesn't do much now...
350 static inline void __devinit
351 smp_setup_percpu_timer (void)
355 static void __cpuinit
358 int cpuid, phys_id, itc_master;
359 struct cpuinfo_ia64 *last_cpuinfo, *this_cpuinfo;
360 extern void ia64_init_itm(void);
361 extern volatile int time_keeper_id;
363 #ifdef CONFIG_PERFMON
364 extern void pfm_init_percpu(void);
367 cpuid = smp_processor_id();
368 phys_id = hard_smp_processor_id();
369 itc_master = time_keeper_id;
371 if (cpu_online(cpuid)) {
372 printk(KERN_ERR "huh, phys CPU#0x%x, CPU#0x%x already present??\n",
380 * numa_node_id() works after this.
382 set_numa_node(cpu_to_node_map[cpuid]);
383 set_numa_mem(local_memory_node(cpu_to_node_map[cpuid]));
385 spin_lock(&vector_lock);
386 /* Setup the per cpu irq handling data structures */
387 __setup_vector_irq(cpuid);
388 notify_cpu_starting(cpuid);
389 set_cpu_online(cpuid, true);
390 per_cpu(cpu_state, cpuid) = CPU_ONLINE;
391 spin_unlock(&vector_lock);
393 smp_setup_percpu_timer();
395 ia64_mca_cmc_vector_setup(); /* Setup vector on AP */
397 #ifdef CONFIG_PERFMON
403 if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) {
405 * Synchronize the ITC with the BP. Need to do this after irqs are
406 * enabled because ia64_sync_itc() calls smp_call_function_single(), which
407 * calls spin_unlock_bh(), which calls spin_unlock_bh(), which calls
408 * local_bh_enable(), which bugs out if irqs are not enabled...
410 Dprintk("Going to syncup ITC with ITC Master.\n");
411 ia64_sync_itc(itc_master);
420 * Delay calibration can be skipped if new processor is identical to the
421 * previous processor.
423 last_cpuinfo = cpu_data(cpuid - 1);
424 this_cpuinfo = local_cpu_data;
425 if (last_cpuinfo->itc_freq != this_cpuinfo->itc_freq ||
426 last_cpuinfo->proc_freq != this_cpuinfo->proc_freq ||
427 last_cpuinfo->features != this_cpuinfo->features ||
428 last_cpuinfo->revision != this_cpuinfo->revision ||
429 last_cpuinfo->family != this_cpuinfo->family ||
430 last_cpuinfo->archrev != this_cpuinfo->archrev ||
431 last_cpuinfo->model != this_cpuinfo->model)
433 local_cpu_data->loops_per_jiffy = loops_per_jiffy;
436 * Allow the master to continue.
438 cpu_set(cpuid, cpu_callin_map);
439 Dprintk("Stack on CPU %d at about %p\n",cpuid, &cpuid);
444 * Activate a secondary processor. head.S calls this.
447 start_secondary (void *unused)
449 /* Early console may use I/O ports */
450 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
451 #ifndef CONFIG_PRINTK_TIME
452 Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id());
464 do_boot_cpu (int sapicid, int cpu, struct task_struct *idle)
468 task_for_booting_cpu = idle;
469 Dprintk("Sending wakeup vector %lu to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid);
471 set_brendez_area(cpu);
472 platform_send_ipi(cpu, ap_wakeup_vector, IA64_IPI_DM_INT, 0);
475 * Wait 10s total for the AP to start
477 Dprintk("Waiting on callin_map ...");
478 for (timeout = 0; timeout < 100000; timeout++) {
479 if (cpu_isset(cpu, cpu_callin_map))
480 break; /* It has booted */
485 if (!cpu_isset(cpu, cpu_callin_map)) {
486 printk(KERN_ERR "Processor 0x%x/0x%x is stuck.\n", cpu, sapicid);
487 ia64_cpu_to_sapicid[cpu] = -1;
488 set_cpu_online(cpu, false); /* was set in smp_callin() */
498 get_option (&str, &ticks);
502 __setup("decay=", decay);
505 * Initialize the logical CPU number to SAPICID mapping
508 smp_build_cpu_map (void)
511 int boot_cpu_id = hard_smp_processor_id();
513 for (cpu = 0; cpu < NR_CPUS; cpu++) {
514 ia64_cpu_to_sapicid[cpu] = -1;
517 ia64_cpu_to_sapicid[0] = boot_cpu_id;
518 init_cpu_present(cpumask_of(0));
519 set_cpu_possible(0, true);
520 for (cpu = 1, i = 0; i < smp_boot_data.cpu_count; i++) {
521 sapicid = smp_boot_data.cpu_phys_id[i];
522 if (sapicid == boot_cpu_id)
524 set_cpu_present(cpu, true);
525 set_cpu_possible(cpu, true);
526 ia64_cpu_to_sapicid[cpu] = sapicid;
532 * Cycle through the APs sending Wakeup IPIs to boot each.
535 smp_prepare_cpus (unsigned int max_cpus)
537 int boot_cpu_id = hard_smp_processor_id();
540 * Initialize the per-CPU profiling counter/multiplier
543 smp_setup_percpu_timer();
545 cpu_set(0, cpu_callin_map);
547 local_cpu_data->loops_per_jiffy = loops_per_jiffy;
548 ia64_cpu_to_sapicid[0] = boot_cpu_id;
550 printk(KERN_INFO "Boot processor id 0x%x/0x%x\n", 0, boot_cpu_id);
552 current_thread_info()->cpu = 0;
555 * If SMP should be disabled, then really disable it!
558 printk(KERN_INFO "SMP mode deactivated.\n");
559 init_cpu_online(cpumask_of(0));
560 init_cpu_present(cpumask_of(0));
561 init_cpu_possible(cpumask_of(0));
566 void __devinit smp_prepare_boot_cpu(void)
568 set_cpu_online(smp_processor_id(), true);
569 cpu_set(smp_processor_id(), cpu_callin_map);
570 set_numa_node(cpu_to_node_map[smp_processor_id()]);
571 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
572 paravirt_post_smp_prepare_boot_cpu();
575 #ifdef CONFIG_HOTPLUG_CPU
577 clear_cpu_sibling_map(int cpu)
581 for_each_cpu_mask(i, per_cpu(cpu_sibling_map, cpu))
582 cpu_clear(cpu, per_cpu(cpu_sibling_map, i));
583 for_each_cpu_mask(i, cpu_core_map[cpu])
584 cpu_clear(cpu, cpu_core_map[i]);
586 per_cpu(cpu_sibling_map, cpu) = cpu_core_map[cpu] = CPU_MASK_NONE;
590 remove_siblinginfo(int cpu)
594 if (cpu_data(cpu)->threads_per_core == 1 &&
595 cpu_data(cpu)->cores_per_socket == 1) {
596 cpu_clear(cpu, cpu_core_map[cpu]);
597 cpu_clear(cpu, per_cpu(cpu_sibling_map, cpu));
601 last = (cpus_weight(cpu_core_map[cpu]) == 1 ? 1 : 0);
603 /* remove it from all sibling map's */
604 clear_cpu_sibling_map(cpu);
607 extern void fixup_irqs(void);
609 int migrate_platform_irqs(unsigned int cpu)
612 struct irq_data *data = NULL;
613 const struct cpumask *mask;
617 * dont permit CPEI target to removed.
619 if (cpe_vector > 0 && is_cpu_cpei_target(cpu)) {
620 printk ("CPU (%d) is CPEI Target\n", cpu);
621 if (can_cpei_retarget()) {
623 * Now re-target the CPEI to a different processor
625 new_cpei_cpu = cpumask_any(cpu_online_mask);
626 mask = cpumask_of(new_cpei_cpu);
627 set_cpei_target_cpu(new_cpei_cpu);
628 data = irq_get_irq_data(ia64_cpe_irq);
630 * Switch for now, immediately, we need to do fake intr
631 * as other interrupts, but need to study CPEI behaviour with
632 * polling before making changes.
634 if (data && data->chip) {
635 data->chip->irq_disable(data);
636 data->chip->irq_set_affinity(data, mask, false);
637 data->chip->irq_enable(data);
638 printk ("Re-targeting CPEI to cpu %d\n", new_cpei_cpu);
642 printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu);
649 /* must be called with cpucontrol mutex held */
650 int __cpu_disable(void)
652 int cpu = smp_processor_id();
655 * dont permit boot processor for now
657 if (cpu == 0 && !bsp_remove_ok) {
658 printk ("Your platform does not support removal of BSP\n");
662 if (ia64_platform_is("sn2")) {
663 if (!sn_cpu_disable_allowed(cpu))
667 set_cpu_online(cpu, false);
669 if (migrate_platform_irqs(cpu)) {
670 set_cpu_online(cpu, true);
674 remove_siblinginfo(cpu);
676 local_flush_tlb_all();
677 cpu_clear(cpu, cpu_callin_map);
681 void __cpu_die(unsigned int cpu)
685 for (i = 0; i < 100; i++) {
686 /* They ack this in play_dead by setting CPU_DEAD */
687 if (per_cpu(cpu_state, cpu) == CPU_DEAD)
689 printk ("CPU %d is now offline\n", cpu);
694 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
696 #endif /* CONFIG_HOTPLUG_CPU */
699 smp_cpus_done (unsigned int dummy)
702 unsigned long bogosum = 0;
705 * Allow the user to impress friends.
708 for_each_online_cpu(cpu) {
709 bogosum += cpu_data(cpu)->loops_per_jiffy;
712 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
713 (int)num_online_cpus(), bogosum/(500000/HZ), (bogosum/(5000/HZ))%100);
716 static inline void __devinit
717 set_cpu_sibling_map(int cpu)
721 for_each_online_cpu(i) {
722 if ((cpu_data(cpu)->socket_id == cpu_data(i)->socket_id)) {
723 cpu_set(i, cpu_core_map[cpu]);
724 cpu_set(cpu, cpu_core_map[i]);
725 if (cpu_data(cpu)->core_id == cpu_data(i)->core_id) {
726 cpu_set(i, per_cpu(cpu_sibling_map, cpu));
727 cpu_set(cpu, per_cpu(cpu_sibling_map, i));
734 __cpu_up(unsigned int cpu, struct task_struct *tidle)
739 sapicid = ia64_cpu_to_sapicid[cpu];
744 * Already booted cpu? not valid anymore since we dont
745 * do idle loop tightspin anymore.
747 if (cpu_isset(cpu, cpu_callin_map))
750 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
751 /* Processor goes to start_secondary(), sets online flag */
752 ret = do_boot_cpu(sapicid, cpu, tidle);
756 if (cpu_data(cpu)->threads_per_core == 1 &&
757 cpu_data(cpu)->cores_per_socket == 1) {
758 cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
759 cpu_set(cpu, cpu_core_map[cpu]);
763 set_cpu_sibling_map(cpu);
769 * Assume that CPUs have been discovered by some platform-dependent interface. For
770 * SoftSDV/Lion, that would be ACPI.
772 * Setup of the IPI irq handler is done in irq.c:init_IRQ_SMP().
775 init_smp_config(void)
783 /* Tell SAL where to drop the APs. */
784 ap_startup = (struct fptr *) start_ap;
785 sal_ret = ia64_sal_set_vectors(SAL_VECTOR_OS_BOOT_RENDEZ,
786 ia64_tpa(ap_startup->fp), ia64_tpa(ap_startup->gp), 0, 0, 0, 0);
788 printk(KERN_ERR "SMP: Can't set SAL AP Boot Rendezvous: %s\n",
789 ia64_sal_strerror(sal_ret));
793 * identify_siblings(cpu) gets called from identify_cpu. This populates the
794 * information related to logical execution units in per_cpu_data structure.
797 identify_siblings(struct cpuinfo_ia64 *c)
801 pal_logical_to_physical_t info;
803 status = ia64_pal_logical_to_phys(-1, &info);
804 if (status != PAL_STATUS_SUCCESS) {
805 if (status != PAL_STATUS_UNIMPLEMENTED) {
807 "ia64_pal_logical_to_phys failed with %ld\n",
812 info.overview_ppid = 0;
813 info.overview_cpp = 1;
814 info.overview_tpc = 1;
817 status = ia64_sal_physical_id_info(&pltid);
818 if (status != PAL_STATUS_SUCCESS) {
819 if (status != PAL_STATUS_UNIMPLEMENTED)
821 "ia64_sal_pltid failed with %ld\n",
826 c->socket_id = (pltid << 8) | info.overview_ppid;
828 if (info.overview_cpp == 1 && info.overview_tpc == 1)
831 c->cores_per_socket = info.overview_cpp;
832 c->threads_per_core = info.overview_tpc;
833 c->num_log = info.overview_num_log;
835 c->core_id = info.log1_cid;
836 c->thread_id = info.log1_tid;
840 * returns non zero, if multi-threading is enabled
841 * on at least one physical package. Due to hotplug cpu
842 * and (maxcpus=), all threads may not necessarily be enabled
843 * even though the processor supports multi-threading.
845 int is_multithreading_enabled(void)
849 for_each_present_cpu(i) {
850 for_each_present_cpu(j) {
853 if ((cpu_data(j)->socket_id == cpu_data(i)->socket_id)) {
854 if (cpu_data(j)->core_id == cpu_data(i)->core_id)
861 EXPORT_SYMBOL_GPL(is_multithreading_enabled);