2 * Platform dependent support for SGI SN
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (c) 2000-2008 Silicon Graphics, Inc. All Rights Reserved.
11 #include <linux/irq.h>
12 #include <linux/spinlock.h>
13 #include <linux/init.h>
14 #include <linux/rculist.h>
15 #include <linux/slab.h>
16 #include <asm/sn/addrs.h>
17 #include <asm/sn/arch.h>
18 #include <asm/sn/intr.h>
19 #include <asm/sn/pcibr_provider.h>
20 #include <asm/sn/pcibus_provider_defs.h>
21 #include <asm/sn/pcidev.h>
22 #include <asm/sn/shub_mmr.h>
23 #include <asm/sn/sn_sal.h>
24 #include <asm/sn/sn_feature_sets.h>
26 static void register_intr_pda(struct sn_irq_info *sn_irq_info);
27 static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
29 extern int sn_ioif_inited;
30 struct list_head **sn_irq_lh;
31 static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */
33 u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
34 struct sn_irq_info *sn_irq_info,
35 int req_irq, nasid_t req_nasid,
38 struct ia64_sal_retval ret_stuff;
42 SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
43 (u64) SAL_INTR_ALLOC, (u64) local_nasid,
44 (u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
45 (u64) req_nasid, (u64) req_slice);
47 return ret_stuff.status;
50 void sn_intr_free(nasid_t local_nasid, int local_widget,
51 struct sn_irq_info *sn_irq_info)
53 struct ia64_sal_retval ret_stuff;
57 SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
58 (u64) SAL_INTR_FREE, (u64) local_nasid,
59 (u64) local_widget, (u64) sn_irq_info->irq_irq,
60 (u64) sn_irq_info->irq_cookie, 0, 0);
63 u64 sn_intr_redirect(nasid_t local_nasid, int local_widget,
64 struct sn_irq_info *sn_irq_info,
65 nasid_t req_nasid, int req_slice)
67 struct ia64_sal_retval ret_stuff;
71 SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
72 (u64) SAL_INTR_REDIRECT, (u64) local_nasid,
73 (u64) local_widget, __pa(sn_irq_info),
74 (u64) req_nasid, (u64) req_slice, 0);
76 return ret_stuff.status;
79 static unsigned int sn_startup_irq(struct irq_data *data)
84 static void sn_shutdown_irq(struct irq_data *data)
88 extern void ia64_mca_register_cpev(int);
90 static void sn_disable_irq(struct irq_data *data)
92 if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR))
93 ia64_mca_register_cpev(0);
96 static void sn_enable_irq(struct irq_data *data)
98 if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR))
99 ia64_mca_register_cpev(data->irq);
102 static void sn_ack_irq(struct irq_data *data)
104 u64 event_occurred, mask;
105 unsigned int irq = data->irq & 0xff;
107 event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
108 mask = event_occurred & SH_ALL_INT_MASK;
109 HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
110 __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
112 move_native_irq(irq);
115 static void sn_irq_info_free(struct rcu_head *head);
117 struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
118 nasid_t nasid, int slice)
126 int local_widget, status;
128 struct sn_irq_info *new_irq_info;
129 struct sn_pcibus_provider *pci_provider;
131 bridge = (u64) sn_irq_info->irq_bridge;
133 return NULL; /* irq is not a device interrupt */
136 local_nasid = NASID_GET(bridge);
139 local_widget = TIO_SWIN_WIDGETNUM(bridge);
141 local_widget = SWIN_WIDGETNUM(bridge);
142 vector = sn_irq_info->irq_irq;
144 /* Make use of SAL_INTR_REDIRECT if PROM supports it */
145 status = sn_intr_redirect(local_nasid, local_widget, sn_irq_info, nasid, slice);
147 new_irq_info = sn_irq_info;
152 * PROM does not support SAL_INTR_REDIRECT, or it failed.
153 * Revert to old method.
155 new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
156 if (new_irq_info == NULL)
159 memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
161 /* Free the old PROM new_irq_info structure */
162 sn_intr_free(local_nasid, local_widget, new_irq_info);
163 unregister_intr_pda(new_irq_info);
165 /* allocate a new PROM new_irq_info struct */
166 status = sn_intr_alloc(local_nasid, local_widget,
167 new_irq_info, vector,
170 /* SAL call failed */
176 register_intr_pda(new_irq_info);
177 spin_lock(&sn_irq_info_lock);
178 list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
179 spin_unlock(&sn_irq_info_lock);
180 call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
184 /* Update kernels new_irq_info with new target info */
185 cpuid = nasid_slice_to_cpuid(new_irq_info->irq_nasid,
186 new_irq_info->irq_slice);
187 new_irq_info->irq_cpuid = cpuid;
189 pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
192 * If this represents a line interrupt, target it. If it's
193 * an msi (irq_int_bit < 0), it's already targeted.
195 if (new_irq_info->irq_int_bit >= 0 &&
196 pci_provider && pci_provider->target_interrupt)
197 (pci_provider->target_interrupt)(new_irq_info);
200 cpuphys = cpu_physical_id(cpuid);
201 set_irq_affinity_info((vector & 0xff), cpuphys, 0);
207 static int sn_set_affinity_irq(struct irq_data *data,
208 const struct cpumask *mask, bool force)
210 struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
211 unsigned int irq = data->irq;
215 nasid = cpuid_to_nasid(cpumask_first(mask));
216 slice = cpuid_to_slice(cpumask_first(mask));
218 list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
219 sn_irq_lh[irq], list)
220 (void)sn_retarget_vector(sn_irq_info, nasid, slice);
226 void sn_set_err_irq_affinity(unsigned int irq)
229 * On systems which support CPU disabling (SHub2), all error interrupts
230 * are targetted at the boot CPU.
232 if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT))
233 set_irq_affinity_info(irq, cpu_physical_id(0), 0);
236 void sn_set_err_irq_affinity(unsigned int irq) { }
240 sn_mask_irq(struct irq_data *data)
245 sn_unmask_irq(struct irq_data *data)
249 struct irq_chip irq_type_sn = {
251 .irq_startup = sn_startup_irq,
252 .irq_shutdown = sn_shutdown_irq,
253 .irq_enable = sn_enable_irq,
254 .irq_disable = sn_disable_irq,
255 .irq_ack = sn_ack_irq,
256 .irq_mask = sn_mask_irq,
257 .irq_unmask = sn_unmask_irq,
258 .irq_set_affinity = sn_set_affinity_irq
261 ia64_vector sn_irq_to_vector(int irq)
263 if (irq >= IA64_NUM_VECTORS)
265 return (ia64_vector)irq;
268 unsigned int sn_local_vector_to_irq(u8 vector)
270 return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
273 void sn_irq_init(void)
276 struct irq_desc *base_desc = irq_desc;
278 ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
279 ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
281 for (i = 0; i < NR_IRQS; i++) {
282 if (base_desc[i].chip == &no_irq_chip) {
283 base_desc[i].chip = &irq_type_sn;
288 static void register_intr_pda(struct sn_irq_info *sn_irq_info)
290 int irq = sn_irq_info->irq_irq;
291 int cpu = sn_irq_info->irq_cpuid;
293 if (pdacpu(cpu)->sn_last_irq < irq) {
294 pdacpu(cpu)->sn_last_irq = irq;
297 if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq)
298 pdacpu(cpu)->sn_first_irq = irq;
301 static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
303 int irq = sn_irq_info->irq_irq;
304 int cpu = sn_irq_info->irq_cpuid;
305 struct sn_irq_info *tmp_irq_info;
309 if (pdacpu(cpu)->sn_last_irq == irq) {
311 for (i = pdacpu(cpu)->sn_last_irq - 1;
312 i && !foundmatch; i--) {
313 list_for_each_entry_rcu(tmp_irq_info,
316 if (tmp_irq_info->irq_cpuid == cpu) {
322 pdacpu(cpu)->sn_last_irq = i;
325 if (pdacpu(cpu)->sn_first_irq == irq) {
327 for (i = pdacpu(cpu)->sn_first_irq + 1;
328 i < NR_IRQS && !foundmatch; i++) {
329 list_for_each_entry_rcu(tmp_irq_info,
332 if (tmp_irq_info->irq_cpuid == cpu) {
338 pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
343 static void sn_irq_info_free(struct rcu_head *head)
345 struct sn_irq_info *sn_irq_info;
347 sn_irq_info = container_of(head, struct sn_irq_info, rcu);
351 void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
353 nasid_t nasid = sn_irq_info->irq_nasid;
354 int slice = sn_irq_info->irq_slice;
355 int cpu = nasid_slice_to_cpuid(nasid, slice);
358 struct irq_desc *desc;
361 pci_dev_get(pci_dev);
362 sn_irq_info->irq_cpuid = cpu;
363 sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);
365 /* link it into the sn_irq[irq] list */
366 spin_lock(&sn_irq_info_lock);
367 list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
368 reserve_irq_vector(sn_irq_info->irq_irq);
369 spin_unlock(&sn_irq_info_lock);
371 register_intr_pda(sn_irq_info);
373 cpuphys = cpu_physical_id(cpu);
374 set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0);
375 desc = irq_to_desc(sn_irq_info->irq_irq);
377 * Affinity was set by the PROM, prevent it from
378 * being reset by the request_irq() path.
380 desc->status |= IRQ_AFFINITY_SET;
384 void sn_irq_unfixup(struct pci_dev *pci_dev)
386 struct sn_irq_info *sn_irq_info;
388 /* Only cleanup IRQ stuff if this device has a host bus context */
389 if (!SN_PCIDEV_BUSSOFT(pci_dev))
392 sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
395 if (!sn_irq_info->irq_irq) {
400 unregister_intr_pda(sn_irq_info);
401 spin_lock(&sn_irq_info_lock);
402 list_del_rcu(&sn_irq_info->list);
403 spin_unlock(&sn_irq_info_lock);
404 if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
405 free_irq_vector(sn_irq_info->irq_irq);
406 call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
407 pci_dev_put(pci_dev);
412 sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
414 struct sn_pcibus_provider *pci_provider;
416 pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
418 /* Don't force an interrupt if the irq has been disabled */
419 if (!(irq_desc[sn_irq_info->irq_irq].status & IRQ_DISABLED) &&
420 pci_provider && pci_provider->force_interrupt)
421 (*pci_provider->force_interrupt)(sn_irq_info);
425 * Check for lost interrupts. If the PIC int_status reg. says that
426 * an interrupt has been sent, but not handled, and the interrupt
427 * is not pending in either the cpu irr regs or in the soft irr regs,
428 * and the interrupt is not in service, then the interrupt may have
429 * been lost. Force an interrupt on that pin. It is possible that
430 * the interrupt is in flight, so we may generate a spurious interrupt,
431 * but we should never miss a real lost interrupt.
433 static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
436 struct pcidev_info *pcidev_info;
437 struct pcibus_info *pcibus_info;
440 * Bridge types attached to TIO (anything but PIC) do not need this WAR
441 * since they do not target Shub II interrupt registers. If that
442 * ever changes, this check needs to accomodate.
444 if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
447 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
452 (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
454 regval = pcireg_intr_status_get(pcibus_info);
456 if (!ia64_get_irr(irq_to_vector(irq))) {
457 if (!test_bit(irq, pda->sn_in_service_ivecs)) {
459 if (sn_irq_info->irq_int_bit & regval &
460 sn_irq_info->irq_last_intr) {
461 regval &= ~(sn_irq_info->irq_int_bit & regval);
462 sn_call_force_intr_provider(sn_irq_info);
466 sn_irq_info->irq_last_intr = regval;
469 void sn_lb_int_war_check(void)
471 struct sn_irq_info *sn_irq_info;
474 if (!sn_ioif_inited || pda->sn_first_irq == 0)
478 for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
479 list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
480 sn_check_intr(i, sn_irq_info);
486 void __init sn_irq_lh_init(void)
490 sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL);
492 panic("SN PCI INIT: Failed to allocate memory for PCI init\n");
494 for (i = 0; i < NR_IRQS; i++) {
495 sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
497 panic("SN PCI INIT: Failed IRQ memory allocation\n");
499 INIT_LIST_HEAD(sn_irq_lh[i]);