2 * linux/arch/m32r/platforms/opsput/setup.c
4 * Setup routines for Renesas OPSPUT Board
6 * Copyright (c) 2002-2005
7 * Hiroyuki Kondo, Hirokazu Takata,
8 * Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
10 * This file is subject to the terms and conditions of the GNU General
11 * Public License. See the file "COPYING" in the main directory of this
12 * archive for more details.
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
20 #include <asm/system.h>
25 * OPSP Interrupt Control Unit (Level 1)
27 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
29 icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
31 static void disable_opsput_irq(unsigned int irq)
33 unsigned long port, data;
36 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
40 static void enable_opsput_irq(unsigned int irq)
42 unsigned long port, data;
45 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
49 static void mask_opsput(struct irq_data *data)
51 disable_opsput_irq(data->irq);
54 static void unmask_opsput(struct irq_data *data)
56 enable_opsput_irq(data->irq);
59 static void shutdown_opsput(struct irq_data *data)
63 port = irq2port(data->irq);
64 outl(M32R_ICUCR_ILEVEL7, port);
67 static struct irq_chip opsput_irq_type =
70 .irq_shutdown = shutdown_opsput,
71 .irq_mask = mask_opsput,
72 .irq_unmask = unmask_opsput,
76 * Interrupt Control Unit of PLD on OPSPUT (Level 2)
78 #define irq2pldirq(x) ((x) - OPSPUT_PLD_IRQ_BASE)
79 #define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
80 (((x) - 1) * sizeof(unsigned short)))
83 unsigned short icucr; /* ICU Control Register */
86 static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];
88 static void disable_opsput_pld_irq(unsigned int irq)
90 unsigned long port, data;
93 pldirq = irq2pldirq(irq);
94 port = pldirq2port(pldirq);
95 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
99 static void enable_opsput_pld_irq(unsigned int irq)
101 unsigned long port, data;
104 pldirq = irq2pldirq(irq);
105 port = pldirq2port(pldirq);
106 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
110 static void mask_opsput_pld(struct irq_data *data)
112 disable_opsput_pld_irq(data->irq);
115 static void unmask_opsput_pld(struct irq_data *data)
117 enable_opsput_pld_irq(data->irq);
118 enable_opsput_irq(M32R_IRQ_INT1);
121 static void shutdown_opsput_pld(struct irq_data *data)
126 pldirq = irq2pldirq(data->irq);
127 port = pldirq2port(pldirq);
128 outw(PLD_ICUCR_ILEVEL7, port);
131 static struct irq_chip opsput_pld_irq_type =
133 .name = "OPSPUT-PLD-IRQ",
134 .irq_shutdown = shutdown_opsput_pld,
135 .irq_mask = mask_opsput_pld,
136 .irq_unmask = unmask_opsput_pld,
140 * Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
142 #define irq2lanpldirq(x) ((x) - OPSPUT_LAN_PLD_IRQ_BASE)
143 #define lanpldirq2port(x) (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
144 (((x) - 1) * sizeof(unsigned short)))
146 static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];
148 static void disable_opsput_lanpld_irq(unsigned int irq)
150 unsigned long port, data;
153 pldirq = irq2lanpldirq(irq);
154 port = lanpldirq2port(pldirq);
155 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
159 static void enable_opsput_lanpld_irq(unsigned int irq)
161 unsigned long port, data;
164 pldirq = irq2lanpldirq(irq);
165 port = lanpldirq2port(pldirq);
166 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
170 static void mask_opsput_lanpld(struct irq_data *data)
172 disable_opsput_lanpld_irq(data->irq);
175 static void unmask_opsput_lanpld(struct irq_data *data)
177 enable_opsput_lanpld_irq(data->irq);
178 enable_opsput_irq(M32R_IRQ_INT0);
181 static void shutdown_opsput_lanpld(struct irq_data *data)
186 pldirq = irq2lanpldirq(data->irq);
187 port = lanpldirq2port(pldirq);
188 outw(PLD_ICUCR_ILEVEL7, port);
191 static struct irq_chip opsput_lanpld_irq_type =
193 .name = "OPSPUT-PLD-LAN-IRQ",
194 .irq_shutdown = shutdown_opsput_lanpld,
195 .irq_mask = mask_opsput_lanpld,
196 .irq_unmask = unmask_opsput_lanpld,
200 * Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
202 #define irq2lcdpldirq(x) ((x) - OPSPUT_LCD_PLD_IRQ_BASE)
203 #define lcdpldirq2port(x) (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
204 (((x) - 1) * sizeof(unsigned short)))
206 static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];
208 static void disable_opsput_lcdpld_irq(unsigned int irq)
210 unsigned long port, data;
213 pldirq = irq2lcdpldirq(irq);
214 port = lcdpldirq2port(pldirq);
215 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
219 static void enable_opsput_lcdpld_irq(unsigned int irq)
221 unsigned long port, data;
224 pldirq = irq2lcdpldirq(irq);
225 port = lcdpldirq2port(pldirq);
226 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
230 static void mask_and_ack_opsput_lcdpld(unsigned int irq)
232 disable_opsput_lcdpld_irq(irq);
235 static void end_opsput_lcdpld_irq(unsigned int irq)
237 enable_opsput_lcdpld_irq(irq);
238 enable_opsput_irq(M32R_IRQ_INT2);
241 static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
243 enable_opsput_lcdpld_irq(irq);
247 static void shutdown_opsput_lcdpld_irq(unsigned int irq)
252 pldirq = irq2lcdpldirq(irq);
253 port = lcdpldirq2port(pldirq);
254 outw(PLD_ICUCR_ILEVEL7, port);
257 static struct irq_chip opsput_lcdpld_irq_type =
259 "OPSPUT-PLD-LCD-IRQ",
260 startup_opsput_lcdpld_irq,
261 shutdown_opsput_lcdpld_irq,
262 enable_opsput_lcdpld_irq,
263 disable_opsput_lcdpld_irq,
264 mask_and_ack_opsput_lcdpld,
265 end_opsput_lcdpld_irq
268 void __init init_IRQ(void)
270 #if defined(CONFIG_SMC91X)
271 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
272 set_irq_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type,
274 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
275 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
276 #endif /* CONFIG_SMC91X */
278 /* MFT2 : system timer */
279 set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type,
281 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
282 disable_opsput_irq(M32R_IRQ_MFT2);
285 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type,
287 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
288 disable_opsput_irq(M32R_IRQ_SIO0_R);
291 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type,
293 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
294 disable_opsput_irq(M32R_IRQ_SIO0_S);
297 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type,
299 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
300 disable_opsput_irq(M32R_IRQ_SIO1_R);
303 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type,
305 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
306 disable_opsput_irq(M32R_IRQ_SIO1_S);
309 set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type,
311 icu_data[M32R_IRQ_DMA1].icucr = 0;
312 disable_opsput_irq(M32R_IRQ_DMA1);
314 #ifdef CONFIG_SERIAL_M32R_PLDSIO
315 /* INT#1: SIO0 Receive on PLD */
316 set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type,
318 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
319 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
321 /* INT#1: SIO0 Send on PLD */
322 set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type,
324 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
325 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
326 #endif /* CONFIG_SERIAL_M32R_PLDSIO */
328 /* INT#1: CFC IREQ on PLD */
329 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type,
331 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
332 disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
334 /* INT#1: CFC Insert on PLD */
335 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type,
337 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
338 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
340 /* INT#1: CFC Eject on PLD */
341 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type,
343 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
344 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
347 * INT0# is used for LAN, DIO
350 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
351 enable_opsput_irq(M32R_IRQ_INT0);
354 * INT1# is used for UART, MMC, CF Controller in FPGA.
357 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
358 enable_opsput_irq(M32R_IRQ_INT1);
360 #if defined(CONFIG_USB)
361 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
363 set_irq_chip(OPSPUT_LCD_IRQ_USB_INT1, &opsput_lcdpld_irq_type);
364 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
365 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
368 * INT2# is used for BAT, USB, AUDIO
371 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
372 enable_opsput_irq(M32R_IRQ_INT2);
374 #if defined(CONFIG_VIDEO_M32R_AR)
376 * INT3# is used for AR
378 set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type,
380 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
381 disable_opsput_irq(M32R_IRQ_INT3);
382 #endif /* CONFIG_VIDEO_M32R_AR */
385 #if defined(CONFIG_SMC91X)
387 #define LAN_IOSTART 0x300
388 #define LAN_IOEND 0x320
389 static struct resource smc91x_resources[] = {
391 .start = (LAN_IOSTART),
393 .flags = IORESOURCE_MEM,
396 .start = OPSPUT_LAN_IRQ_LAN,
397 .end = OPSPUT_LAN_IRQ_LAN,
398 .flags = IORESOURCE_IRQ,
402 static struct platform_device smc91x_device = {
405 .num_resources = ARRAY_SIZE(smc91x_resources),
406 .resource = smc91x_resources,
410 #if defined(CONFIG_FB_S1D13XXX)
412 #include <video/s1d13xxxfb.h>
413 #include <asm/s1d13806.h>
415 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
416 .initregs = s1d13xxxfb_initregs,
417 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
418 .platform_init_video = NULL,
420 .platform_suspend_video = NULL,
421 .platform_resume_video = NULL,
425 static struct resource s1d13xxxfb_resources[] = {
427 .start = 0x10600000UL,
429 .flags = IORESOURCE_MEM,
432 .start = 0x10400000UL,
434 .flags = IORESOURCE_MEM,
438 static struct platform_device s1d13xxxfb_device = {
439 .name = S1D_DEVICENAME,
442 .platform_data = &s1d13xxxfb_data,
444 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
445 .resource = s1d13xxxfb_resources,
449 static int __init platform_init(void)
451 #if defined(CONFIG_SMC91X)
452 platform_device_register(&smc91x_device);
454 #if defined(CONFIG_FB_S1D13XXX)
455 platform_device_register(&s1d13xxxfb_device);
459 arch_initcall(platform_init);