1 #ifndef __ARCH_M68K_ATOMIC__
2 #define __ARCH_M68K_ATOMIC__
4 #include <linux/types.h>
5 #include <linux/irqflags.h>
6 #include <asm/cmpxchg.h>
9 * Atomic operations that C can't guarantee us. Useful for
10 * resource counting etc..
14 * We do not have SMP m68k systems, so we don't have to deal with that.
17 #define ATOMIC_INIT(i) { (i) }
19 #define atomic_read(v) (*(volatile int *)&(v)->counter)
20 #define atomic_set(v, i) (((v)->counter) = i)
23 * The ColdFire parts cannot do some immediate to memory operations,
24 * so for them we do not specify the "i" asm constraint.
26 #ifdef CONFIG_COLDFIRE
32 static inline void atomic_add(int i, atomic_t *v)
34 __asm__ __volatile__("addl %1,%0" : "+m" (*v) : ASM_DI (i));
37 static inline void atomic_sub(int i, atomic_t *v)
39 __asm__ __volatile__("subl %1,%0" : "+m" (*v) : ASM_DI (i));
42 static inline void atomic_inc(atomic_t *v)
44 __asm__ __volatile__("addql #1,%0" : "+m" (*v));
47 static inline void atomic_dec(atomic_t *v)
49 __asm__ __volatile__("subql #1,%0" : "+m" (*v));
52 static inline int atomic_dec_and_test(atomic_t *v)
55 __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
59 static inline int atomic_dec_and_test_lt(atomic_t *v)
69 static inline int atomic_inc_and_test(atomic_t *v)
72 __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
76 #ifdef CONFIG_RMW_INSNS
78 static inline int atomic_add_return(int i, atomic_t *v)
87 : "+m" (*v), "=&d" (t), "=&d" (tmp)
88 : "g" (i), "2" (atomic_read(v)));
92 static inline int atomic_sub_return(int i, atomic_t *v)
101 : "+m" (*v), "=&d" (t), "=&d" (tmp)
102 : "g" (i), "2" (atomic_read(v)));
106 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
107 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
109 #else /* !CONFIG_RMW_INSNS */
111 static inline int atomic_add_return(int i, atomic_t * v)
116 local_irq_save(flags);
120 local_irq_restore(flags);
125 static inline int atomic_sub_return(int i, atomic_t * v)
130 local_irq_save(flags);
134 local_irq_restore(flags);
139 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
144 local_irq_save(flags);
145 prev = atomic_read(v);
148 local_irq_restore(flags);
152 static inline int atomic_xchg(atomic_t *v, int new)
157 local_irq_save(flags);
158 prev = atomic_read(v);
160 local_irq_restore(flags);
164 #endif /* !CONFIG_RMW_INSNS */
166 #define atomic_dec_return(v) atomic_sub_return(1, (v))
167 #define atomic_inc_return(v) atomic_add_return(1, (v))
169 static inline int atomic_sub_and_test(int i, atomic_t *v)
172 __asm__ __volatile__("subl %2,%1; seq %0"
173 : "=d" (c), "+m" (*v)
178 static inline int atomic_add_negative(int i, atomic_t *v)
181 __asm__ __volatile__("addl %2,%1; smi %0"
182 : "=d" (c), "+m" (*v)
187 static inline void atomic_clear_mask(unsigned long mask, unsigned long *v)
189 __asm__ __volatile__("andl %1,%0" : "+m" (*v) : ASM_DI (~(mask)));
192 static inline void atomic_set_mask(unsigned long mask, unsigned long *v)
194 __asm__ __volatile__("orl %1,%0" : "+m" (*v) : ASM_DI (mask));
197 static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
202 if (unlikely(c == (u)))
204 old = atomic_cmpxchg((v), c, c + (a));
205 if (likely(old == c))
213 /* Atomic operations are already serializing */
214 #define smp_mb__before_atomic_dec() barrier()
215 #define smp_mb__after_atomic_dec() barrier()
216 #define smp_mb__before_atomic_inc() barrier()
217 #define smp_mb__after_atomic_inc() barrier()
219 #endif /* __ARCH_M68K_ATOMIC __ */