1 #ifndef __ARCH_M68K_ATOMIC__
2 #define __ARCH_M68K_ATOMIC__
4 #include <linux/types.h>
5 #include <asm/system.h>
8 * Atomic operations that C can't guarantee us. Useful for
9 * resource counting etc..
13 * We do not have SMP m68k systems, so we don't have to deal with that.
16 #define ATOMIC_INIT(i) { (i) }
18 #define atomic_read(v) (*(volatile int *)&(v)->counter)
19 #define atomic_set(v, i) (((v)->counter) = i)
22 * The ColdFire parts cannot do some immediate to memory operations,
23 * so for them we do not specify the "i" asm constraint.
25 #ifdef CONFIG_COLDFIRE
31 static inline void atomic_add(int i, atomic_t *v)
33 __asm__ __volatile__("addl %1,%0" : "+m" (*v) : ASM_DI (i));
36 static inline void atomic_sub(int i, atomic_t *v)
38 __asm__ __volatile__("subl %1,%0" : "+m" (*v) : ASM_DI (i));
41 static inline void atomic_inc(atomic_t *v)
43 __asm__ __volatile__("addql #1,%0" : "+m" (*v));
46 static inline void atomic_dec(atomic_t *v)
48 __asm__ __volatile__("subql #1,%0" : "+m" (*v));
51 static inline int atomic_dec_and_test(atomic_t *v)
54 __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
58 static inline int atomic_dec_and_test_lt(atomic_t *v)
68 static inline int atomic_inc_and_test(atomic_t *v)
71 __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
75 #ifdef CONFIG_RMW_INSNS
77 static inline int atomic_add_return(int i, atomic_t *v)
86 : "+m" (*v), "=&d" (t), "=&d" (tmp)
87 : "g" (i), "2" (atomic_read(v)));
91 static inline int atomic_sub_return(int i, atomic_t *v)
100 : "+m" (*v), "=&d" (t), "=&d" (tmp)
101 : "g" (i), "2" (atomic_read(v)));
105 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
106 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
108 #else /* !CONFIG_RMW_INSNS */
110 static inline int atomic_add_return(int i, atomic_t * v)
115 local_irq_save(flags);
119 local_irq_restore(flags);
124 static inline int atomic_sub_return(int i, atomic_t * v)
129 local_irq_save(flags);
133 local_irq_restore(flags);
138 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
143 local_irq_save(flags);
144 prev = atomic_read(v);
147 local_irq_restore(flags);
151 static inline int atomic_xchg(atomic_t *v, int new)
156 local_irq_save(flags);
157 prev = atomic_read(v);
159 local_irq_restore(flags);
163 #endif /* !CONFIG_RMW_INSNS */
165 #define atomic_dec_return(v) atomic_sub_return(1, (v))
166 #define atomic_inc_return(v) atomic_add_return(1, (v))
168 static inline int atomic_sub_and_test(int i, atomic_t *v)
171 __asm__ __volatile__("subl %2,%1; seq %0"
172 : "=d" (c), "+m" (*v)
177 static inline int atomic_add_negative(int i, atomic_t *v)
180 __asm__ __volatile__("addl %2,%1; smi %0"
181 : "=d" (c), "+m" (*v)
186 static inline void atomic_clear_mask(unsigned long mask, unsigned long *v)
188 __asm__ __volatile__("andl %1,%0" : "+m" (*v) : ASM_DI (~(mask)));
191 static inline void atomic_set_mask(unsigned long mask, unsigned long *v)
193 __asm__ __volatile__("orl %1,%0" : "+m" (*v) : ASM_DI (mask));
196 static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
201 if (unlikely(c == (u)))
203 old = atomic_cmpxchg((v), c, c + (a));
204 if (likely(old == c))
212 /* Atomic operations are already serializing */
213 #define smp_mb__before_atomic_dec() barrier()
214 #define smp_mb__after_atomic_dec() barrier()
215 #define smp_mb__before_atomic_inc() barrier()
216 #define smp_mb__after_atomic_inc() barrier()
218 #endif /* __ARCH_M68K_ATOMIC __ */