1 #ifndef __ARCH_M68K_ATOMIC__
2 #define __ARCH_M68K_ATOMIC__
4 #include <linux/types.h>
5 #include <linux/irqflags.h>
6 #include <asm/cmpxchg.h>
7 #include <asm/barrier.h>
10 * Atomic operations that C can't guarantee us. Useful for
11 * resource counting etc..
15 * We do not have SMP m68k systems, so we don't have to deal with that.
18 #define ATOMIC_INIT(i) { (i) }
20 #define atomic_read(v) READ_ONCE((v)->counter)
21 #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
24 * The ColdFire parts cannot do some immediate to memory operations,
25 * so for them we do not specify the "i" asm constraint.
27 #ifdef CONFIG_COLDFIRE
33 #define ATOMIC_OP(op, c_op, asm_op) \
34 static inline void atomic_##op(int i, atomic_t *v) \
36 __asm__ __volatile__(#asm_op "l %1,%0" : "+m" (*v) : ASM_DI (i));\
39 #ifdef CONFIG_RMW_INSNS
41 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
42 static inline int atomic_##op##_return(int i, atomic_t *v) \
46 __asm__ __volatile__( \
48 " " #asm_op "l %3,%1\n" \
51 : "+m" (*v), "=&d" (t), "=&d" (tmp) \
52 : "g" (i), "2" (atomic_read(v))); \
58 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
59 static inline int atomic_##op##_return(int i, atomic_t * v) \
61 unsigned long flags; \
64 local_irq_save(flags); \
65 t = (v->counter c_op i); \
66 local_irq_restore(flags); \
71 #endif /* CONFIG_RMW_INSNS */
73 #define ATOMIC_OPS(op, c_op, asm_op) \
74 ATOMIC_OP(op, c_op, asm_op) \
75 ATOMIC_OP_RETURN(op, c_op, asm_op)
77 ATOMIC_OPS(add, +=, add)
78 ATOMIC_OPS(sub, -=, sub)
80 ATOMIC_OP(and, &=, and)
82 ATOMIC_OP(xor, ^=, eor)
85 #undef ATOMIC_OP_RETURN
88 static inline void atomic_inc(atomic_t *v)
90 __asm__ __volatile__("addql #1,%0" : "+m" (*v));
93 static inline void atomic_dec(atomic_t *v)
95 __asm__ __volatile__("subql #1,%0" : "+m" (*v));
98 static inline int atomic_dec_and_test(atomic_t *v)
101 __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
105 static inline int atomic_dec_and_test_lt(atomic_t *v)
108 __asm__ __volatile__(
109 "subql #1,%1; slt %0"
110 : "=d" (c), "=m" (*v)
115 static inline int atomic_inc_and_test(atomic_t *v)
118 __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
122 #ifdef CONFIG_RMW_INSNS
124 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
125 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
127 #else /* !CONFIG_RMW_INSNS */
129 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
134 local_irq_save(flags);
135 prev = atomic_read(v);
138 local_irq_restore(flags);
142 static inline int atomic_xchg(atomic_t *v, int new)
147 local_irq_save(flags);
148 prev = atomic_read(v);
150 local_irq_restore(flags);
154 #endif /* !CONFIG_RMW_INSNS */
156 #define atomic_dec_return(v) atomic_sub_return(1, (v))
157 #define atomic_inc_return(v) atomic_add_return(1, (v))
159 static inline int atomic_sub_and_test(int i, atomic_t *v)
162 __asm__ __volatile__("subl %2,%1; seq %0"
163 : "=d" (c), "+m" (*v)
168 static inline int atomic_add_negative(int i, atomic_t *v)
171 __asm__ __volatile__("addl %2,%1; smi %0"
172 : "=d" (c), "+m" (*v)
177 static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
182 if (unlikely(c == (u)))
184 old = atomic_cmpxchg((v), c, c + (a));
185 if (likely(old == c))
192 #endif /* __ARCH_M68K_ATOMIC __ */