1 /****************************************************************************/
4 * m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
6 * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
9 /****************************************************************************/
12 /****************************************************************************/
14 #define CPU_NAME "COLDFIRE(m520x)"
15 #define CPU_INSTR_PER_JIFFY 3
16 #define MCF_BUSCLK (MCF_CLK / 2)
18 #include <asm/m52xxacr.h>
21 * Define the 520x SIM register set addresses.
23 #define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */
24 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
25 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
26 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
27 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
28 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
29 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
30 #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */
31 #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */
32 #define MCFINTC_ICR0 0x40 /* Base ICR register */
35 * The common interrupt controller code just wants to know the absolute
36 * address to the SIMR and CIMR registers (not offsets into IPSBAR).
37 * The 520x family only has a single INTC unit.
39 #define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR)
40 #define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR)
41 #define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0)
42 #define MCFINTC1_SIMR (0)
43 #define MCFINTC1_CIMR (0)
44 #define MCFINTC1_ICR0 (0)
46 #define MCFINT_VECBASE 64
47 #define MCFINT_UART0 26 /* Interrupt number for UART0 */
48 #define MCFINT_UART1 27 /* Interrupt number for UART1 */
49 #define MCFINT_UART2 28 /* Interrupt number for UART2 */
50 #define MCFINT_QSPI 31 /* Interrupt number for QSPI */
51 #define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */
52 #define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */
53 #define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */
54 #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
56 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
57 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
58 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
60 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
61 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
62 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
64 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
65 #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
68 * SDRAM configuration registers.
70 #define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
71 #define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
72 #define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
73 #define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
74 #define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
75 #define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
78 * EPORT and GPIO registers.
80 #define MCFEPORT_EPPAR 0xFC088000
81 #define MCFEPORT_EPDDR 0xFC088002
82 #define MCFEPORT_EPIER 0xFC088003
83 #define MCFEPORT_EPDR 0xFC088004
84 #define MCFEPORT_EPPDR 0xFC088005
85 #define MCFEPORT_EPFR 0xFC088006
87 #define MCFGPIO_PODR_BUSCTL 0xFC0A4000
88 #define MCFGPIO_PODR_BE 0xFC0A4001
89 #define MCFGPIO_PODR_CS 0xFC0A4002
90 #define MCFGPIO_PODR_FECI2C 0xFC0A4003
91 #define MCFGPIO_PODR_QSPI 0xFC0A4004
92 #define MCFGPIO_PODR_TIMER 0xFC0A4005
93 #define MCFGPIO_PODR_UART 0xFC0A4006
94 #define MCFGPIO_PODR_FECH 0xFC0A4007
95 #define MCFGPIO_PODR_FECL 0xFC0A4008
97 #define MCFGPIO_PDDR_BUSCTL 0xFC0A400C
98 #define MCFGPIO_PDDR_BE 0xFC0A400D
99 #define MCFGPIO_PDDR_CS 0xFC0A400E
100 #define MCFGPIO_PDDR_FECI2C 0xFC0A400F
101 #define MCFGPIO_PDDR_QSPI 0xFC0A4010
102 #define MCFGPIO_PDDR_TIMER 0xFC0A4011
103 #define MCFGPIO_PDDR_UART 0xFC0A4012
104 #define MCFGPIO_PDDR_FECH 0xFC0A4013
105 #define MCFGPIO_PDDR_FECL 0xFC0A4014
107 #define MCFGPIO_PPDSDR_CS 0xFC0A401A
108 #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B
109 #define MCFGPIO_PPDSDR_QSPI 0xFC0A401C
110 #define MCFGPIO_PPDSDR_TIMER 0xFC0A401D
111 #define MCFGPIO_PPDSDR_UART 0xFC0A401E
112 #define MCFGPIO_PPDSDR_FECH 0xFC0A401F
113 #define MCFGPIO_PPDSDR_FECL 0xFC0A4020
115 #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024
116 #define MCFGPIO_PCLRR_BE 0xFC0A4025
117 #define MCFGPIO_PCLRR_CS 0xFC0A4026
118 #define MCFGPIO_PCLRR_FECI2C 0xFC0A4027
119 #define MCFGPIO_PCLRR_QSPI 0xFC0A4028
120 #define MCFGPIO_PCLRR_TIMER 0xFC0A4029
121 #define MCFGPIO_PCLRR_UART 0xFC0A402A
122 #define MCFGPIO_PCLRR_FECH 0xFC0A402B
123 #define MCFGPIO_PCLRR_FECL 0xFC0A402C
126 * Generic GPIO support
128 #define MCFGPIO_PODR MCFGPIO_PODR_CS
129 #define MCFGPIO_PDDR MCFGPIO_PDDR_CS
130 #define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS
131 #define MCFGPIO_SETR MCFGPIO_PPDSDR_CS
132 #define MCFGPIO_CLRR MCFGPIO_PCLRR_CS
134 #define MCFGPIO_PIN_MAX 80
135 #define MCFGPIO_IRQ_MAX 8
136 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
138 #define MCF_GPIO_PAR_UART 0xFC0A4036
139 #define MCF_GPIO_PAR_FECI2C 0xFC0A4033
140 #define MCF_GPIO_PAR_QSPI 0xFC0A4034
141 #define MCF_GPIO_PAR_FEC 0xFC0A4038
143 #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
144 #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
146 #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040)
147 #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080)
149 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
150 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
155 #define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
156 #define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
161 #define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */
162 #define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */
163 #define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */
168 #define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */
169 #define MCFFEC_SIZE0 0x800 /* Register set size */
174 #define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */
175 #define MCFQSPI_SIZE 0x40 /* Register set size */
177 #define MCFQSPI_CS0 46
178 #define MCFQSPI_CS1 47
179 #define MCFQSPI_CS2 27
182 * Reset Control Unit.
184 #define MCF_RCR 0xFC0A0000
185 #define MCF_RSR 0xFC0A0001
187 #define MCF_RCR_SWRESET 0x80 /* Software reset bit */
188 #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
190 /****************************************************************************/
191 #endif /* m520xsim_h */