2 * USB block power/access management abstraction.
4 * Au1000+: The OHCI block control register is at the far end of the OHCI memory
5 * area. Au1550 has OHCI on different base address. No need to handle
7 * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
8 * as well as the PHY for EHCI and UDC.
12 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/syscore_ops.h>
17 #include <asm/mach-au1x00/au1000.h>
19 /* control register offsets */
20 #define AU1000_OHCICFG 0x7fffc
21 #define AU1550_OHCICFG 0x07ffc
22 #define AU1200_USBCFG 0x04
24 /* Au1000 USB block config bits */
25 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
26 #define USBHEN_CE (1 << 3) /* OHCI block clock enable */
27 #define USBHEN_E (1 << 2) /* OHCI block enable */
28 #define USBHEN_C (1 << 1) /* OHCI block coherency bit */
29 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
31 /* Au1200 USB config bits */
32 #define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */
33 #define USBCFG_RDCOMB (1 << 30) /* read combining (undoc) */
34 #define USBCFG_UNKNOWN (5 << 20) /* unknown, leave this way */
35 #define USBCFG_SSD (1 << 23) /* serial short detect en */
36 #define USBCFG_PPE (1 << 19) /* HS PHY PLL */
37 #define USBCFG_UCE (1 << 18) /* UDC clock enable */
38 #define USBCFG_ECE (1 << 17) /* EHCI clock enable */
39 #define USBCFG_OCE (1 << 16) /* OHCI clock enable */
40 #define USBCFG_FLA(x) (((x) & 0x3f) << 8)
41 #define USBCFG_UCAM (1 << 7) /* coherent access (undoc) */
42 #define USBCFG_GME (1 << 6) /* OTG mem access */
43 #define USBCFG_DBE (1 << 5) /* UDC busmaster enable */
44 #define USBCFG_DME (1 << 4) /* UDC mem enable */
45 #define USBCFG_EBE (1 << 3) /* EHCI busmaster enable */
46 #define USBCFG_EME (1 << 2) /* EHCI mem enable */
47 #define USBCFG_OBE (1 << 1) /* OHCI busmaster enable */
48 #define USBCFG_OME (1 << 0) /* OHCI mem enable */
49 #define USBCFG_INIT_AU1200 (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\
50 USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \
51 USBCFG_GME | USBCFG_DBE | USBCFG_DME | \
52 USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \
55 /* Au1300 USB config registers */
56 #define USB_DWC_CTRL1 0x00
57 #define USB_DWC_CTRL2 0x04
58 #define USB_VBUS_TIMER 0x10
59 #define USB_SBUS_CTRL 0x14
60 #define USB_MSR_ERR 0x18
61 #define USB_DWC_CTRL3 0x1C
62 #define USB_DWC_CTRL4 0x20
63 #define USB_OTG_STATUS 0x28
64 #define USB_DWC_CTRL5 0x2C
65 #define USB_DWC_CTRL6 0x30
66 #define USB_DWC_CTRL7 0x34
67 #define USB_PHY_STATUS 0xC0
68 #define USB_INT_STATUS 0xC4
69 #define USB_INT_ENABLE 0xC8
71 #define USB_DWC_CTRL1_OTGD 0x04 /* set to DISable OTG */
72 #define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */
73 #define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */
75 #define USB_DWC_CTRL2_PHY1RS 0x04 /* set to enable PHY1 */
76 #define USB_DWC_CTRL2_PHY0RS 0x02 /* set to enable PHY0 */
77 #define USB_DWC_CTRL2_PHYRS 0x01 /* set to enable PHY */
79 #define USB_DWC_CTRL3_OHCI1_CKEN (1 << 19)
80 #define USB_DWC_CTRL3_OHCI0_CKEN (1 << 18)
81 #define USB_DWC_CTRL3_EHCI0_CKEN (1 << 17)
82 #define USB_DWC_CTRL3_OTG0_CKEN (1 << 16)
84 #define USB_SBUS_CTRL_SBCA 0x04 /* coherent access */
86 #define USB_INTEN_FORCE 0x20
87 #define USB_INTEN_PHY 0x10
88 #define USB_INTEN_UDC 0x08
89 #define USB_INTEN_EHCI 0x04
90 #define USB_INTEN_OHCI1 0x02
91 #define USB_INTEN_OHCI0 0x01
93 static DEFINE_SPINLOCK(alchemy_usb_lock);
95 static inline void __au1300_usb_phyctl(void __iomem *base, int enable)
99 r = __raw_readl(base + USB_DWC_CTRL2);
100 s = __raw_readl(base + USB_DWC_CTRL3);
102 s &= USB_DWC_CTRL3_OHCI1_CKEN | USB_DWC_CTRL3_OHCI0_CKEN |
103 USB_DWC_CTRL3_EHCI0_CKEN | USB_DWC_CTRL3_OTG0_CKEN;
106 /* simply enable all PHYs */
107 r |= USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
109 __raw_writel(r, base + USB_DWC_CTRL2);
112 /* no USB block active, do disable all PHYs */
113 r &= ~(USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
114 USB_DWC_CTRL2_PHYRS);
115 __raw_writel(r, base + USB_DWC_CTRL2);
120 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id)
125 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */
128 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */
129 r |= (id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
130 : USB_DWC_CTRL3_OHCI1_CKEN;
131 __raw_writel(r, base + USB_DWC_CTRL3);
134 __au1300_usb_phyctl(base, enable); /* power up the PHYs */
136 r = __raw_readl(base + USB_INT_ENABLE);
137 r |= (id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1;
138 __raw_writel(r, base + USB_INT_ENABLE);
141 /* reset the OHCI start clock bit */
142 __raw_writel(0, base + USB_DWC_CTRL7);
145 r = __raw_readl(base + USB_INT_ENABLE);
146 r &= ~((id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1);
147 __raw_writel(r, base + USB_INT_ENABLE);
150 r = __raw_readl(base + USB_DWC_CTRL3);
151 r &= ~((id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
152 : USB_DWC_CTRL3_OHCI1_CKEN);
153 __raw_writel(r, base + USB_DWC_CTRL3);
156 __au1300_usb_phyctl(base, enable);
160 static inline void __au1300_ehci_control(void __iomem *base, int enable)
165 r = __raw_readl(base + USB_DWC_CTRL3);
166 r |= USB_DWC_CTRL3_EHCI0_CKEN;
167 __raw_writel(r, base + USB_DWC_CTRL3);
170 r = __raw_readl(base + USB_DWC_CTRL1);
171 r |= USB_DWC_CTRL1_HSTRS;
172 __raw_writel(r, base + USB_DWC_CTRL1);
175 __au1300_usb_phyctl(base, enable);
177 r = __raw_readl(base + USB_INT_ENABLE);
179 __raw_writel(r, base + USB_INT_ENABLE);
182 r = __raw_readl(base + USB_INT_ENABLE);
183 r &= ~USB_INTEN_EHCI;
184 __raw_writel(r, base + USB_INT_ENABLE);
187 r = __raw_readl(base + USB_DWC_CTRL1);
188 r &= ~USB_DWC_CTRL1_HSTRS;
189 __raw_writel(r, base + USB_DWC_CTRL1);
192 r = __raw_readl(base + USB_DWC_CTRL3);
193 r &= ~USB_DWC_CTRL3_EHCI0_CKEN;
194 __raw_writel(r, base + USB_DWC_CTRL3);
197 __au1300_usb_phyctl(base, enable);
201 static inline void __au1300_udc_control(void __iomem *base, int enable)
206 r = __raw_readl(base + USB_DWC_CTRL1);
207 r |= USB_DWC_CTRL1_DCRS;
208 __raw_writel(r, base + USB_DWC_CTRL1);
211 __au1300_usb_phyctl(base, enable);
213 r = __raw_readl(base + USB_INT_ENABLE);
215 __raw_writel(r, base + USB_INT_ENABLE);
218 r = __raw_readl(base + USB_INT_ENABLE);
220 __raw_writel(r, base + USB_INT_ENABLE);
223 r = __raw_readl(base + USB_DWC_CTRL1);
224 r &= ~USB_DWC_CTRL1_DCRS;
225 __raw_writel(r, base + USB_DWC_CTRL1);
228 __au1300_usb_phyctl(base, enable);
232 static inline void __au1300_otg_control(void __iomem *base, int enable)
236 r = __raw_readl(base + USB_DWC_CTRL3);
237 r |= USB_DWC_CTRL3_OTG0_CKEN;
238 __raw_writel(r, base + USB_DWC_CTRL3);
241 r = __raw_readl(base + USB_DWC_CTRL1);
242 r &= ~USB_DWC_CTRL1_OTGD;
243 __raw_writel(r, base + USB_DWC_CTRL1);
246 __au1300_usb_phyctl(base, enable);
248 r = __raw_readl(base + USB_DWC_CTRL1);
249 r |= USB_DWC_CTRL1_OTGD;
250 __raw_writel(r, base + USB_DWC_CTRL1);
253 r = __raw_readl(base + USB_DWC_CTRL3);
254 r &= ~USB_DWC_CTRL3_OTG0_CKEN;
255 __raw_writel(r, base + USB_DWC_CTRL3);
258 __au1300_usb_phyctl(base, enable);
262 static inline int au1300_usb_control(int block, int enable)
265 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
269 case ALCHEMY_USB_OHCI0:
270 __au1300_ohci_control(base, enable, 0);
272 case ALCHEMY_USB_OHCI1:
273 __au1300_ohci_control(base, enable, 1);
275 case ALCHEMY_USB_EHCI0:
276 __au1300_ehci_control(base, enable);
278 case ALCHEMY_USB_UDC0:
279 __au1300_udc_control(base, enable);
281 case ALCHEMY_USB_OTG0:
282 __au1300_otg_control(base, enable);
290 static inline void au1300_usb_init(void)
293 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
295 /* set some sane defaults. Note: we don't fiddle with DWC_CTRL4
296 * here at all: Port 2 routing (EHCI or UDC) must be set either
297 * by boot firmware or platform init code; I can't autodetect
300 __raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */
302 __raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */
304 __raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */
306 __raw_writel(~0, base + USB_INT_STATUS); /* clear int status */
308 /* set coherent access bit */
309 __raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL);
313 static inline void __au1200_ohci_control(void __iomem *base, int enable)
315 unsigned long r = __raw_readl(base + AU1200_USBCFG);
317 __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG);
321 __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG);
327 static inline void __au1200_ehci_control(void __iomem *base, int enable)
329 unsigned long r = __raw_readl(base + AU1200_USBCFG);
331 __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG);
335 if (!(r & USBCFG_UCE)) /* UDC also off? */
336 r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
337 __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG);
343 static inline void __au1200_udc_control(void __iomem *base, int enable)
345 unsigned long r = __raw_readl(base + AU1200_USBCFG);
347 __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG);
350 if (!(r & USBCFG_ECE)) /* EHCI also off? */
351 r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
352 __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG);
357 static inline int au1200_coherency_bug(void)
359 #if defined(CONFIG_DMA_COHERENT)
360 /* Au1200 AB USB does not support coherent memory */
361 if (!(read_c0_prid() & 0xff)) {
362 printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n");
363 printk(KERN_INFO "Au1200 USB: update your board or re-configure"
371 static inline int au1200_usb_control(int block, int enable)
374 (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
378 case ALCHEMY_USB_OHCI0:
379 ret = au1200_coherency_bug();
382 __au1200_ohci_control(base, enable);
384 case ALCHEMY_USB_UDC0:
385 __au1200_udc_control(base, enable);
387 case ALCHEMY_USB_EHCI0:
388 ret = au1200_coherency_bug();
391 __au1200_ehci_control(base, enable);
401 /* initialize USB block(s) to a known working state */
402 static inline void au1200_usb_init(void)
405 (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
406 __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
411 static inline void au1000_usb_init(unsigned long rb, int reg)
413 void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
414 unsigned long r = __raw_readl(base);
416 #if defined(__BIG_ENDIAN)
421 __raw_writel(r, base);
427 static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
429 void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
430 unsigned long r = __raw_readl(base + creg);
433 __raw_writel(r | USBHEN_CE, base + creg);
436 __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg);
440 /* wait for reset complete (read reg twice: au1500 erratum) */
441 while (__raw_readl(base + creg),
442 !(__raw_readl(base + creg) & USBHEN_RD))
445 __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
450 static inline int au1000_usb_control(int block, int enable, unsigned long rb,
456 case ALCHEMY_USB_OHCI0:
457 __au1xx0_ohci_control(enable, rb, creg);
466 * alchemy_usb_control - control Alchemy on-chip USB blocks
467 * @block: USB block to target
468 * @enable: set 1 to enable a block, 0 to disable
470 int alchemy_usb_control(int block, int enable)
475 spin_lock_irqsave(&alchemy_usb_lock, flags);
476 switch (alchemy_get_cputype()) {
477 case ALCHEMY_CPU_AU1000:
478 case ALCHEMY_CPU_AU1500:
479 case ALCHEMY_CPU_AU1100:
480 ret = au1000_usb_control(block, enable,
481 AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
483 case ALCHEMY_CPU_AU1550:
484 ret = au1000_usb_control(block, enable,
485 AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
487 case ALCHEMY_CPU_AU1200:
488 ret = au1200_usb_control(block, enable);
490 case ALCHEMY_CPU_AU1300:
491 ret = au1300_usb_control(block, enable);
496 spin_unlock_irqrestore(&alchemy_usb_lock, flags);
499 EXPORT_SYMBOL_GPL(alchemy_usb_control);
502 static unsigned long alchemy_usb_pmdata[2];
504 static void au1000_usb_pm(unsigned long br, int creg, int susp)
506 void __iomem *base = (void __iomem *)KSEG1ADDR(br);
509 alchemy_usb_pmdata[0] = __raw_readl(base + creg);
510 /* There appears to be some undocumented reset register.... */
511 __raw_writel(0, base + 0x04);
513 __raw_writel(0, base + creg);
516 __raw_writel(alchemy_usb_pmdata[0], base + creg);
521 static void au1200_usb_pm(int susp)
524 (void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR);
526 /* save OTG_CAP/MUX registers which indicate port routing */
527 /* FIXME: write an OTG driver to do that */
528 alchemy_usb_pmdata[0] = __raw_readl(base + 0x00);
529 alchemy_usb_pmdata[1] = __raw_readl(base + 0x04);
531 /* restore access to all MMIO areas */
534 /* restore OTG_CAP/MUX registers */
535 __raw_writel(alchemy_usb_pmdata[0], base + 0x00);
536 __raw_writel(alchemy_usb_pmdata[1], base + 0x04);
541 static void au1300_usb_pm(int susp)
544 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
545 /* remember Port2 routing */
547 alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4);
550 __raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4);
555 static void alchemy_usb_pm(int susp)
557 switch (alchemy_get_cputype()) {
558 case ALCHEMY_CPU_AU1000:
559 case ALCHEMY_CPU_AU1500:
560 case ALCHEMY_CPU_AU1100:
561 au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp);
563 case ALCHEMY_CPU_AU1550:
564 au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp);
566 case ALCHEMY_CPU_AU1200:
569 case ALCHEMY_CPU_AU1300:
575 static int alchemy_usb_suspend(void)
581 static void alchemy_usb_resume(void)
586 static struct syscore_ops alchemy_usb_pm_ops = {
587 .suspend = alchemy_usb_suspend,
588 .resume = alchemy_usb_resume,
591 static int __init alchemy_usb_init(void)
593 switch (alchemy_get_cputype()) {
594 case ALCHEMY_CPU_AU1000:
595 case ALCHEMY_CPU_AU1500:
596 case ALCHEMY_CPU_AU1100:
597 au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
599 case ALCHEMY_CPU_AU1550:
600 au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
602 case ALCHEMY_CPU_AU1200:
605 case ALCHEMY_CPU_AU1300:
610 register_syscore_ops(&alchemy_usb_pm_ops);
614 arch_initcall(alchemy_usb_init);