2 * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
4 * All Alchemy development boards (except, of course, the weird PB1000)
5 * have a few registers in a CPLD with standardised layout; they mostly
6 * only differ in base address.
7 * All registers are 16bits wide with 32bit spacing.
10 #include <linux/module.h>
11 #include <linux/spinlock.h>
12 #include <asm/addrspace.h>
14 #include <asm/mach-db1x00/bcsr.h>
16 static struct bcsr_reg {
19 } bcsr_regs[BCSR_CNT];
21 void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)
25 bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys));
26 bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys));
28 for (i = 0; i < BCSR_CNT; i++) {
29 if (i >= BCSR_HEXLEDS)
30 bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys +
31 (0x04 * (i - BCSR_HEXLEDS));
33 bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys +
36 spin_lock_init(&bcsr_regs[i].lock);
40 unsigned short bcsr_read(enum bcsr_id reg)
45 spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
46 r = __raw_readw(bcsr_regs[reg].raddr);
47 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
50 EXPORT_SYMBOL_GPL(bcsr_read);
52 void bcsr_write(enum bcsr_id reg, unsigned short val)
56 spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
57 __raw_writew(val, bcsr_regs[reg].raddr);
59 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
61 EXPORT_SYMBOL_GPL(bcsr_write);
63 void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set)
68 spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
69 r = __raw_readw(bcsr_regs[reg].raddr);
72 __raw_writew(r, bcsr_regs[reg].raddr);
74 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
76 EXPORT_SYMBOL_GPL(bcsr_mod);