3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Db1x00 board setup.
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 #include <linux/gpio.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
34 #include <asm/mach-au1x00/au1000.h>
35 #include <asm/mach-au1x00/au1xxx_eth.h>
36 #include <asm/mach-db1x00/db1x00.h>
37 #include <asm/mach-db1x00/bcsr.h>
41 #ifdef CONFIG_MIPS_DB1500
42 char irq_tab_alchemy[][5] __initdata = {
43 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
44 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
49 * Micrel/Kendin 5 port switch attached to MAC0,
50 * MAC0 is associated with PHY address 5 (== WAN port)
51 * MAC1 is not associated with any PHY, since it's connected directly
53 * no interrupts are used
55 static struct au1000_eth_platform_data eth0_pdata = {
56 .phy_static_config = 1,
60 #ifdef CONFIG_MIPS_BOSPORUS
61 char irq_tab_alchemy[][5] __initdata = {
62 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
63 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */
64 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
70 #ifdef CONFIG_MIPS_MIRAGE
71 char irq_tab_alchemy[][5] __initdata = {
72 [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
73 [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
74 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
78 #ifdef CONFIG_MIPS_DB1550
79 char irq_tab_alchemy[][5] __initdata = {
80 [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
81 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
82 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
86 const char *get_system_type(void)
88 #ifdef CONFIG_MIPS_BOSPORUS
89 return "Alchemy Bosporus Gateway Reference";
91 return "Alchemy Db1x00";
95 void board_reset(void)
97 bcsr_write(BCSR_SYSTEM, 0);
100 void __init board_setup(void)
102 unsigned long bcsr1, bcsr2;
106 bcsr1 = DB1000_BCSR_PHYS_ADDR;
107 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
111 #ifdef CONFIG_MIPS_DB1000
112 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
114 #ifdef CONFIG_MIPS_DB1500
115 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
117 #ifdef CONFIG_MIPS_DB1100
118 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
120 #ifdef CONFIG_MIPS_BOSPORUS
121 au1xxx_override_eth_cfg(0, ð0_pdata);
123 printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
125 #ifdef CONFIG_MIPS_MIRAGE
126 printk(KERN_INFO "AMD Alchemy Mirage Board\n");
128 #ifdef CONFIG_MIPS_DB1550
129 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
131 bcsr1 = DB1550_BCSR_PHYS_ADDR;
132 bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
135 /* initialize board register space */
136 bcsr_init(bcsr1, bcsr2);
138 argptr = prom_getcmdline();
139 #ifdef CONFIG_SERIAL_8250_CONSOLE
140 argptr = strstr(argptr, "console=");
141 if (argptr == NULL) {
142 argptr = prom_getcmdline();
143 strcat(argptr, " console=ttyS0,115200");
147 #ifdef CONFIG_FB_AU1100
148 argptr = strstr(argptr, "video=");
149 if (argptr == NULL) {
150 argptr = prom_getcmdline();
152 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
156 #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
157 /* au1000 does not support vra, au1500 and au1100 do */
158 strcat(argptr, " au1000_audio=vra");
159 argptr = prom_getcmdline();
162 /* Not valid for Au1550 */
163 #if defined(CONFIG_IRDA) && \
164 (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
165 /* Set IRFIRSEL instead of GPIO15 */
166 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
167 au_writel(pin_func, SYS_PINFUNC);
168 /* Power off until the driver is in use */
169 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
170 BCSR_RESETS_IRDA_MODE_OFF);
172 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
174 /* Enable GPIO[31:0] inputs */
175 alchemy_gpio1_input_enable();
177 #ifdef CONFIG_MIPS_MIRAGE
178 /* GPIO[20] is output */
179 alchemy_gpio_direction_output(20, 0);
181 /* Set GPIO[210:208] instead of SSI_0 */
182 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
184 /* Set GPIO[215:211] for LEDs */
187 /* Set GPIO[214:213] for more LEDs */
190 /* Set GPIO[207:200] instead of PCMCIA/LCD */
191 pin_func |= SYS_PF_LCD | SYS_PF_PC;
192 au_writel(pin_func, SYS_PINFUNC);
195 * Enable speaker amplifier. This should
196 * be part of the audio driver.
198 alchemy_gpio_direction_output(209, 1);
204 static int __init db1x00_init_irq(void)
206 #if defined(CONFIG_MIPS_MIRAGE)
207 set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
208 #elif defined(CONFIG_MIPS_DB1550)
209 set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
210 set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
211 set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
212 set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
213 set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
214 set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
215 #elif defined(CONFIG_MIPS_DB1500)
216 set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
217 set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
218 set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
219 set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
220 set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
221 set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
222 #elif defined(CONFIG_MIPS_DB1100)
223 set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
224 set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
225 set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
226 set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
227 set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
228 set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
229 #elif defined(CONFIG_MIPS_DB1000)
230 set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
231 set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
232 set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
233 set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
234 set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
235 set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
239 arch_initcall(db1x00_init_irq);