2 * Copyright 2000, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/delay.h>
27 #include <linux/gpio.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <asm/mach-au1x00/au1000.h>
31 #include <asm/mach-pb1x00/pb1000.h>
34 #include "../platform.h"
36 const char *get_system_type(void)
38 return "Alchemy Pb1000";
41 void board_reset(void)
45 void __init board_setup(void)
47 u32 pin_func, static_cfg0;
48 u32 sys_freqctrl, sys_clksrc;
49 u32 prid = read_c0_prid();
54 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
55 au_writel(8, SYS_AUXPLL);
56 au_writel(0, SYS_PINSTATERD);
59 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
60 /* Zero and disable FREQ2 */
61 sys_freqctrl = au_readl(SYS_FREQCTRL0);
62 sys_freqctrl &= ~0xFFF00000;
63 au_writel(sys_freqctrl, SYS_FREQCTRL0);
65 /* Zero and disable USBH/USBD clocks */
66 sys_clksrc = au_readl(SYS_CLKSRC);
67 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
68 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
69 au_writel(sys_clksrc, SYS_CLKSRC);
71 sys_freqctrl = au_readl(SYS_FREQCTRL0);
72 sys_freqctrl &= ~0xFFF00000;
74 sys_clksrc = au_readl(SYS_CLKSRC);
75 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
76 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
78 switch (prid & 0x000000FF) {
82 /* CPU core freq to 48 MHz to slow it way down... */
83 au_writel(4, SYS_CPUPLL);
86 * Setup 48 MHz FREQ2 from CPUPLL for USB Host
87 * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
89 sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
90 au_writel(sys_freqctrl, SYS_FREQCTRL0);
92 /* CPU core freq to 384 MHz */
93 au_writel(0x20, SYS_CPUPLL);
95 printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
98 default: /* HC and newer */
99 /* FREQ2 = aux / 2 = 48 MHz */
100 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
101 SYS_FC_FE2 | SYS_FC_FS2;
102 au_writel(sys_freqctrl, SYS_FREQCTRL0);
107 * Route 48 MHz FREQ2 into USB Host and/or Device
109 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
110 au_writel(sys_clksrc, SYS_CLKSRC);
112 /* Configure pins GPIO[14:9] as GPIO */
113 pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
115 /* 2nd USB port is USB host */
116 pin_func |= SYS_PF_USB;
118 au_writel(pin_func, SYS_PINFUNC);
120 alchemy_gpio_direction_input(11);
121 alchemy_gpio_direction_input(13);
122 alchemy_gpio_direction_output(4, 0);
123 alchemy_gpio_direction_output(5, 0);
124 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
126 /* Make GPIO 15 an input (for interrupt line) */
127 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
128 /* We don't need I2S, so make it available for GPIO[31:29] */
129 pin_func |= SYS_PF_I2S;
130 au_writel(pin_func, SYS_PINFUNC);
132 alchemy_gpio_direction_input(15);
134 static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
135 au_writel(static_cfg0, MEM_STCFG0);
137 /* configure RCE2* for LCD */
138 au_writel(0x00000004, MEM_STCFG2);
141 au_writel(0x09000000, MEM_STTIME2);
143 /* Set 32-bit base address decoding for RCE2* */
144 au_writel(0x10003ff0, MEM_STADDR2);
148 * Expand CE0 to cover PCI
150 au_writel(0x11803e40, MEM_STADDR1);
152 /* Burst visibility on */
153 au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
155 au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */
156 au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */
158 /* Setup the static bus controller */
159 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
160 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
161 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
164 * Enable Au1000 BCLK switching - note: sed1356 must not use
165 * its BCLK (Au1000 LCLK) for any timings
167 switch (prid & 0x000000FF) {
172 default: /* HC and newer */
174 * Enable sys bus clock divider when IDLE state or no bus
177 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
182 static int __init pb1000_init_irq(void)
184 set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
187 arch_initcall(pb1000_init_irq);
189 static int __init pb1000_device_init(void)
191 return db1x_register_norflash(8 * 1024 * 1024, 4, 0);
193 device_initcall(pb1000_device_init);