2 * Copyright 2000, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/delay.h>
27 #include <linux/gpio.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <asm/mach-au1x00/au1000.h>
32 #include <asm/mach-db1x00/bcsr.h>
37 char irq_tab_alchemy[][5] __initdata = {
38 [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */
39 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
43 const char *get_system_type(void)
45 return "Alchemy Pb1500";
48 void board_reset(void)
50 bcsr_write(BCSR_SYSTEM, 0);
53 void __init board_setup(void)
56 u32 sys_freqctrl, sys_clksrc;
59 bcsr_init(DB1000_BCSR_PHYS_ADDR,
60 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
62 argptr = prom_getcmdline();
63 #ifdef CONFIG_SERIAL_8250_CONSOLE
64 argptr = strstr(argptr, "console=");
66 argptr = prom_getcmdline();
67 strcat(argptr, " console=ttyS0,115200");
71 #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
72 /* au1000 does not support vra, au1500 and au1100 do */
73 strcat(argptr, " au1000_audio=vra");
74 argptr = prom_getcmdline();
77 sys_clksrc = sys_freqctrl = pin_func = 0;
78 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
79 au_writel(8, SYS_AUXPLL);
80 au_writel(0, SYS_PINSTATERD);
83 /* GPIO201 is input for PCMCIA card detect */
84 /* GPIO203 is input for PCMCIA interrupt request */
85 alchemy_gpio_direction_input(201);
86 alchemy_gpio_direction_input(203);
88 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
90 /* Zero and disable FREQ2 */
91 sys_freqctrl = au_readl(SYS_FREQCTRL0);
92 sys_freqctrl &= ~0xFFF00000;
93 au_writel(sys_freqctrl, SYS_FREQCTRL0);
95 /* zero and disable USBH/USBD clocks */
96 sys_clksrc = au_readl(SYS_CLKSRC);
97 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
98 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
99 au_writel(sys_clksrc, SYS_CLKSRC);
101 sys_freqctrl = au_readl(SYS_FREQCTRL0);
102 sys_freqctrl &= ~0xFFF00000;
104 sys_clksrc = au_readl(SYS_CLKSRC);
105 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
106 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
108 /* FREQ2 = aux/2 = 48 MHz */
109 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
110 au_writel(sys_freqctrl, SYS_FREQCTRL0);
113 * Route 48MHz FREQ2 into USB Host and/or Device
115 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
116 au_writel(sys_clksrc, SYS_CLKSRC);
118 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
119 /* 2nd USB port is USB host */
120 pin_func |= SYS_PF_USB;
121 au_writel(pin_func, SYS_PINFUNC);
122 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
125 /* Setup PCI bus controller */
126 au_writel(0, Au1500_PCI_CMEM);
127 au_writel(0x00003fff, Au1500_CFG_BASE);
128 #if defined(__MIPSEB__)
129 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
131 au_writel(0xf, Au1500_PCI_CFG);
133 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
134 au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
135 au_writel(0x02a00356, Au1500_PCI_STATCMD);
136 au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
137 au_writel(0x00000008, Au1500_PCI_MBAR);
141 /* Enable sys bus clock divider when IDLE state or no bus activity. */
142 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
144 /* Enable the RTC if not already enabled */
145 if (!(au_readl(0xac000028) & 0x20)) {
146 printk(KERN_INFO "enabling clock ...\n");
147 au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
149 /* Put the clock in BCD mode */
150 if (au_readl(0xac00002c) & 0x4) { /* reg B */
151 au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
156 static int __init pb1500_init_irq(void)
158 set_irq_type(AU1000_GPIO_9, IRQF_TRIGGER_LOW); /* CD0# */
159 set_irq_type(AU1000_GPIO_10, IRQF_TRIGGER_LOW); /* CARD0 */
160 set_irq_type(AU1000_GPIO_11, IRQF_TRIGGER_LOW); /* STSCHG0# */
161 set_irq_type(AU1500_GPIO_204, IRQF_TRIGGER_HIGH);
162 set_irq_type(AU1500_GPIO_201, IRQF_TRIGGER_LOW);
163 set_irq_type(AU1500_GPIO_202, IRQF_TRIGGER_LOW);
164 set_irq_type(AU1500_GPIO_203, IRQF_TRIGGER_LOW);
165 set_irq_type(AU1500_GPIO_205, IRQF_TRIGGER_LOW);
169 arch_initcall(pb1500_init_irq);