2 * Atheros AR71xx/AR724x/AR913x specific interrupt handling
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/irqchip.h>
19 #include <linux/of_irq.h>
21 #include <asm/irq_cpu.h>
22 #include <asm/mipsregs.h>
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include "machtypes.h"
29 static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
31 void __iomem *base = ath79_reset_base;
34 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
35 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
43 int bit = __ffs(pending);
45 generic_handle_irq(ATH79_MISC_IRQ(bit));
50 static void ar71xx_misc_irq_unmask(struct irq_data *d)
52 unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
53 void __iomem *base = ath79_reset_base;
56 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
57 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
60 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
63 static void ar71xx_misc_irq_mask(struct irq_data *d)
65 unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
66 void __iomem *base = ath79_reset_base;
69 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
70 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
73 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
76 static void ar724x_misc_irq_ack(struct irq_data *d)
78 unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
79 void __iomem *base = ath79_reset_base;
82 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
83 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
86 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
89 static struct irq_chip ath79_misc_irq_chip = {
91 .irq_unmask = ar71xx_misc_irq_unmask,
92 .irq_mask = ar71xx_misc_irq_mask,
95 static void __init ath79_misc_irq_init(void)
97 void __iomem *base = ath79_reset_base;
100 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
101 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
103 if (soc_is_ar71xx() || soc_is_ar913x())
104 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
105 else if (soc_is_ar724x() ||
109 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
113 for (i = ATH79_MISC_IRQ_BASE;
114 i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
115 irq_set_chip_and_handler(i, &ath79_misc_irq_chip,
119 irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);
122 static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
126 status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
128 if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
129 ath79_ddr_wb_flush(3);
130 generic_handle_irq(ATH79_IP2_IRQ(0));
131 } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
132 ath79_ddr_wb_flush(4);
133 generic_handle_irq(ATH79_IP2_IRQ(1));
135 spurious_interrupt();
139 static void ar934x_ip2_irq_init(void)
143 for (i = ATH79_IP2_IRQ_BASE;
144 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
145 irq_set_chip_and_handler(i, &dummy_irq_chip,
148 irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
151 static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
155 status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
156 status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
159 spurious_interrupt();
163 if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
164 /* TODO: flush DDR? */
165 generic_handle_irq(ATH79_IP2_IRQ(0));
168 if (status & QCA955X_EXT_INT_WMAC_ALL) {
169 /* TODO: flush DDR? */
170 generic_handle_irq(ATH79_IP2_IRQ(1));
174 static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
178 status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
179 status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
180 QCA955X_EXT_INT_USB1 |
181 QCA955X_EXT_INT_USB2;
184 spurious_interrupt();
188 if (status & QCA955X_EXT_INT_USB1) {
189 /* TODO: flush DDR? */
190 generic_handle_irq(ATH79_IP3_IRQ(0));
193 if (status & QCA955X_EXT_INT_USB2) {
194 /* TODO: flush DDR? */
195 generic_handle_irq(ATH79_IP3_IRQ(1));
198 if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
199 /* TODO: flush DDR? */
200 generic_handle_irq(ATH79_IP3_IRQ(2));
204 static void qca955x_irq_init(void)
208 for (i = ATH79_IP2_IRQ_BASE;
209 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
210 irq_set_chip_and_handler(i, &dummy_irq_chip,
213 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
215 for (i = ATH79_IP3_IRQ_BASE;
216 i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
217 irq_set_chip_and_handler(i, &dummy_irq_chip,
220 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
224 * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
225 * these devices typically allocate coherent DMA memory, however the
226 * DMA controller may still have some unsynchronized data in the FIFO.
227 * Issue a flush in the handlers to ensure that the driver sees
230 * This array map the interrupt lines to the DDR write buffer channels.
233 static unsigned irq_wb_chan[8] = {
234 -1, -1, -1, -1, -1, -1, -1, -1,
237 asmlinkage void plat_irq_dispatch(void)
239 unsigned long pending;
242 pending = read_c0_status() & read_c0_cause() & ST0_IM;
245 spurious_interrupt();
249 pending >>= CAUSEB_IP;
251 irq = fls(pending) - 1;
252 if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1)
253 ath79_ddr_wb_flush(irq_wb_chan[irq]);
254 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
255 pending &= ~BIT(irq);
259 #ifdef CONFIG_IRQCHIP
260 static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
262 irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
266 static const struct irq_domain_ops misc_irq_domain_ops = {
267 .xlate = irq_domain_xlate_onecell,
271 static int __init ath79_misc_intc_of_init(
272 struct device_node *node, struct device_node *parent)
274 void __iomem *base = ath79_reset_base;
275 struct irq_domain *domain;
278 irq = irq_of_parse_and_map(node, 0);
280 panic("Failed to get MISC IRQ");
282 domain = irq_domain_add_legacy(node, ATH79_MISC_IRQ_COUNT,
283 ATH79_MISC_IRQ_BASE, 0, &misc_irq_domain_ops, NULL);
285 panic("Failed to add MISC irqdomain");
287 /* Disable and clear all interrupts */
288 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
289 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
292 irq_set_chained_handler(irq, ath79_misc_irq_handler);
296 IRQCHIP_DECLARE(ath79_misc_intc, "qca,ar7100-misc-intc",
297 ath79_misc_intc_of_init);
299 static int __init ar79_cpu_intc_of_init(
300 struct device_node *node, struct device_node *parent)
304 /* Fill the irq_wb_chan table */
305 count = of_count_phandle_with_args(
306 node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
308 for (i = 0; i < count; i++) {
309 struct of_phandle_args args;
312 of_property_read_u32_index(
313 node, "qca,ddr-wb-channel-interrupts", i, &irq);
314 if (irq >= ARRAY_SIZE(irq_wb_chan))
317 err = of_parse_phandle_with_args(
318 node, "qca,ddr-wb-channels",
319 "#qca,ddr-wb-channel-cells",
324 irq_wb_chan[irq] = args.args[0];
325 pr_info("IRQ: Set flush channel of IRQ%d to %d\n",
329 return mips_cpu_irq_of_init(node, parent);
331 IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
332 ar79_cpu_intc_of_init);
336 void __init arch_init_irq(void)
338 if (mips_machtype == ATH79_MACH_GENERIC_OF) {
343 if (soc_is_ar71xx() || soc_is_ar724x() ||
344 soc_is_ar913x() || soc_is_ar933x()) {
347 } else if (soc_is_ar934x()) {
352 ath79_misc_irq_init();
355 ar934x_ip2_irq_init();
356 else if (soc_is_qca955x())