2 * Atheros AR71XX/AR724X/AR913X specific setup
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/bootmem.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
21 #include <asm/bootinfo.h>
23 #include <asm/time.h> /* for mips_hpt_frequency */
24 #include <asm/reboot.h> /* for _machine_{restart,halt} */
25 #include <asm/mips_machine.h>
27 #include <asm/mach-ath79/ath79.h>
28 #include <asm/mach-ath79/ar71xx_regs.h>
30 #include "dev-common.h"
31 #include "machtypes.h"
33 #define ATH79_SYS_TYPE_LEN 64
35 #define AR71XX_BASE_FREQ 40000000
36 #define AR724X_BASE_FREQ 5000000
37 #define AR913X_BASE_FREQ 5000000
39 static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
41 static void ath79_restart(char *command)
43 ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
49 static void ath79_halt(void)
55 static void __init ath79_detect_sys_type(void)
63 id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
64 major = id & REV_ID_MAJOR_MASK;
67 case REV_ID_MAJOR_AR71XX:
68 minor = id & AR71XX_REV_ID_MINOR_MASK;
69 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
70 rev &= AR71XX_REV_ID_REVISION_MASK;
72 case AR71XX_REV_ID_MINOR_AR7130:
73 ath79_soc = ATH79_SOC_AR7130;
77 case AR71XX_REV_ID_MINOR_AR7141:
78 ath79_soc = ATH79_SOC_AR7141;
82 case AR71XX_REV_ID_MINOR_AR7161:
83 ath79_soc = ATH79_SOC_AR7161;
89 case REV_ID_MAJOR_AR7240:
90 ath79_soc = ATH79_SOC_AR7240;
92 rev = id & AR724X_REV_ID_REVISION_MASK;
95 case REV_ID_MAJOR_AR7241:
96 ath79_soc = ATH79_SOC_AR7241;
98 rev = id & AR724X_REV_ID_REVISION_MASK;
101 case REV_ID_MAJOR_AR7242:
102 ath79_soc = ATH79_SOC_AR7242;
104 rev = id & AR724X_REV_ID_REVISION_MASK;
107 case REV_ID_MAJOR_AR913X:
108 minor = id & AR913X_REV_ID_MINOR_MASK;
109 rev = id >> AR913X_REV_ID_REVISION_SHIFT;
110 rev &= AR913X_REV_ID_REVISION_MASK;
112 case AR913X_REV_ID_MINOR_AR9130:
113 ath79_soc = ATH79_SOC_AR9130;
117 case AR913X_REV_ID_MINOR_AR9132:
118 ath79_soc = ATH79_SOC_AR9132;
124 case REV_ID_MAJOR_AR9330:
125 ath79_soc = ATH79_SOC_AR9330;
127 rev = id & AR933X_REV_ID_REVISION_MASK;
130 case REV_ID_MAJOR_AR9331:
131 ath79_soc = ATH79_SOC_AR9331;
133 rev = id & AR933X_REV_ID_REVISION_MASK;
136 case REV_ID_MAJOR_AR9341:
137 ath79_soc = ATH79_SOC_AR9341;
139 rev = id & AR934X_REV_ID_REVISION_MASK;
142 case REV_ID_MAJOR_AR9342:
143 ath79_soc = ATH79_SOC_AR9342;
145 rev = id & AR934X_REV_ID_REVISION_MASK;
148 case REV_ID_MAJOR_AR9344:
149 ath79_soc = ATH79_SOC_AR9344;
151 rev = id & AR934X_REV_ID_REVISION_MASK;
154 case REV_ID_MAJOR_QCA9556:
155 ath79_soc = ATH79_SOC_QCA9556;
157 rev = id & QCA955X_REV_ID_REVISION_MASK;
160 case REV_ID_MAJOR_QCA9558:
161 ath79_soc = ATH79_SOC_QCA9558;
163 rev = id & QCA955X_REV_ID_REVISION_MASK;
167 panic("ath79: unknown SoC, id:0x%08x", id);
172 if (soc_is_qca955x())
173 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
176 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
177 pr_info("SoC: %s\n", ath79_sys_type);
180 const char *get_system_type(void)
182 return ath79_sys_type;
185 unsigned int __cpuinit get_c0_compare_int(void)
187 return CP0_LEGACY_COMPARE_IRQ;
190 void __init plat_mem_setup(void)
192 set_io_port_base(KSEG1);
194 ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
196 ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
198 ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
199 AR71XX_DDR_CTRL_SIZE);
201 ath79_detect_sys_type();
202 detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
205 _machine_restart = ath79_restart;
206 _machine_halt = ath79_halt;
207 pm_power_off = ath79_halt;
210 void __init plat_time_init(void)
214 clk = clk_get(NULL, "cpu");
216 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
218 mips_hpt_frequency = clk_get_rate(clk) / 2;
221 static int __init ath79_setup(void)
224 ath79_register_uart();
225 ath79_register_wdt();
227 mips_machine_setup();
232 arch_initcall(ath79_setup);
234 static void __init ath79_generic_init(void)
239 MIPS_MACHINE(ATH79_MACH_GENERIC,
241 "Generic AR71XX/AR724X/AR913X based board",