2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/cpu.h>
14 #include <asm/cpu-info.h>
15 #include <asm/mipsregs.h>
16 #include <bcm63xx_cpu.h>
17 #include <bcm63xx_regs.h>
18 #include <bcm63xx_io.h>
19 #include <bcm63xx_irq.h>
21 const unsigned long *bcm63xx_regs_base;
22 EXPORT_SYMBOL(bcm63xx_regs_base);
24 const int *bcm63xx_irqs;
25 EXPORT_SYMBOL(bcm63xx_irqs);
27 static u16 bcm63xx_cpu_id;
28 static u8 bcm63xx_cpu_rev;
29 static unsigned int bcm63xx_cpu_freq;
30 static unsigned int bcm63xx_memory_size;
32 static const unsigned long bcm6328_regs_base[] = {
33 __GEN_CPU_REGS_TABLE(6328)
36 static const int bcm6328_irqs[] = {
37 __GEN_CPU_IRQ_TABLE(6328)
40 static const unsigned long bcm6338_regs_base[] = {
41 __GEN_CPU_REGS_TABLE(6338)
44 static const int bcm6338_irqs[] = {
45 __GEN_CPU_IRQ_TABLE(6338)
48 static const unsigned long bcm6345_regs_base[] = {
49 __GEN_CPU_REGS_TABLE(6345)
52 static const int bcm6345_irqs[] = {
53 __GEN_CPU_IRQ_TABLE(6345)
56 static const unsigned long bcm6348_regs_base[] = {
57 __GEN_CPU_REGS_TABLE(6348)
60 static const int bcm6348_irqs[] = {
61 __GEN_CPU_IRQ_TABLE(6348)
65 static const unsigned long bcm6358_regs_base[] = {
66 __GEN_CPU_REGS_TABLE(6358)
69 static const int bcm6358_irqs[] = {
70 __GEN_CPU_IRQ_TABLE(6358)
74 static const unsigned long bcm6362_regs_base[] = {
75 __GEN_CPU_REGS_TABLE(6362)
78 static const int bcm6362_irqs[] = {
79 __GEN_CPU_IRQ_TABLE(6362)
83 static const unsigned long bcm6368_regs_base[] = {
84 __GEN_CPU_REGS_TABLE(6368)
87 static const int bcm6368_irqs[] = {
88 __GEN_CPU_IRQ_TABLE(6368)
92 u16 __bcm63xx_get_cpu_id(void)
94 return bcm63xx_cpu_id;
97 EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
99 u8 bcm63xx_get_cpu_rev(void)
101 return bcm63xx_cpu_rev;
104 EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
106 unsigned int bcm63xx_get_cpu_freq(void)
108 return bcm63xx_cpu_freq;
111 unsigned int bcm63xx_get_memory_size(void)
113 return bcm63xx_memory_size;
116 static unsigned int detect_cpu_clock(void)
118 switch (bcm63xx_get_cpu_id()) {
121 unsigned int tmp, mips_pll_fcvo;
123 tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
124 mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
125 >> STRAPBUS_6328_FCVO_SHIFT;
127 switch (mips_pll_fcvo) {
147 /* BCM6338 has a fixed 240 Mhz frequency */
151 /* BCM6345 has a fixed 140Mhz frequency */
156 unsigned int tmp, n1, n2, m1;
158 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
159 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
160 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
161 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
162 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
166 return (16 * 1000000 * n1 * n2) / m1;
171 unsigned int tmp, n1, n2, m1;
173 /* 16MHz * N1 * N2 / M1_CPU */
174 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
175 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
176 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
177 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
178 return (16 * 1000000 * n1 * n2) / m1;
183 unsigned int tmp, mips_pll_fcvo;
185 tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
186 mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)
187 >> STRAPBUS_6362_FCVO_SHIFT;
188 switch (mips_pll_fcvo) {
219 unsigned int tmp, p1, p2, ndiv, m1;
221 /* (64MHz / P1) * P2 * NDIV / M1_CPU */
222 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
224 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
225 DMIPSPLLCFG_6368_P1_SHIFT;
227 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
228 DMIPSPLLCFG_6368_P2_SHIFT;
230 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
231 DMIPSPLLCFG_6368_NDIV_SHIFT;
233 tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
234 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
235 DMIPSPLLDIV_6368_MDIV_SHIFT;
237 return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
246 * attempt to detect the amount of memory installed
248 static unsigned int detect_memory_size(void)
250 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
253 if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
254 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
256 if (BCMCPU_IS_6345()) {
257 val = bcm_sdram_readl(SDRAM_MBASE_REG);
258 return (val * 8 * 1024 * 1024);
261 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
262 val = bcm_sdram_readl(SDRAM_CFG_REG);
263 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
264 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
265 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
266 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
269 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
270 val = bcm_memc_readl(MEMC_CFG_REG);
271 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
272 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
273 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
277 /* 0 => 11 address bits ... 2 => 13 address bits */
280 /* 0 => 8 address bits ... 2 => 10 address bits */
283 return 1 << (cols + rows + (is_32bits + 1) + banks);
286 void __init bcm63xx_cpu_init(void)
289 struct cpuinfo_mips *c = ¤t_cpu_data;
290 unsigned int cpu = smp_processor_id();
293 /* soc registers location depends on cpu type */
296 switch (c->cputype) {
298 if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT)
299 __cpu_name[cpu] = "Broadcom BCM6338";
302 chipid_reg = BCM_6345_PERF_BASE;
305 if ((read_c0_prid() & 0xf0) == 0x10)
306 chipid_reg = BCM_6345_PERF_BASE;
308 chipid_reg = BCM_6368_PERF_BASE;
313 * really early to panic, but delaying panic would not help since we
314 * will never get any working console
317 panic("unsupported Broadcom CPU");
319 /* read out CPU type */
320 tmp = bcm_readl(chipid_reg);
321 bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
322 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
324 switch (bcm63xx_cpu_id) {
326 bcm63xx_regs_base = bcm6328_regs_base;
327 bcm63xx_irqs = bcm6328_irqs;
330 bcm63xx_regs_base = bcm6338_regs_base;
331 bcm63xx_irqs = bcm6338_irqs;
334 bcm63xx_regs_base = bcm6345_regs_base;
335 bcm63xx_irqs = bcm6345_irqs;
338 bcm63xx_regs_base = bcm6348_regs_base;
339 bcm63xx_irqs = bcm6348_irqs;
342 bcm63xx_regs_base = bcm6358_regs_base;
343 bcm63xx_irqs = bcm6358_irqs;
346 bcm63xx_regs_base = bcm6362_regs_base;
347 bcm63xx_irqs = bcm6362_irqs;
350 bcm63xx_regs_base = bcm6368_regs_base;
351 bcm63xx_irqs = bcm6368_irqs;
354 panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
358 bcm63xx_cpu_freq = detect_cpu_clock();
359 bcm63xx_memory_size = detect_memory_size();
361 printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
362 bcm63xx_cpu_id, bcm63xx_cpu_rev);
363 printk(KERN_INFO "CPU frequency is %u MHz\n",
364 bcm63xx_cpu_freq / 1000000);
365 printk(KERN_INFO "%uMB of RAM installed\n",
366 bcm63xx_memory_size >> 20);