2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2007 Cavium Networks
7 * Copyright (C) 2008, 2009 Wind River Systems
8 * written by Ralf Baechle <ralf@linux-mips.org>
10 #include <linux/compiler.h>
11 #include <linux/vmalloc.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/console.h>
15 #include <linux/delay.h>
16 #include <linux/export.h>
17 #include <linux/interrupt.h>
19 #include <linux/serial.h>
20 #include <linux/smp.h>
21 #include <linux/types.h>
22 #include <linux/string.h> /* for memset */
23 #include <linux/tty.h>
24 #include <linux/time.h>
25 #include <linux/platform_device.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial_8250.h>
28 #include <linux/of_fdt.h>
29 #include <linux/libfdt.h>
30 #include <linux/kexec.h>
32 #include <asm/processor.h>
33 #include <asm/reboot.h>
34 #include <asm/smp-ops.h>
35 #include <asm/irq_cpu.h>
36 #include <asm/mipsregs.h>
37 #include <asm/bootinfo.h>
38 #include <asm/sections.h>
41 #include <asm/octeon/octeon.h>
42 #include <asm/octeon/pci-octeon.h>
43 #include <asm/octeon/cvmx-mio-defs.h>
45 extern struct plat_smp_ops octeon_smp_ops;
48 extern void pci_console_init(const char *arg);
51 static unsigned long long MAX_MEMORY = 512ull << 20;
53 struct octeon_boot_descriptor *octeon_boot_desc_ptr;
55 struct cvmx_bootinfo *octeon_bootinfo;
56 EXPORT_SYMBOL(octeon_bootinfo);
58 static unsigned long long RESERVE_LOW_MEM = 0ull;
62 * Wait for relocation code is prepared and send
63 * secondary CPUs to spin until kernel is relocated.
65 static void octeon_kexec_smp_down(void *ignored)
67 int cpu = smp_processor_id();
70 set_cpu_online(cpu, false);
71 while (!atomic_read(&kexec_ready_to_reboot))
78 relocated_kexec_smp_wait(NULL);
82 #define OCTEON_DDR0_BASE (0x0ULL)
83 #define OCTEON_DDR0_SIZE (0x010000000ULL)
84 #define OCTEON_DDR1_BASE (0x410000000ULL)
85 #define OCTEON_DDR1_SIZE (0x010000000ULL)
86 #define OCTEON_DDR2_BASE (0x020000000ULL)
87 #define OCTEON_DDR2_SIZE (0x3e0000000ULL)
88 #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
90 static struct kimage *kimage_ptr;
92 static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes)
95 struct cvmx_bootmem_desc *bootmem_desc;
97 bootmem_desc = cvmx_bootmem_get_desc();
99 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) {
100 mem_size = OCTEON_MAX_PHY_MEM_SIZE;
101 pr_err("Error: requested memory too large,"
102 "truncating to maximum size\n");
105 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
106 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
108 addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes);
109 bootmem_desc->head_addr = 0;
111 if (mem_size <= OCTEON_DDR0_SIZE) {
112 __cvmx_bootmem_phy_free(addr,
113 mem_size - RESERVE_LOW_MEM -
114 low_reserved_bytes, 0);
118 __cvmx_bootmem_phy_free(addr,
119 OCTEON_DDR0_SIZE - RESERVE_LOW_MEM -
120 low_reserved_bytes, 0);
122 mem_size -= OCTEON_DDR0_SIZE;
124 if (mem_size > OCTEON_DDR1_SIZE) {
125 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
126 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
127 mem_size - OCTEON_DDR1_SIZE, 0);
129 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
132 static int octeon_kexec_prepare(struct kimage *image)
135 char *bootloader = "kexec";
137 octeon_boot_desc_ptr->argc = 0;
138 for (i = 0; i < image->nr_segments; i++) {
139 if (!strncmp(bootloader, (char *)image->segment[i].buf,
140 strlen(bootloader))) {
142 * convert command line string to array
143 * of parameters (as bootloader does).
146 char *str = (char *)image->segment[i].buf;
147 char *ptr = strchr(str, ' ');
148 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) {
151 offt = (int)(ptr - str + 1);
152 octeon_boot_desc_ptr->argv[argc] =
153 image->segment[i].mem + offt;
156 ptr = strchr(ptr + 1, ' ');
158 octeon_boot_desc_ptr->argc = argc;
164 * Information about segments will be needed during pre-boot memory
171 static void octeon_generic_shutdown(void)
177 struct cvmx_bootmem_desc *bootmem_desc;
178 void *named_block_array_ptr;
180 bootmem_desc = cvmx_bootmem_get_desc();
181 named_block_array_ptr =
182 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr);
185 /* disable watchdogs */
186 for_each_online_cpu(cpu)
187 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
189 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
191 if (kimage_ptr != kexec_crash_image) {
192 memset(named_block_array_ptr,
194 CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
195 sizeof(struct cvmx_bootmem_named_block_desc));
197 * Mark all memory (except low 0x100000 bytes) as free.
198 * It is the same thing that bootloader does.
200 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL,
203 * Allocate all segments to avoid their corruption during boot.
205 for (i = 0; i < kimage_ptr->nr_segments; i++)
206 cvmx_bootmem_alloc_address(
207 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE,
208 kimage_ptr->segment[i].mem - PAGE_SIZE,
212 * Do not mark all memory as free. Free only named sections
213 * leaving the rest of memory unchanged.
215 struct cvmx_bootmem_named_block_desc *ptr =
216 (struct cvmx_bootmem_named_block_desc *)
217 named_block_array_ptr;
219 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++)
221 cvmx_bootmem_free_named(ptr[i].name);
223 kexec_args[2] = 1UL; /* running on octeon_main_processor */
224 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
226 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */
227 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
231 static void octeon_shutdown(void)
233 octeon_generic_shutdown();
235 smp_call_function(octeon_kexec_smp_down, NULL, 0);
237 while (num_online_cpus() > 1) {
244 static void octeon_crash_shutdown(struct pt_regs *regs)
246 octeon_generic_shutdown();
247 default_machine_crash_shutdown(regs);
250 #endif /* CONFIG_KEXEC */
252 #ifdef CONFIG_CAVIUM_RESERVE32
253 uint64_t octeon_reserve32_memory;
254 EXPORT_SYMBOL(octeon_reserve32_memory);
258 /* crashkernel cmdline parameter is parsed _after_ memory setup
259 * we also parse it here (workaround for EHB5200) */
260 static uint64_t crashk_size, crashk_base;
263 static int octeon_uart;
265 extern asmlinkage void handle_int(void);
268 * Return non zero if we are currently running in the Octeon simulator
272 int octeon_is_simulation(void)
274 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
276 EXPORT_SYMBOL(octeon_is_simulation);
279 * Return true if Octeon is in PCI Host mode. This means
280 * Linux can control the PCI bus.
282 * Returns Non zero if Octeon in host mode.
284 int octeon_is_pci_host(void)
287 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
294 * Get the clock rate of Octeon
296 * Returns Clock rate in HZ
298 uint64_t octeon_get_clock_rate(void)
300 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
302 return sysinfo->cpu_clock_hz;
304 EXPORT_SYMBOL(octeon_get_clock_rate);
306 static u64 octeon_io_clock_rate;
308 u64 octeon_get_io_clock_rate(void)
310 return octeon_io_clock_rate;
312 EXPORT_SYMBOL(octeon_get_io_clock_rate);
316 * Write to the LCD display connected to the bootbus. This display
317 * exists on most Cavium evaluation boards. If it doesn't exist, then
318 * this function doesn't do anything.
320 * @s: String to write
322 void octeon_write_lcd(const char *s)
324 if (octeon_bootinfo->led_display_base_addr) {
325 void __iomem *lcd_address =
326 ioremap_nocache(octeon_bootinfo->led_display_base_addr,
329 for (i = 0; i < 8; i++, s++) {
331 iowrite8(*s, lcd_address + i);
333 iowrite8(' ', lcd_address + i);
335 iounmap(lcd_address);
340 * Return the console uart passed by the bootloader
342 * Returns uart (0 or 1)
344 int octeon_get_boot_uart(void)
347 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
350 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
357 * Get the coremask Linux was booted on.
361 int octeon_get_boot_coremask(void)
363 return octeon_boot_desc_ptr->core_mask;
367 * Check the hardware BIST results for a CPU
369 void octeon_check_cpu_bist(void)
371 const int coreid = cvmx_get_core_num();
372 unsigned long long mask;
373 unsigned long long bist_val;
375 /* Check BIST results for COP0 registers */
376 mask = 0x1f00000000ull;
377 bist_val = read_octeon_c0_icacheerr();
379 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
382 bist_val = read_octeon_c0_dcacheerr();
384 pr_err("Core%d L1 Dcache parity error: "
385 "CacheErr(dcache) = 0x%llx\n",
388 mask = 0xfc00000000000000ull;
389 bist_val = read_c0_cvmmemctl();
391 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
394 write_octeon_c0_dcacheerr(0);
400 * @command: Command to pass to the bootloader. Currently ignored.
402 static void octeon_restart(char *command)
404 /* Disable all watchdogs before soft reset. They don't get cleared */
407 for_each_online_cpu(cpu)
408 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
410 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
415 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
420 * Permanently stop a core.
424 static void octeon_kill_core(void *arg)
426 if (octeon_is_simulation())
427 /* A break instruction causes the simulator stop a core */
428 asm volatile ("break" ::: "memory");
431 /* Disable watchdog on this core. */
432 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
433 /* Spin in a low power mode. */
435 asm volatile ("wait" ::: "memory");
442 static void octeon_halt(void)
444 smp_call_function(octeon_kill_core, NULL, 0);
446 switch (octeon_bootinfo->board_type) {
447 case CVMX_BOARD_TYPE_NAO38:
448 /* Driving a 1 to GPIO 12 shuts off this board */
449 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
450 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
453 octeon_write_lcd("PowerOff");
457 octeon_kill_core(NULL);
460 static char __read_mostly octeon_system_type[80];
462 static int __init init_octeon_system_type(void)
464 snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)",
465 cvmx_board_type_to_string(octeon_bootinfo->board_type),
466 octeon_model_get_string(read_c0_prid()));
470 early_initcall(init_octeon_system_type);
473 * Return a string representing the system type
477 const char *octeon_board_type_string(void)
479 return octeon_system_type;
482 const char *get_system_type(void)
483 __attribute__ ((alias("octeon_board_type_string")));
485 void octeon_user_io_init(void)
487 union octeon_cvmemctl cvmmemctl;
488 union cvmx_iob_fau_timeout fau_timeout;
489 union cvmx_pow_nw_tim nm_tim;
491 /* Get the current settings for CP0_CVMMEMCTL_REG */
492 cvmmemctl.u64 = read_c0_cvmmemctl();
493 /* R/W If set, marked write-buffer entries time out the same
494 * as as other entries; if clear, marked write-buffer entries
495 * use the maximum timeout. */
496 cvmmemctl.s.dismarkwblongto = 1;
497 /* R/W If set, a merged store does not clear the write-buffer
498 * entry timeout state. */
499 cvmmemctl.s.dismrgclrwbto = 0;
500 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
501 * word location for an IOBDMA. The other 8 bits come from the
502 * SCRADDR field of the IOBDMA. */
503 cvmmemctl.s.iobdmascrmsb = 0;
504 /* R/W If set, SYNCWS and SYNCS only order marked stores; if
505 * clear, SYNCWS and SYNCS only order unmarked
506 * stores. SYNCWSMARKED has no effect when DISSYNCWS is
508 cvmmemctl.s.syncwsmarked = 0;
509 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
510 cvmmemctl.s.dissyncws = 0;
511 /* R/W If set, no stall happens on write buffer full. */
512 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
513 cvmmemctl.s.diswbfst = 1;
515 cvmmemctl.s.diswbfst = 0;
516 /* R/W If set (and SX set), supervisor-level loads/stores can
517 * use XKPHYS addresses with <48>==0 */
518 cvmmemctl.s.xkmemenas = 0;
520 /* R/W If set (and UX set), user-level loads/stores can use
521 * XKPHYS addresses with VA<48>==0 */
522 cvmmemctl.s.xkmemenau = 0;
524 /* R/W If set (and SX set), supervisor-level loads/stores can
525 * use XKPHYS addresses with VA<48>==1 */
526 cvmmemctl.s.xkioenas = 0;
528 /* R/W If set (and UX set), user-level loads/stores can use
529 * XKPHYS addresses with VA<48>==1 */
530 cvmmemctl.s.xkioenau = 0;
532 /* R/W If set, all stores act as SYNCW (NOMERGE must be set
533 * when this is set) RW, reset to 0. */
534 cvmmemctl.s.allsyncw = 0;
536 /* R/W If set, no stores merge, and all stores reach the
537 * coherent bus in order. */
538 cvmmemctl.s.nomerge = 0;
539 /* R/W Selects the bit in the counter used for DID time-outs 0
540 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
541 * between 1x and 2x this interval. For example, with
542 * DIDTTO=3, expiration interval is between 16K and 32K. */
543 cvmmemctl.s.didtto = 0;
544 /* R/W If set, the (mem) CSR clock never turns off. */
545 cvmmemctl.s.csrckalwys = 0;
546 /* R/W If set, mclk never turns off. */
547 cvmmemctl.s.mclkalwys = 0;
548 /* R/W Selects the bit in the counter used for write buffer
549 * flush time-outs (WBFLT+11) is the bit position in an
550 * internal counter used to determine expiration. The write
551 * buffer expires between 1x and 2x this interval. For
552 * example, with WBFLT = 0, a write buffer expires between 2K
553 * and 4K cycles after the write buffer entry is allocated. */
554 cvmmemctl.s.wbfltime = 0;
555 /* R/W If set, do not put Istream in the L2 cache. */
556 cvmmemctl.s.istrnol2 = 0;
559 * R/W The write buffer threshold. As per erratum Core-14752
560 * for CN63XX, a sc/scd might fail if the write buffer is
561 * full. Lowering WBTHRESH greatly lowers the chances of the
562 * write buffer ever being full and triggering the erratum.
564 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
565 cvmmemctl.s.wbthresh = 4;
567 cvmmemctl.s.wbthresh = 10;
569 /* R/W If set, CVMSEG is available for loads/stores in
570 * kernel/debug mode. */
571 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
572 cvmmemctl.s.cvmsegenak = 1;
574 cvmmemctl.s.cvmsegenak = 0;
576 /* R/W If set, CVMSEG is available for loads/stores in
577 * supervisor mode. */
578 cvmmemctl.s.cvmsegenas = 0;
579 /* R/W If set, CVMSEG is available for loads/stores in user
581 cvmmemctl.s.cvmsegenau = 0;
582 /* R/W Size of local memory in cache blocks, 54 (6912 bytes)
583 * is max legal value. */
584 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
586 write_c0_cvmmemctl(cvmmemctl.u64);
588 if (smp_processor_id() == 0)
589 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
590 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
591 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
593 /* Set a default for the hardware timeouts */
595 fau_timeout.s.tout_val = 0xfff;
596 /* Disable tagwait FAU timeout */
597 fau_timeout.s.tout_enb = 0;
598 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
603 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
605 write_octeon_c0_icacheerr(0);
606 write_c0_derraddr1(0);
610 * Early entry point for arch setup
612 void __init prom_init(void)
614 struct cvmx_sysinfo *sysinfo;
619 #ifdef CONFIG_CAVIUM_RESERVE32
623 * The bootloader passes a pointer to the boot descriptor in
624 * $a3, this is available as fw_arg3.
626 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
628 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
629 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
631 sysinfo = cvmx_sysinfo_get();
632 memset(sysinfo, 0, sizeof(*sysinfo));
633 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
634 sysinfo->phy_mem_desc_ptr =
635 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
636 sysinfo->core_mask = octeon_bootinfo->core_mask;
637 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
638 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
639 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
640 sysinfo->board_type = octeon_bootinfo->board_type;
641 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
642 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
643 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
644 sizeof(sysinfo->mac_addr_base));
645 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
646 memcpy(sysinfo->board_serial_number,
647 octeon_bootinfo->board_serial_number,
648 sizeof(sysinfo->board_serial_number));
649 sysinfo->compact_flash_common_base_addr =
650 octeon_bootinfo->compact_flash_common_base_addr;
651 sysinfo->compact_flash_attribute_base_addr =
652 octeon_bootinfo->compact_flash_attribute_base_addr;
653 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
654 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
655 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
657 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
658 /* I/O clock runs at a different rate than the CPU. */
659 union cvmx_mio_rst_boot rst_boot;
660 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
661 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
663 octeon_io_clock_rate = sysinfo->cpu_clock_hz;
667 * Only enable the LED controller if we're running on a CN38XX, CN58XX,
668 * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
670 if (!octeon_is_simulation() &&
671 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
672 cvmx_write_csr(CVMX_LED_EN, 0);
673 cvmx_write_csr(CVMX_LED_PRT, 0);
674 cvmx_write_csr(CVMX_LED_DBG, 0);
675 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
676 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
677 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
678 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
679 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
680 cvmx_write_csr(CVMX_LED_EN, 1);
682 #ifdef CONFIG_CAVIUM_RESERVE32
684 * We need to temporarily allocate all memory in the reserve32
685 * region. This makes sure the kernel doesn't allocate this
686 * memory when it is getting memory from the
687 * bootloader. Later, after the memory allocations are
688 * complete, the reserve32 will be freed.
690 * Allocate memory for RESERVED32 aligned on 2MB boundary. This
691 * is in case we later use hugetlb entries with it.
693 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
695 "CAVIUM_RESERVE32", 0);
697 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
699 octeon_reserve32_memory = addr;
702 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
703 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
704 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
706 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
707 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
709 cvmx_l2c_lock_mem_region(ebase, 0x100);
711 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
712 /* General exception */
713 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
715 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
716 /* Interrupt handler */
717 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
719 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
720 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
721 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
723 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
724 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
729 octeon_check_cpu_bist();
731 octeon_uart = octeon_get_boot_uart();
734 octeon_write_lcd("LinuxSMP");
736 octeon_write_lcd("Linux");
739 octeon_setup_delays();
742 * BIST should always be enabled when doing a soft reset. L2
743 * Cache locking for instance is not cleared unless BIST is
744 * enabled. Unfortunately due to a chip errata G-200 for
745 * Cn38XX and CN31XX, BIST msut be disabled on these parts.
747 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
748 OCTEON_IS_MODEL(OCTEON_CN31XX))
749 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
751 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
753 /* Default to 64MB in the simulator to speed things up */
754 if (octeon_is_simulation())
755 MAX_MEMORY = 64ull << 20;
757 arg = strstr(arcs_cmdline, "mem=");
759 MAX_MEMORY = memparse(arg + 4, &p);
761 MAX_MEMORY = 32ull << 30;
763 RESERVE_LOW_MEM = memparse(p + 1, &p);
767 argc = octeon_boot_desc_ptr->argc;
768 for (i = 0; i < argc; i++) {
770 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
771 if ((strncmp(arg, "MEM=", 4) == 0) ||
772 (strncmp(arg, "mem=", 4) == 0)) {
773 MAX_MEMORY = memparse(arg + 4, &p);
775 MAX_MEMORY = 32ull << 30;
777 RESERVE_LOW_MEM = memparse(p + 1, &p);
779 } else if (strncmp(arg, "crashkernel=", 12) == 0) {
780 crashk_size = memparse(arg+12, &p);
782 crashk_base = memparse(p+1, &p);
783 strcat(arcs_cmdline, " ");
784 strcat(arcs_cmdline, arg);
786 * To do: switch parsing to new style, something like:
787 * parse_crashkernel(arg, sysinfo->system_dram_size,
788 * &crashk_size, &crashk_base);
791 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
792 sizeof(arcs_cmdline) - 1) {
793 strcat(arcs_cmdline, " ");
794 strcat(arcs_cmdline, arg);
798 if (strstr(arcs_cmdline, "console=") == NULL) {
799 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
800 strcat(arcs_cmdline, " console=ttyS0,115200");
802 if (octeon_uart == 1)
803 strcat(arcs_cmdline, " console=ttyS1,115200");
805 strcat(arcs_cmdline, " console=ttyS0,115200");
809 mips_hpt_frequency = octeon_get_clock_rate();
811 octeon_init_cvmcount();
813 _machine_restart = octeon_restart;
814 _machine_halt = octeon_halt;
817 _machine_kexec_shutdown = octeon_shutdown;
818 _machine_crash_shutdown = octeon_crash_shutdown;
819 _machine_kexec_prepare = octeon_kexec_prepare;
822 octeon_user_io_init();
823 register_smp_ops(&octeon_smp_ops);
826 /* Exclude a single page from the regions obtained in plat_mem_setup. */
827 #ifndef CONFIG_CRASH_DUMP
828 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
830 if (addr > *mem && addr < *mem + *size) {
831 u64 inc = addr - *mem;
832 add_memory_region(*mem, inc, BOOT_MEM_RAM);
837 if (addr == *mem && *size > PAGE_SIZE) {
842 #endif /* CONFIG_CRASH_DUMP */
844 void __init plat_mem_setup(void)
846 uint64_t mem_alloc_size;
849 #ifndef CONFIG_CRASH_DUMP
851 uint64_t kernel_start;
852 uint64_t kernel_size;
859 * The Mips memory init uses the first memory location for
860 * some memory vectors. When SPARSEMEM is in use, it doesn't
861 * verify that the size is big enough for the final
862 * vectors. Making the smallest chuck 4MB seems to be enough
863 * to consistently work.
865 mem_alloc_size = 4 << 20;
866 if (mem_alloc_size > MAX_MEMORY)
867 mem_alloc_size = MAX_MEMORY;
869 /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */
870 #ifdef CONFIG_CRASH_DUMP
871 add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM);
875 if (crashk_size > 0) {
876 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM);
877 crashk_end = crashk_base + crashk_size;
881 * When allocating memory, we want incrementing addresses from
882 * bootmem_alloc so the code in add_memory_region can merge
883 * regions next to each other.
886 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
887 && (total < MAX_MEMORY)) {
888 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
889 __pa_symbol(&__init_end), -1,
891 CVMX_BOOTMEM_FLAG_NO_LOCKING);
893 u64 size = mem_alloc_size;
899 * exclude a page at the beginning and end of
900 * the 256MB PCIe 'hole' so the kernel will not
901 * try to allocate multi-page buffers that
902 * span the discontinuity.
904 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
906 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
907 CVMX_PCIE_BAR1_PHYS_SIZE,
910 end = memory + mem_alloc_size;
913 * This function automatically merges address regions
914 * next to each other if they are received in
917 if (memory < crashk_base && end > crashk_end) {
918 /* region is fully in */
919 add_memory_region(memory,
920 crashk_base - memory,
922 total += crashk_base - memory;
923 add_memory_region(crashk_end,
926 total += end - crashk_end;
930 if (memory >= crashk_base && end <= crashk_end)
932 * Entire memory region is within the new
933 * kernel's memory, ignore it.
937 if (memory > crashk_base && memory < crashk_end &&
940 * Overlap with the beginning of the region,
941 * reserve the beginning.
943 mem_alloc_size -= crashk_end - memory;
945 } else if (memory < crashk_base && end > crashk_base &&
948 * Overlap with the beginning of the region,
951 mem_alloc_size -= end - crashk_base;
953 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
954 total += mem_alloc_size;
955 /* Recovering mem_alloc_size */
956 mem_alloc_size = 4 << 20;
961 cvmx_bootmem_unlock();
962 /* Add the memory region for the kernel. */
963 kernel_start = (unsigned long) _text;
964 kernel_size = _end - _text;
966 /* Adjust for physical offset. */
967 kernel_start &= ~0xffffffff80000000ULL;
968 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM);
969 #endif /* CONFIG_CRASH_DUMP */
971 #ifdef CONFIG_CAVIUM_RESERVE32
973 * Now that we've allocated the kernel memory it is safe to
974 * free the reserved region. We free it here so that builtin
975 * drivers can use the memory.
977 if (octeon_reserve32_memory)
978 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
979 #endif /* CONFIG_CAVIUM_RESERVE32 */
982 panic("Unable to allocate memory from "
983 "cvmx_bootmem_phy_alloc");
987 * Emit one character to the boot UART. Exported for use by the
990 int prom_putchar(char c)
994 /* Spin until there is room */
996 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
997 } while ((lsrval & 0x20) == 0);
1000 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
1003 EXPORT_SYMBOL(prom_putchar);
1005 void prom_free_prom_memory(void)
1007 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
1008 /* Check for presence of Core-14449 fix. */
1014 asm volatile("# before" : : : "memory");
1018 ".set noreorder\n\t"
1021 "1:\tlw %0,-12($31)\n\t"
1023 : "=r" (insn) : : "$31", "memory");
1025 if ((insn >> 26) != 0x33)
1026 panic("No PREF instruction at Core-14449 probe point.");
1028 if (((insn >> 16) & 0x1f) != 28)
1029 panic("Core-14449 WAR not in place (%04x).\n"
1030 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
1034 int octeon_prune_device_tree(void);
1036 extern const char __dtb_octeon_3xxx_begin;
1037 extern const char __dtb_octeon_68xx_begin;
1038 void __init device_tree_init(void)
1043 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
1044 fdt = phys_to_virt(octeon_bootinfo->fdt_addr);
1045 if (fdt_check_header(fdt))
1046 panic("Corrupt Device Tree passed to kernel.");
1048 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
1049 fdt = &__dtb_octeon_68xx_begin;
1052 fdt = &__dtb_octeon_3xxx_begin;
1056 initial_boot_params = (void *)fdt;
1059 octeon_prune_device_tree();
1060 pr_info("Using internal Device Tree.\n");
1062 pr_info("Using passed Device Tree.\n");
1064 unflatten_and_copy_device_tree();
1067 static int __initdata disable_octeon_edac_p;
1069 static int __init disable_octeon_edac(char *str)
1071 disable_octeon_edac_p = 1;
1074 early_param("disable_octeon_edac", disable_octeon_edac);
1076 static char *edac_device_names[] = {
1081 static int __init edac_devinit(void)
1083 struct platform_device *dev;
1088 if (disable_octeon_edac_p)
1091 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) {
1092 name = edac_device_names[i];
1093 dev = platform_device_register_simple(name, -1, NULL, 0);
1095 pr_err("Registation of %s failed!\n", name);
1100 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 :
1101 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1);
1102 for (i = 0; i < num_lmc; i++) {
1103 dev = platform_device_register_simple("octeon_lmc_edac",
1106 pr_err("Registation of octeon_lmc_edac %d failed!\n", i);
1113 device_initcall(edac_devinit);
1115 static void __initdata *octeon_dummy_iospace;
1117 static int __init octeon_no_pci_init(void)
1120 * Initially assume there is no PCI. The PCI/PCIe platform code will
1121 * later re-initialize these to correct values if they are present.
1123 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT);
1124 set_io_port_base((unsigned long)octeon_dummy_iospace);
1125 ioport_resource.start = MAX_RESOURCE;
1126 ioport_resource.end = 0;
1129 core_initcall(octeon_no_pci_init);
1131 static int __init octeon_no_pci_release(void)
1134 * Release the allocated memory if a real IO space is there.
1136 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base)
1137 vfree(octeon_dummy_iospace);
1140 late_initcall(octeon_no_pci_release);