2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
9 #include <linux/delay.h>
10 #include <linux/smp.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/sched.h>
14 #include <linux/module.h>
16 #include <asm/mmu_context.h>
18 #include <asm/setup.h>
20 #include <asm/octeon/octeon.h>
22 #include "octeon_boot.h"
24 volatile unsigned long octeon_processor_boot = 0xff;
25 volatile unsigned long octeon_processor_sp;
26 volatile unsigned long octeon_processor_gp;
28 #ifdef CONFIG_HOTPLUG_CPU
29 uint64_t octeon_bootloader_entry_addr;
30 EXPORT_SYMBOL(octeon_bootloader_entry_addr);
33 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
35 const int coreid = cvmx_get_core_num();
38 /* Load the mailbox register to figure out what we're supposed to do */
39 action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;
41 /* Clear the mailbox to clear the interrupt */
42 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
44 if (action & SMP_CALL_FUNCTION)
45 smp_call_function_interrupt();
46 if (action & SMP_RESCHEDULE_YOURSELF)
49 /* Check if we've been told to flush the icache */
50 if (action & SMP_ICACHE_FLUSH)
51 asm volatile ("synci 0($0)\n");
56 * Cause the function described by call_data to be executed on the passed
57 * cpu. When the function has finished, increment the finished field of
60 void octeon_send_ipi_single(int cpu, unsigned int action)
62 int coreid = cpu_logical_map(cpu);
64 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
67 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
70 static inline void octeon_send_ipi_mask(const struct cpumask *mask,
75 for_each_cpu_mask(i, *mask)
76 octeon_send_ipi_single(i, action);
80 * Detect available CPUs, populate cpu_possible_mask
82 static void octeon_smp_hotplug_setup(void)
84 #ifdef CONFIG_HOTPLUG_CPU
85 struct linux_app_boot_info *labi;
87 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
88 if (labi->labi_signature != LABI_SIGNATURE)
89 panic("The bootloader version on this board is incorrect.");
91 octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
95 static void octeon_smp_setup(void)
97 const int coreid = cvmx_get_core_num();
100 int core_mask = octeon_get_boot_coremask();
101 #ifdef CONFIG_HOTPLUG_CPU
102 unsigned int num_cores = cvmx_octeon_num_cores();
105 /* The present CPUs are initially just the boot cpu (CPU 0). */
106 for (id = 0; id < NR_CPUS; id++) {
107 set_cpu_possible(id, id == 0);
108 set_cpu_present(id, id == 0);
111 __cpu_number_map[coreid] = 0;
112 __cpu_logical_map[0] = coreid;
114 /* The present CPUs get the lowest CPU numbers. */
116 for (id = 0; id < NR_CPUS; id++) {
117 if ((id != coreid) && (core_mask & (1 << id))) {
118 set_cpu_possible(cpus, true);
119 set_cpu_present(cpus, true);
120 __cpu_number_map[id] = cpus;
121 __cpu_logical_map[cpus] = id;
126 #ifdef CONFIG_HOTPLUG_CPU
128 * The possible CPUs are all those present on the chip. We
129 * will assign CPU numbers for possible cores as well. Cores
130 * are always consecutively numberd from 0.
132 for (id = 0; id < num_cores && id < NR_CPUS; id++) {
133 if (!(core_mask & (1 << id))) {
134 set_cpu_possible(cpus, true);
135 __cpu_number_map[id] = cpus;
136 __cpu_logical_map[cpus] = id;
142 octeon_smp_hotplug_setup();
146 * Firmware CPU startup hook
149 static void octeon_boot_secondary(int cpu, struct task_struct *idle)
153 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
154 cpu_logical_map(cpu));
156 octeon_processor_sp = __KSTK_TOS(idle);
157 octeon_processor_gp = (unsigned long)(task_thread_info(idle));
158 octeon_processor_boot = cpu_logical_map(cpu);
162 while (octeon_processor_sp && count) {
163 /* Waiting for processor to get the SP and GP */
168 pr_err("Secondary boot timeout\n");
172 * After we've done initial boot, this function is called to allow the
173 * board code to clean up state, if needed
175 static void octeon_init_secondary(void)
179 sr = set_c0_status(ST0_BEV);
180 write_c0_ebase((u32)ebase);
183 octeon_check_cpu_bist();
184 octeon_init_cvmcount();
186 octeon_irq_setup_secondary();
190 * Callout to firmware before smp_init
193 void octeon_prepare_cpus(unsigned int max_cpus)
195 #ifdef CONFIG_HOTPLUG_CPU
196 struct linux_app_boot_info *labi;
198 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
200 if (labi->labi_signature != LABI_SIGNATURE)
201 panic("The bootloader version on this board is incorrect.");
204 * Only the low order mailbox bits are used for IPIs, leave
205 * the other bits alone.
207 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
208 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
209 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
210 mailbox_interrupt)) {
211 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
216 * Last chance for the board code to finish SMP initialization before
217 * the CPU is "online".
219 static void octeon_smp_finish(void)
221 #ifdef CONFIG_CAVIUM_GDB
223 /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
224 to be not masked by this core so we know the signal is received by
226 asm volatile ("dmfc0 %0, $22\n"
227 "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
230 octeon_user_io_init();
232 /* to generate the first CPU timer interrupt */
233 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
238 * Hook for after all CPUs are online
240 static void octeon_cpus_done(void)
242 #ifdef CONFIG_CAVIUM_GDB
244 /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
245 to be not masked by this core so we know the signal is received by
247 asm volatile ("dmfc0 %0, $22\n"
248 "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
252 #ifdef CONFIG_HOTPLUG_CPU
254 /* State of each CPU. */
255 DEFINE_PER_CPU(int, cpu_state);
257 static int octeon_cpu_disable(void)
259 unsigned int cpu = smp_processor_id();
264 set_cpu_online(cpu, false);
265 cpu_clear(cpu, cpu_callin_map);
271 local_flush_tlb_all();
276 static void octeon_cpu_die(unsigned int cpu)
278 int coreid = cpu_logical_map(cpu);
279 uint32_t mask, new_mask;
280 const struct cvmx_bootmem_named_block_desc *block_desc;
282 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
286 * This is a bit complicated strategics of getting/settig available
287 * cores mask, copied from bootloader
291 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
292 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
295 struct linux_app_boot_info *labi;
297 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
299 labi->avail_coremask |= mask;
300 new_mask = labi->avail_coremask;
301 } else { /* alternative, already initialized */
302 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
303 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
308 pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
310 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
311 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
316 int cpu = cpu_number_map(cvmx_get_core_num());
319 octeon_processor_boot = 0xff;
320 per_cpu(cpu_state, cpu) = CPU_DEAD;
324 while (1) /* core will be reset here */
328 extern void kernel_entry(unsigned long arg1, ...);
330 static void start_after_reset(void)
332 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
335 static int octeon_update_boot_vector(unsigned int cpu)
338 int coreid = cpu_logical_map(cpu);
339 uint32_t avail_coremask;
340 const struct cvmx_bootmem_named_block_desc *block_desc;
341 struct boot_init_vector *boot_vect =
342 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
344 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
347 struct linux_app_boot_info *labi;
349 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
351 avail_coremask = labi->avail_coremask;
352 labi->avail_coremask &= ~(1 << coreid);
353 } else { /* alternative, already initialized */
354 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
355 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
358 if (!(avail_coremask & (1 << coreid))) {
359 /* core not available, assume, that catched by simple-executive */
360 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
361 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
364 boot_vect[coreid].app_start_func_addr =
365 (uint32_t) (unsigned long) start_after_reset;
366 boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
370 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
375 static int octeon_cpu_callback(struct notifier_block *nfb,
376 unsigned long action, void *hcpu)
378 unsigned int cpu = (unsigned long)hcpu;
382 octeon_update_boot_vector(cpu);
385 pr_info("Cpu %d online\n", cpu);
394 static int register_cavium_notifier(void)
396 hotcpu_notifier(octeon_cpu_callback, 0);
399 late_initcall(register_cavium_notifier);
401 #endif /* CONFIG_HOTPLUG_CPU */
403 struct plat_smp_ops octeon_smp_ops = {
404 .send_ipi_single = octeon_send_ipi_single,
405 .send_ipi_mask = octeon_send_ipi_mask,
406 .init_secondary = octeon_init_secondary,
407 .smp_finish = octeon_smp_finish,
408 .cpus_done = octeon_cpus_done,
409 .boot_secondary = octeon_boot_secondary,
410 .smp_setup = octeon_smp_setup,
411 .prepare_cpus = octeon_prepare_cpus,
412 #ifdef CONFIG_HOTPLUG_CPU
413 .cpu_disable = octeon_cpu_disable,
414 .cpu_die = octeon_cpu_die,