2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) MIPS Technologies, Inc.
8 * written by Ralf Baechle <ralf@linux-mips.org>
10 #ifndef _ASM_HAZARDS_H
11 #define _ASM_HAZARDS_H
14 #define ASMMACRO(name, code...) .macro name; code; .endm
17 #include <asm/cpu-features.h>
19 #define ASMMACRO(name, code...) \
20 __asm__(".macro " #name "; " #code "; .endm"); \
22 static inline void name(void) \
24 __asm__ __volatile__ (#name); \
28 * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
30 extern void mips_ihb(void);
45 #if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
48 * MIPSR2 defines ehb for hazard avoidance
51 ASMMACRO(mtc0_tlbw_hazard,
54 ASMMACRO(tlbw_use_hazard,
57 ASMMACRO(tlb_probe_hazard,
60 ASMMACRO(irq_enable_hazard,
63 ASMMACRO(irq_disable_hazard,
66 ASMMACRO(back_to_back_c0_hazard,
70 * gcc has a tradition of misscompiling the previous construct using the
71 * address of a label as argument to inline assembler. Gas otoh has the
72 * annoying difference between la and dla which are only usable for 32-bit
73 * rsp. 64-bit code, so can't be used without conditional compilation.
74 * The alterantive is switching the assembler to 64-bit code which happens
75 * to work right even for 32-bit code ...
77 #define instruction_hazard() \
81 __asm__ __volatile__( \
90 #elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
91 defined(CONFIG_CPU_BMIPS)
94 * These are slightly complicated by the fact that we guarantee R1 kernels to
95 * run fine on R2 processors.
97 ASMMACRO(mtc0_tlbw_hazard,
100 ASMMACRO(tlbw_use_hazard,
101 _ssnop; _ssnop; _ssnop; _ehb
103 ASMMACRO(tlb_probe_hazard,
104 _ssnop; _ssnop; _ssnop; _ehb
106 ASMMACRO(irq_enable_hazard,
107 _ssnop; _ssnop; _ssnop; _ehb
109 ASMMACRO(irq_disable_hazard,
110 _ssnop; _ssnop; _ssnop; _ehb
112 ASMMACRO(back_to_back_c0_hazard,
113 _ssnop; _ssnop; _ssnop; _ehb
116 * gcc has a tradition of misscompiling the previous construct using the
117 * address of a label as argument to inline assembler. Gas otoh has the
118 * annoying difference between la and dla which are only usable for 32-bit
119 * rsp. 64-bit code, so can't be used without conditional compilation.
120 * The alterantive is switching the assembler to 64-bit code which happens
121 * to work right even for 32-bit code ...
123 #define __instruction_hazard() \
127 __asm__ __volatile__( \
128 " .set mips64r2 \n" \
136 #define instruction_hazard() \
138 if (cpu_has_mips_r2) \
139 __instruction_hazard(); \
142 #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
143 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
144 defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
147 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
150 ASMMACRO(mtc0_tlbw_hazard,
152 ASMMACRO(tlbw_use_hazard,
154 ASMMACRO(tlb_probe_hazard,
156 ASMMACRO(irq_enable_hazard,
158 ASMMACRO(irq_disable_hazard,
160 ASMMACRO(back_to_back_c0_hazard,
162 #define instruction_hazard() do { } while (0)
164 #elif defined(CONFIG_CPU_SB1)
167 * Mostly like R4000 for historic reasons
169 ASMMACRO(mtc0_tlbw_hazard,
171 ASMMACRO(tlbw_use_hazard,
173 ASMMACRO(tlb_probe_hazard,
175 ASMMACRO(irq_enable_hazard,
177 ASMMACRO(irq_disable_hazard,
178 _ssnop; _ssnop; _ssnop
180 ASMMACRO(back_to_back_c0_hazard,
182 #define instruction_hazard() do { } while (0)
187 * Finally the catchall case for all other processors including R4000, R4400,
188 * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
190 * The taken branch will result in a two cycle penalty for the two killed
191 * instructions on R4000 / R4400. Other processors only have a single cycle
192 * hazard so this is nice trick to have an optimal code for a range of
195 ASMMACRO(mtc0_tlbw_hazard,
198 ASMMACRO(tlbw_use_hazard,
201 ASMMACRO(tlb_probe_hazard,
204 ASMMACRO(irq_enable_hazard,
205 _ssnop; _ssnop; _ssnop;
207 ASMMACRO(irq_disable_hazard,
210 ASMMACRO(back_to_back_c0_hazard,
211 _ssnop; _ssnop; _ssnop;
213 #define instruction_hazard() do { } while (0)
220 #if defined(CONFIG_CPU_SB1)
221 ASMMACRO(enable_fpu_hazard,
230 ASMMACRO(disable_fpu_hazard,
233 #elif defined(CONFIG_CPU_MIPSR2)
234 ASMMACRO(enable_fpu_hazard,
237 ASMMACRO(disable_fpu_hazard,
241 ASMMACRO(enable_fpu_hazard,
244 ASMMACRO(disable_fpu_hazard,
249 #endif /* _ASM_HAZARDS_H */