arch/mips/include/asm/kvm_host.h

   1 /*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
   8 */
   9
  10 #ifndef __MIPS_KVM_HOST_H__
  11 #define __MIPS_KVM_HOST_H__
  12
  13 #include <linux/mutex.h>
  14 #include <linux/hrtimer.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/types.h>
  17 #include <linux/kvm.h>
  18 #include <linux/kvm_types.h>
  19 #include <linux/threads.h>
  20 #include <linux/spinlock.h>
  21
  22 /* MIPS KVM register ids */
  23 #define MIPS_CP0_32(_R, _S)                                     \
  24         (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
  25
  26 #define MIPS_CP0_64(_R, _S)                                     \
  27         (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
  28
  29 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
  30 #define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
  31 #define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
  32 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
  33 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
  34 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
  35 #define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
  36 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
  37 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
  38 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
  39 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
  40 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
  41 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
  42 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
  43 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
  44 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
  45 #define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
  46 #define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
  47 #define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
  48 #define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
  49 #define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
  50 #define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
  51 #define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
  52 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
  53
  54
  55 #define KVM_MAX_VCPUS           1
  56 #define KVM_USER_MEM_SLOTS      8
  57 /* memory slots that does not exposed to userspace */
  58 #define KVM_PRIVATE_MEM_SLOTS   0
  59
  60 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  61
  62
  63
  64 /* Special address that contains the comm page, used for reducing # of traps */
  65 #define KVM_GUEST_COMMPAGE_ADDR         0x0
  66
  67 #define KVM_GUEST_KERNEL_MODE(vcpu)     ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
  68                                         ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
  69
  70 #define KVM_GUEST_KUSEG                 0x00000000UL
  71 #define KVM_GUEST_KSEG0                 0x40000000UL
  72 #define KVM_GUEST_KSEG23                0x60000000UL
  73 #define KVM_GUEST_KSEGX(a)              ((_ACAST32_(a)) & 0x60000000)
  74 #define KVM_GUEST_CPHYSADDR(a)          ((_ACAST32_(a)) & 0x1fffffff)
  75
  76 #define KVM_GUEST_CKSEG0ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  77 #define KVM_GUEST_CKSEG1ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  78 #define KVM_GUEST_CKSEG23ADDR(a)        (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  79
  80 /*
  81  * Map an address to a certain kernel segment
  82  */
  83 #define KVM_GUEST_KSEG0ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  84 #define KVM_GUEST_KSEG1ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  85 #define KVM_GUEST_KSEG23ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  86
  87 #define KVM_INVALID_PAGE                0xdeadbeef
  88 #define KVM_INVALID_INST                0xdeadbeef
  89 #define KVM_INVALID_ADDR                0xdeadbeef
  90
  91 #define KVM_MALTA_GUEST_RTC_ADDR        0xb8000070UL
  92
  93 #define GUEST_TICKS_PER_JIFFY           (40000000/HZ)
  94 #define MS_TO_NS(x)                     (x * 1E6L)
  95
  96 #define CAUSEB_DC                       27
  97 #define CAUSEF_DC                       (_ULCAST_(1) << 27)
  98
  99 struct kvm;
 100 struct kvm_run;
 101 struct kvm_vcpu;
 102 struct kvm_interrupt;
 103
 104 extern atomic_t kvm_mips_instance;
 105 extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
 106 extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
 107 extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
 108
 109 struct kvm_vm_stat {
 110         u32 remote_tlb_flush;
 111 };
 112
 113 struct kvm_vcpu_stat {
 114         u32 wait_exits;
 115         u32 cache_exits;
 116         u32 signal_exits;
 117         u32 int_exits;
 118         u32 cop_unusable_exits;
 119         u32 tlbmod_exits;
 120         u32 tlbmiss_ld_exits;
 121         u32 tlbmiss_st_exits;
 122         u32 addrerr_st_exits;
 123         u32 addrerr_ld_exits;
 124         u32 syscall_exits;
 125         u32 resvd_inst_exits;
 126         u32 break_inst_exits;
 127         u32 flush_dcache_exits;
 128         u32 halt_wakeup;
 129 };
 130
 131 enum kvm_mips_exit_types {
 132         WAIT_EXITS,
 133         CACHE_EXITS,
 134         SIGNAL_EXITS,
 135         INT_EXITS,
 136         COP_UNUSABLE_EXITS,
 137         TLBMOD_EXITS,
 138         TLBMISS_LD_EXITS,
 139         TLBMISS_ST_EXITS,
 140         ADDRERR_ST_EXITS,
 141         ADDRERR_LD_EXITS,
 142         SYSCALL_EXITS,
 143         RESVD_INST_EXITS,
 144         BREAK_INST_EXITS,
 145         FLUSH_DCACHE_EXITS,
 146         MAX_KVM_MIPS_EXIT_TYPES
 147 };
 148
 149 struct kvm_arch_memory_slot {
 150 };
 151
 152 struct kvm_arch {
 153         /* Guest GVA->HPA page table */
 154         unsigned long *guest_pmap;
 155         unsigned long guest_pmap_npages;
 156
 157         /* Wired host TLB used for the commpage */
 158         int commpage_tlb;
 159 };
 160
 161 #define N_MIPS_COPROC_REGS      32
 162 #define N_MIPS_COPROC_SEL       8
 163
 164 struct mips_coproc {
 165         unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 166 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 167         unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 168 #endif
 169 };
 170
 171 /*
 172  * Coprocessor 0 register names
 173  */
 174 #define MIPS_CP0_TLB_INDEX      0
 175 #define MIPS_CP0_TLB_RANDOM     1
 176 #define MIPS_CP0_TLB_LOW        2
 177 #define MIPS_CP0_TLB_LO0        2
 178 #define MIPS_CP0_TLB_LO1        3
 179 #define MIPS_CP0_TLB_CONTEXT    4
 180 #define MIPS_CP0_TLB_PG_MASK    5
 181 #define MIPS_CP0_TLB_WIRED      6
 182 #define MIPS_CP0_HWRENA         7
 183 #define MIPS_CP0_BAD_VADDR      8
 184 #define MIPS_CP0_COUNT          9
 185 #define MIPS_CP0_TLB_HI         10
 186 #define MIPS_CP0_COMPARE        11
 187 #define MIPS_CP0_STATUS         12
 188 #define MIPS_CP0_CAUSE          13
 189 #define MIPS_CP0_EXC_PC         14
 190 #define MIPS_CP0_PRID           15
 191 #define MIPS_CP0_CONFIG         16
 192 #define MIPS_CP0_LLADDR         17
 193 #define MIPS_CP0_WATCH_LO       18
 194 #define MIPS_CP0_WATCH_HI       19
 195 #define MIPS_CP0_TLB_XCONTEXT   20
 196 #define MIPS_CP0_ECC            26
 197 #define MIPS_CP0_CACHE_ERR      27
 198 #define MIPS_CP0_TAG_LO         28
 199 #define MIPS_CP0_TAG_HI         29
 200 #define MIPS_CP0_ERROR_PC       30
 201 #define MIPS_CP0_DEBUG          23
 202 #define MIPS_CP0_DEPC           24
 203 #define MIPS_CP0_PERFCNT        25
 204 #define MIPS_CP0_ERRCTL         26
 205 #define MIPS_CP0_DATA_LO        28
 206 #define MIPS_CP0_DATA_HI        29
 207 #define MIPS_CP0_DESAVE         31
 208
 209 #define MIPS_CP0_CONFIG_SEL     0
 210 #define MIPS_CP0_CONFIG1_SEL    1
 211 #define MIPS_CP0_CONFIG2_SEL    2
 212 #define MIPS_CP0_CONFIG3_SEL    3
 213
 214 /* Config0 register bits */
 215 #define CP0C0_M                 31
 216 #define CP0C0_K23               28
 217 #define CP0C0_KU                25
 218 #define CP0C0_MDU               20
 219 #define CP0C0_MM                17
 220 #define CP0C0_BM                16
 221 #define CP0C0_BE                15
 222 #define CP0C0_AT                13
 223 #define CP0C0_AR                10
 224 #define CP0C0_MT                7
 225 #define CP0C0_VI                3
 226 #define CP0C0_K0                0
 227
 228 /* Config1 register bits */
 229 #define CP0C1_M                 31
 230 #define CP0C1_MMU               25
 231 #define CP0C1_IS                22
 232 #define CP0C1_IL                19
 233 #define CP0C1_IA                16
 234 #define CP0C1_DS                13
 235 #define CP0C1_DL                10
 236 #define CP0C1_DA                7
 237 #define CP0C1_C2                6
 238 #define CP0C1_MD                5
 239 #define CP0C1_PC                4
 240 #define CP0C1_WR                3
 241 #define CP0C1_CA                2
 242 #define CP0C1_EP                1
 243 #define CP0C1_FP                0
 244
 245 /* Config2 Register bits */
 246 #define CP0C2_M                 31
 247 #define CP0C2_TU                28
 248 #define CP0C2_TS                24
 249 #define CP0C2_TL                20
 250 #define CP0C2_TA                16
 251 #define CP0C2_SU                12
 252 #define CP0C2_SS                8
 253 #define CP0C2_SL                4
 254 #define CP0C2_SA                0
 255
 256 /* Config3 Register bits */
 257 #define CP0C3_M                 31
 258 #define CP0C3_ISA_ON_EXC        16
 259 #define CP0C3_ULRI              13
 260 #define CP0C3_DSPP              10
 261 #define CP0C3_LPA               7
 262 #define CP0C3_VEIC              6
 263 #define CP0C3_VInt              5
 264 #define CP0C3_SP                4
 265 #define CP0C3_MT                2
 266 #define CP0C3_SM                1
 267 #define CP0C3_TL                0
 268
 269 /* Have config1, Cacheable, noncoherent, write-back, write allocate*/
 270 #define MIPS_CONFIG0                                            \
 271   ((1 << CP0C0_M) | (0x3 << CP0C0_K0))
 272
 273 /* Have config2, no coprocessor2 attached, no MDMX support attached,
 274    no performance counters, watch registers present,
 275    no code compression, EJTAG present, no FPU, no watch registers */
 276 #define MIPS_CONFIG1                                            \
 277 ((1 << CP0C1_M) |                                               \
 278  (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |          \
 279  (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |          \
 280  (0 << CP0C1_FP))
 281
 282 /* Have config3, no tertiary/secondary caches implemented */
 283 #define MIPS_CONFIG2                                            \
 284 ((1 << CP0C2_M))
 285
 286 /* No config4, no DSP ASE, no large physaddr (PABITS),
 287    no external interrupt controller, no vectored interrupts,
 288    no 1kb pages, no SmartMIPS ASE, no trace logic */
 289 #define MIPS_CONFIG3                                            \
 290 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |        \
 291  (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |      \
 292  (0 << CP0C3_SM) | (0 << CP0C3_TL))
 293
 294 /* MMU types, the first four entries have the same layout as the
 295    CP0C0_MT field.  */
 296 enum mips_mmu_types {
 297         MMU_TYPE_NONE,
 298         MMU_TYPE_R4000,
 299         MMU_TYPE_RESERVED,
 300         MMU_TYPE_FMT,
 301         MMU_TYPE_R3000,
 302         MMU_TYPE_R6000,
 303         MMU_TYPE_R8000
 304 };
 305
 306 /*
 307  * Trap codes
 308  */
 309 #define T_INT                   0       /* Interrupt pending */
 310 #define T_TLB_MOD               1       /* TLB modified fault */
 311 #define T_TLB_LD_MISS           2       /* TLB miss on load or ifetch */
 312 #define T_TLB_ST_MISS           3       /* TLB miss on a store */
 313 #define T_ADDR_ERR_LD           4       /* Address error on a load or ifetch */
 314 #define T_ADDR_ERR_ST           5       /* Address error on a store */
 315 #define T_BUS_ERR_IFETCH        6       /* Bus error on an ifetch */
 316 #define T_BUS_ERR_LD_ST         7       /* Bus error on a load or store */
 317 #define T_SYSCALL               8       /* System call */
 318 #define T_BREAK                 9       /* Breakpoint */
 319 #define T_RES_INST              10      /* Reserved instruction exception */
 320 #define T_COP_UNUSABLE          11      /* Coprocessor unusable */
 321 #define T_OVFLOW                12      /* Arithmetic overflow */
 322
 323 /*
 324  * Trap definitions added for r4000 port.
 325  */
 326 #define T_TRAP                  13      /* Trap instruction */
 327 #define T_VCEI                  14      /* Virtual coherency exception */
 328 #define T_FPE                   15      /* Floating point exception */
 329 #define T_WATCH                 23      /* Watch address reference */
 330 #define T_VCED                  31      /* Virtual coherency data */
 331
 332 /* Resume Flags */
 333 #define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
 334 #define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
 335
 336 #define RESUME_GUEST            0
 337 #define RESUME_GUEST_DR         RESUME_FLAG_DR
 338 #define RESUME_HOST             RESUME_FLAG_HOST
 339
 340 enum emulation_result {
 341         EMULATE_DONE,           /* no further processing */
 342         EMULATE_DO_MMIO,        /* kvm_run filled with MMIO request */
 343         EMULATE_FAIL,           /* can't emulate this instruction */
 344         EMULATE_WAIT,           /* WAIT instruction */
 345         EMULATE_PRIV_FAIL,
 346 };
 347
 348 #define MIPS3_PG_G      0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
 349 #define MIPS3_PG_V      0x00000002 /* Valid */
 350 #define MIPS3_PG_NV     0x00000000
 351 #define MIPS3_PG_D      0x00000004 /* Dirty */
 352
 353 #define mips3_paddr_to_tlbpfn(x) \
 354         (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
 355 #define mips3_tlbpfn_to_paddr(x) \
 356         ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
 357
 358 #define MIPS3_PG_SHIFT          6
 359 #define MIPS3_PG_FRAME          0x3fffffc0
 360
 361 #define VPN2_MASK               0xffffe000
 362 #define TLB_IS_GLOBAL(x)        (((x).tlb_lo0 & MIPS3_PG_G) &&  \
 363                                  ((x).tlb_lo1 & MIPS3_PG_G))
 364 #define TLB_VPN2(x)             ((x).tlb_hi & VPN2_MASK)
 365 #define TLB_ASID(x)             ((x).tlb_hi & ASID_MASK)
 366 #define TLB_IS_VALID(x, va)     (((va) & (1 << PAGE_SHIFT))     \
 367                                  ? ((x).tlb_lo1 & MIPS3_PG_V)   \
 368                                  : ((x).tlb_lo0 & MIPS3_PG_V))
 369
 370 struct kvm_mips_tlb {
 371         long tlb_mask;
 372         long tlb_hi;
 373         long tlb_lo0;
 374         long tlb_lo1;
 375 };
 376
 377 #define KVM_MIPS_GUEST_TLB_SIZE 64
 378 struct kvm_vcpu_arch {
 379         void *host_ebase, *guest_ebase;
 380         unsigned long host_stack;
 381         unsigned long host_gp;
 382
 383         /* Host CP0 registers used when handling exits from guest */
 384         unsigned long host_cp0_badvaddr;
 385         unsigned long host_cp0_cause;
 386         unsigned long host_cp0_epc;
 387         unsigned long host_cp0_entryhi;
 388         uint32_t guest_inst;
 389
 390         /* GPRS */
 391         unsigned long gprs[32];
 392         unsigned long hi;
 393         unsigned long lo;
 394         unsigned long pc;
 395
 396         /* FPU State */
 397         struct mips_fpu_struct fpu;
 398
 399         /* COP0 State */
 400         struct mips_coproc *cop0;
 401
 402         /* Host KSEG0 address of the EI/DI offset */
 403         void *kseg0_commpage;
 404
 405         u32 io_gpr;             /* GPR used as IO source/target */
 406
 407         /* Used to calibrate the virutal count register for the guest */
 408         int32_t host_cp0_count;
 409
 410         /* Bitmask of exceptions that are pending */
 411         unsigned long pending_exceptions;
 412
 413         /* Bitmask of pending exceptions to be cleared */
 414         unsigned long pending_exceptions_clr;
 415
 416         unsigned long pending_load_cause;
 417
 418         /* Save/Restore the entryhi register when are are preempted/scheduled back in */
 419         unsigned long preempt_entryhi;
 420
 421         /* S/W Based TLB for guest */
 422         struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
 423
 424         /* Cached guest kernel/user ASIDs */
 425         uint32_t guest_user_asid[NR_CPUS];
 426         uint32_t guest_kernel_asid[NR_CPUS];
 427         struct mm_struct guest_kernel_mm, guest_user_mm;
 428
 429         struct hrtimer comparecount_timer;
 430
 431         int last_sched_cpu;
 432
 433         /* WAIT executed */
 434         int wait;
 435 };
 436
 437
 438 #define kvm_read_c0_guest_index(cop0)           (cop0->reg[MIPS_CP0_TLB_INDEX][0])
 439 #define kvm_write_c0_guest_index(cop0, val)     (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
 440 #define kvm_read_c0_guest_entrylo0(cop0)        (cop0->reg[MIPS_CP0_TLB_LO0][0])
 441 #define kvm_read_c0_guest_entrylo1(cop0)        (cop0->reg[MIPS_CP0_TLB_LO1][0])
 442 #define kvm_read_c0_guest_context(cop0)         (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
 443 #define kvm_write_c0_guest_context(cop0, val)   (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
 444 #define kvm_read_c0_guest_userlocal(cop0)       (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
 445 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
 446 #define kvm_read_c0_guest_pagemask(cop0)        (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
 447 #define kvm_write_c0_guest_pagemask(cop0, val)  (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
 448 #define kvm_read_c0_guest_wired(cop0)           (cop0->reg[MIPS_CP0_TLB_WIRED][0])
 449 #define kvm_write_c0_guest_wired(cop0, val)     (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
 450 #define kvm_read_c0_guest_hwrena(cop0)          (cop0->reg[MIPS_CP0_HWRENA][0])
 451 #define kvm_write_c0_guest_hwrena(cop0, val)    (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
 452 #define kvm_read_c0_guest_badvaddr(cop0)        (cop0->reg[MIPS_CP0_BAD_VADDR][0])
 453 #define kvm_write_c0_guest_badvaddr(cop0, val)  (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
 454 #define kvm_read_c0_guest_count(cop0)           (cop0->reg[MIPS_CP0_COUNT][0])
 455 #define kvm_write_c0_guest_count(cop0, val)     (cop0->reg[MIPS_CP0_COUNT][0] = (val))
 456 #define kvm_read_c0_guest_entryhi(cop0)         (cop0->reg[MIPS_CP0_TLB_HI][0])
 457 #define kvm_write_c0_guest_entryhi(cop0, val)   (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
 458 #define kvm_read_c0_guest_compare(cop0)         (cop0->reg[MIPS_CP0_COMPARE][0])
 459 #define kvm_write_c0_guest_compare(cop0, val)   (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
 460 #define kvm_read_c0_guest_status(cop0)          (cop0->reg[MIPS_CP0_STATUS][0])
 461 #define kvm_write_c0_guest_status(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][0] = (val))
 462 #define kvm_read_c0_guest_intctl(cop0)          (cop0->reg[MIPS_CP0_STATUS][1])
 463 #define kvm_write_c0_guest_intctl(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][1] = (val))
 464 #define kvm_read_c0_guest_cause(cop0)           (cop0->reg[MIPS_CP0_CAUSE][0])
 465 #define kvm_write_c0_guest_cause(cop0, val)     (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
 466 #define kvm_read_c0_guest_epc(cop0)             (cop0->reg[MIPS_CP0_EXC_PC][0])
 467 #define kvm_write_c0_guest_epc(cop0, val)       (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
 468 #define kvm_read_c0_guest_prid(cop0)            (cop0->reg[MIPS_CP0_PRID][0])
 469 #define kvm_write_c0_guest_prid(cop0, val)      (cop0->reg[MIPS_CP0_PRID][0] = (val))
 470 #define kvm_read_c0_guest_ebase(cop0)           (cop0->reg[MIPS_CP0_PRID][1])
 471 #define kvm_write_c0_guest_ebase(cop0, val)     (cop0->reg[MIPS_CP0_PRID][1] = (val))
 472 #define kvm_read_c0_guest_config(cop0)          (cop0->reg[MIPS_CP0_CONFIG][0])
 473 #define kvm_read_c0_guest_config1(cop0)         (cop0->reg[MIPS_CP0_CONFIG][1])
 474 #define kvm_read_c0_guest_config2(cop0)         (cop0->reg[MIPS_CP0_CONFIG][2])
 475 #define kvm_read_c0_guest_config3(cop0)         (cop0->reg[MIPS_CP0_CONFIG][3])
 476 #define kvm_read_c0_guest_config7(cop0)         (cop0->reg[MIPS_CP0_CONFIG][7])
 477 #define kvm_write_c0_guest_config(cop0, val)    (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
 478 #define kvm_write_c0_guest_config1(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
 479 #define kvm_write_c0_guest_config2(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
 480 #define kvm_write_c0_guest_config3(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
 481 #define kvm_write_c0_guest_config7(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
 482 #define kvm_read_c0_guest_errorepc(cop0)        (cop0->reg[MIPS_CP0_ERROR_PC][0])
 483 #define kvm_write_c0_guest_errorepc(cop0, val)  (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
 484
 485 /*
 486  * Some of the guest registers may be modified asynchronously (e.g. from a
 487  * hrtimer callback in hard irq context) and therefore need stronger atomicity
 488  * guarantees than other registers.
 489  */
 490
 491 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
 492                                                 unsigned long val)
 493 {
 494         unsigned long temp;
 495         do {
 496                 __asm__ __volatile__(
 497                 "       .set    mips3                           \n"
 498                 "       " __LL "%0, %1                          \n"
 499                 "       or      %0, %2                          \n"
 500                 "       " __SC  "%0, %1                         \n"
 501                 "       .set    mips0                           \n"
 502                 : "=&r" (temp), "+m" (*reg)
 503                 : "r" (val));
 504         } while (unlikely(!temp));
 505 }
 506
 507 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
 508                                                   unsigned long val)
 509 {
 510         unsigned long temp;
 511         do {
 512                 __asm__ __volatile__(
 513                 "       .set    mips3                           \n"
 514                 "       " __LL "%0, %1                          \n"
 515                 "       and     %0, %2                          \n"
 516                 "       " __SC  "%0, %1                         \n"
 517                 "       .set    mips0                           \n"
 518                 : "=&r" (temp), "+m" (*reg)
 519                 : "r" (~val));
 520         } while (unlikely(!temp));
 521 }
 522
 523 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
 524                                                    unsigned long change,
 525                                                    unsigned long val)
 526 {
 527         unsigned long temp;
 528         do {
 529                 __asm__ __volatile__(
 530                 "       .set    mips3                           \n"
 531                 "       " __LL "%0, %1                          \n"
 532                 "       and     %0, %2                          \n"
 533                 "       or      %0, %3                          \n"
 534                 "       " __SC  "%0, %1                         \n"
 535                 "       .set    mips0                           \n"
 536                 : "=&r" (temp), "+m" (*reg)
 537                 : "r" (~change), "r" (val & change));
 538         } while (unlikely(!temp));
 539 }
 540
 541 #define kvm_set_c0_guest_status(cop0, val)      (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
 542 #define kvm_clear_c0_guest_status(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
 543
 544 /* Cause can be modified asynchronously from hardirq hrtimer callback */
 545 #define kvm_set_c0_guest_cause(cop0, val)                               \
 546         _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
 547 #define kvm_clear_c0_guest_cause(cop0, val)                             \
 548         _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
 549 #define kvm_change_c0_guest_cause(cop0, change, val)                    \
 550         _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0],  \
 551                                         change, val)
 552
 553 #define kvm_set_c0_guest_ebase(cop0, val)       (cop0->reg[MIPS_CP0_PRID][1] |= (val))
 554 #define kvm_clear_c0_guest_ebase(cop0, val)     (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
 555 #define kvm_change_c0_guest_ebase(cop0, change, val)                    \
 556 {                                                                       \
 557         kvm_clear_c0_guest_ebase(cop0, change);                         \
 558         kvm_set_c0_guest_ebase(cop0, ((val) & (change)));               \
 559 }
 560
 561
 562 struct kvm_mips_callbacks {
 563         int (*handle_cop_unusable) (struct kvm_vcpu *vcpu);
 564         int (*handle_tlb_mod) (struct kvm_vcpu *vcpu);
 565         int (*handle_tlb_ld_miss) (struct kvm_vcpu *vcpu);
 566         int (*handle_tlb_st_miss) (struct kvm_vcpu *vcpu);
 567         int (*handle_addr_err_st) (struct kvm_vcpu *vcpu);
 568         int (*handle_addr_err_ld) (struct kvm_vcpu *vcpu);
 569         int (*handle_syscall) (struct kvm_vcpu *vcpu);
 570         int (*handle_res_inst) (struct kvm_vcpu *vcpu);
 571         int (*handle_break) (struct kvm_vcpu *vcpu);
 572         int (*vm_init) (struct kvm *kvm);
 573         int (*vcpu_init) (struct kvm_vcpu *vcpu);
 574         int (*vcpu_setup) (struct kvm_vcpu *vcpu);
 575          gpa_t(*gva_to_gpa) (gva_t gva);
 576         void (*queue_timer_int) (struct kvm_vcpu *vcpu);
 577         void (*dequeue_timer_int) (struct kvm_vcpu *vcpu);
 578         void (*queue_io_int) (struct kvm_vcpu *vcpu,
 579                               struct kvm_mips_interrupt *irq);
 580         void (*dequeue_io_int) (struct kvm_vcpu *vcpu,
 581                                 struct kvm_mips_interrupt *irq);
 582         int (*irq_deliver) (struct kvm_vcpu *vcpu, unsigned int priority,
 583                             uint32_t cause);
 584         int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority,
 585                           uint32_t cause);
 586         int (*get_one_reg)(struct kvm_vcpu *vcpu,
 587                            const struct kvm_one_reg *reg, s64 *v);
 588         int (*set_one_reg)(struct kvm_vcpu *vcpu,
 589                            const struct kvm_one_reg *reg, s64 v);
 590 };
 591 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
 592 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
 593
 594 /* Debug: dump vcpu state */
 595 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
 596
 597 /* Trampoline ASM routine to start running in "Guest" context */
 598 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
 599
 600 /* TLB handling */
 601 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
 602
 603 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
 604
 605 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
 606
 607 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
 608                                            struct kvm_vcpu *vcpu);
 609
 610 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
 611                                               struct kvm_vcpu *vcpu);
 612
 613 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
 614                                                 struct kvm_mips_tlb *tlb,
 615                                                 unsigned long *hpa0,
 616                                                 unsigned long *hpa1);
 617
 618 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
 619                                                      uint32_t *opc,
 620                                                      struct kvm_run *run,
 621                                                      struct kvm_vcpu *vcpu);
 622
 623 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
 624                                                     uint32_t *opc,
 625                                                     struct kvm_run *run,
 626                                                     struct kvm_vcpu *vcpu);
 627
 628 extern void kvm_mips_dump_host_tlbs(void);
 629 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
 630 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
 631 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
 632 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
 633
 634 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
 635                                      unsigned long entryhi);
 636 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
 637 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
 638                                                    unsigned long gva);
 639 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
 640                                     struct kvm_vcpu *vcpu);
 641 extern void kvm_local_flush_tlb_all(void);
 642 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
 643 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 644 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
 645
 646 /* Emulation */
 647 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
 648 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
 649
 650 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
 651                                                    uint32_t *opc,
 652                                                    struct kvm_run *run,
 653                                                    struct kvm_vcpu *vcpu);
 654
 655 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
 656                                                       uint32_t *opc,
 657                                                       struct kvm_run *run,
 658                                                       struct kvm_vcpu *vcpu);
 659
 660 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
 661                                                          uint32_t *opc,
 662                                                          struct kvm_run *run,
 663                                                          struct kvm_vcpu *vcpu);
 664
 665 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
 666                                                         uint32_t *opc,
 667                                                         struct kvm_run *run,
 668                                                         struct kvm_vcpu *vcpu);
 669
 670 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
 671                                                          uint32_t *opc,
 672                                                          struct kvm_run *run,
 673                                                          struct kvm_vcpu *vcpu);
 674
 675 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
 676                                                         uint32_t *opc,
 677                                                         struct kvm_run *run,
 678                                                         struct kvm_vcpu *vcpu);
 679
 680 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
 681                                                      uint32_t *opc,
 682                                                      struct kvm_run *run,
 683                                                      struct kvm_vcpu *vcpu);
 684
 685 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
 686                                                       uint32_t *opc,
 687                                                       struct kvm_run *run,
 688                                                       struct kvm_vcpu *vcpu);
 689
 690 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
 691                                                 uint32_t *opc,
 692                                                 struct kvm_run *run,
 693                                                 struct kvm_vcpu *vcpu);
 694
 695 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
 696                                                      uint32_t *opc,
 697                                                      struct kvm_run *run,
 698                                                      struct kvm_vcpu *vcpu);
 699
 700 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
 701                                                      uint32_t *opc,
 702                                                      struct kvm_run *run,
 703                                                      struct kvm_vcpu *vcpu);
 704
 705 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
 706                                                          struct kvm_run *run);
 707
 708 enum emulation_result kvm_mips_emulate_count(struct kvm_vcpu *vcpu);
 709
 710 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
 711                                                uint32_t *opc,
 712                                                struct kvm_run *run,
 713                                                struct kvm_vcpu *vcpu);
 714
 715 enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
 716                                              uint32_t *opc,
 717                                              uint32_t cause,
 718                                              struct kvm_run *run,
 719                                              struct kvm_vcpu *vcpu);
 720 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
 721                                            uint32_t *opc,
 722                                            uint32_t cause,
 723                                            struct kvm_run *run,
 724                                            struct kvm_vcpu *vcpu);
 725 enum emulation_result kvm_mips_emulate_store(uint32_t inst,
 726                                              uint32_t cause,
 727                                              struct kvm_run *run,
 728                                              struct kvm_vcpu *vcpu);
 729 enum emulation_result kvm_mips_emulate_load(uint32_t inst,
 730                                             uint32_t cause,
 731                                             struct kvm_run *run,
 732                                             struct kvm_vcpu *vcpu);
 733
 734 /* Dynamic binary translation */
 735 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
 736                                       struct kvm_vcpu *vcpu);
 737 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
 738                                    struct kvm_vcpu *vcpu);
 739 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
 740                                struct kvm_vcpu *vcpu);
 741 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
 742                                struct kvm_vcpu *vcpu);
 743
 744 /* Misc */
 745 extern int kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
 746 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
 747
 748
 749 #endif /* __MIPS_KVM_HOST_H__ */