2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
23 #define KVM_MAX_VCPUS 1
24 #define KVM_USER_MEM_SLOTS 8
25 /* memory slots that does not exposed to userspace */
26 #define KVM_PRIVATE_MEM_SLOTS 0
28 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
32 /* Special address that contains the comm page, used for reducing # of traps */
33 #define KVM_GUEST_COMMPAGE_ADDR 0x0
35 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
36 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
38 #define KVM_GUEST_KUSEG 0x00000000UL
39 #define KVM_GUEST_KSEG0 0x40000000UL
40 #define KVM_GUEST_KSEG23 0x60000000UL
41 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
42 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
44 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
45 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
46 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
49 * Map an address to a certain kernel segment
51 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
52 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
53 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
55 #define KVM_INVALID_PAGE 0xdeadbeef
56 #define KVM_INVALID_INST 0xdeadbeef
57 #define KVM_INVALID_ADDR 0xdeadbeef
59 #define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL
61 #define GUEST_TICKS_PER_JIFFY (40000000/HZ)
62 #define MS_TO_NS(x) (x * 1E6L)
65 #define CAUSEF_DC (_ULCAST_(1) << 27)
72 extern atomic_t kvm_mips_instance;
73 extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
74 extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
75 extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
81 struct kvm_vcpu_stat {
86 u32 cop_unusable_exits;
95 u32 flush_dcache_exits;
99 enum kvm_mips_exit_types {
114 MAX_KVM_MIPS_EXIT_TYPES
117 struct kvm_arch_memory_slot {
121 /* Guest GVA->HPA page table */
122 unsigned long *guest_pmap;
123 unsigned long guest_pmap_npages;
125 /* Wired host TLB used for the commpage */
129 #define N_MIPS_COPROC_REGS 32
130 #define N_MIPS_COPROC_SEL 8
133 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
134 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
135 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
140 * Coprocessor 0 register names
142 #define MIPS_CP0_TLB_INDEX 0
143 #define MIPS_CP0_TLB_RANDOM 1
144 #define MIPS_CP0_TLB_LOW 2
145 #define MIPS_CP0_TLB_LO0 2
146 #define MIPS_CP0_TLB_LO1 3
147 #define MIPS_CP0_TLB_CONTEXT 4
148 #define MIPS_CP0_TLB_PG_MASK 5
149 #define MIPS_CP0_TLB_WIRED 6
150 #define MIPS_CP0_HWRENA 7
151 #define MIPS_CP0_BAD_VADDR 8
152 #define MIPS_CP0_COUNT 9
153 #define MIPS_CP0_TLB_HI 10
154 #define MIPS_CP0_COMPARE 11
155 #define MIPS_CP0_STATUS 12
156 #define MIPS_CP0_CAUSE 13
157 #define MIPS_CP0_EXC_PC 14
158 #define MIPS_CP0_PRID 15
159 #define MIPS_CP0_CONFIG 16
160 #define MIPS_CP0_LLADDR 17
161 #define MIPS_CP0_WATCH_LO 18
162 #define MIPS_CP0_WATCH_HI 19
163 #define MIPS_CP0_TLB_XCONTEXT 20
164 #define MIPS_CP0_ECC 26
165 #define MIPS_CP0_CACHE_ERR 27
166 #define MIPS_CP0_TAG_LO 28
167 #define MIPS_CP0_TAG_HI 29
168 #define MIPS_CP0_ERROR_PC 30
169 #define MIPS_CP0_DEBUG 23
170 #define MIPS_CP0_DEPC 24
171 #define MIPS_CP0_PERFCNT 25
172 #define MIPS_CP0_ERRCTL 26
173 #define MIPS_CP0_DATA_LO 28
174 #define MIPS_CP0_DATA_HI 29
175 #define MIPS_CP0_DESAVE 31
177 #define MIPS_CP0_CONFIG_SEL 0
178 #define MIPS_CP0_CONFIG1_SEL 1
179 #define MIPS_CP0_CONFIG2_SEL 2
180 #define MIPS_CP0_CONFIG3_SEL 3
182 /* Config0 register bits */
196 /* Config1 register bits */
213 /* Config2 Register bits */
224 /* Config3 Register bits */
226 #define CP0C3_ISA_ON_EXC 16
227 #define CP0C3_ULRI 13
228 #define CP0C3_DSPP 10
237 /* Have config1, Cacheable, noncoherent, write-back, write allocate*/
238 #define MIPS_CONFIG0 \
239 ((1 << CP0C0_M) | (0x3 << CP0C0_K0))
241 /* Have config2, no coprocessor2 attached, no MDMX support attached,
242 no performance counters, watch registers present,
243 no code compression, EJTAG present, no FPU, no watch registers */
244 #define MIPS_CONFIG1 \
246 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
247 (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
250 /* Have config3, no tertiary/secondary caches implemented */
251 #define MIPS_CONFIG2 \
254 /* No config4, no DSP ASE, no large physaddr (PABITS),
255 no external interrupt controller, no vectored interrupts,
256 no 1kb pages, no SmartMIPS ASE, no trace logic */
257 #define MIPS_CONFIG3 \
258 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
259 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
260 (0 << CP0C3_SM) | (0 << CP0C3_TL))
262 /* MMU types, the first four entries have the same layout as the
264 enum mips_mmu_types {
277 #define T_INT 0 /* Interrupt pending */
278 #define T_TLB_MOD 1 /* TLB modified fault */
279 #define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
280 #define T_TLB_ST_MISS 3 /* TLB miss on a store */
281 #define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
282 #define T_ADDR_ERR_ST 5 /* Address error on a store */
283 #define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
284 #define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
285 #define T_SYSCALL 8 /* System call */
286 #define T_BREAK 9 /* Breakpoint */
287 #define T_RES_INST 10 /* Reserved instruction exception */
288 #define T_COP_UNUSABLE 11 /* Coprocessor unusable */
289 #define T_OVFLOW 12 /* Arithmetic overflow */
292 * Trap definitions added for r4000 port.
294 #define T_TRAP 13 /* Trap instruction */
295 #define T_VCEI 14 /* Virtual coherency exception */
296 #define T_FPE 15 /* Floating point exception */
297 #define T_WATCH 23 /* Watch address reference */
298 #define T_VCED 31 /* Virtual coherency data */
301 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
302 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
304 #define RESUME_GUEST 0
305 #define RESUME_GUEST_DR RESUME_FLAG_DR
306 #define RESUME_HOST RESUME_FLAG_HOST
308 enum emulation_result {
309 EMULATE_DONE, /* no further processing */
310 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
311 EMULATE_FAIL, /* can't emulate this instruction */
312 EMULATE_WAIT, /* WAIT instruction */
316 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
317 #define MIPS3_PG_V 0x00000002 /* Valid */
318 #define MIPS3_PG_NV 0x00000000
319 #define MIPS3_PG_D 0x00000004 /* Dirty */
321 #define mips3_paddr_to_tlbpfn(x) \
322 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
323 #define mips3_tlbpfn_to_paddr(x) \
324 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
326 #define MIPS3_PG_SHIFT 6
327 #define MIPS3_PG_FRAME 0x3fffffc0
329 #define VPN2_MASK 0xffffe000
330 #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \
331 ((x).tlb_lo1 & MIPS3_PG_G))
332 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
333 #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
334 #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
335 ? ((x).tlb_lo1 & MIPS3_PG_V) \
336 : ((x).tlb_lo0 & MIPS3_PG_V))
338 struct kvm_mips_tlb {
345 #define KVM_MIPS_GUEST_TLB_SIZE 64
346 struct kvm_vcpu_arch {
347 void *host_ebase, *guest_ebase;
348 unsigned long host_stack;
349 unsigned long host_gp;
351 /* Host CP0 registers used when handling exits from guest */
352 unsigned long host_cp0_badvaddr;
353 unsigned long host_cp0_cause;
354 unsigned long host_cp0_epc;
355 unsigned long host_cp0_entryhi;
359 unsigned long gprs[32];
365 struct mips_fpu_struct fpu;
368 struct mips_coproc *cop0;
370 /* Host KSEG0 address of the EI/DI offset */
371 void *kseg0_commpage;
373 u32 io_gpr; /* GPR used as IO source/target */
375 /* Used to calibrate the virutal count register for the guest */
376 int32_t host_cp0_count;
378 /* Bitmask of exceptions that are pending */
379 unsigned long pending_exceptions;
381 /* Bitmask of pending exceptions to be cleared */
382 unsigned long pending_exceptions_clr;
384 unsigned long pending_load_cause;
386 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
387 unsigned long preempt_entryhi;
389 /* S/W Based TLB for guest */
390 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
392 /* Cached guest kernel/user ASIDs */
393 uint32_t guest_user_asid[NR_CPUS];
394 uint32_t guest_kernel_asid[NR_CPUS];
395 struct mm_struct guest_kernel_mm, guest_user_mm;
397 struct hrtimer comparecount_timer;
406 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
407 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
408 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
409 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
410 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
411 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
412 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
413 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
414 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
415 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
416 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
417 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
418 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
419 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
420 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
421 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
422 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
423 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
424 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
425 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
426 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
427 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
428 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
429 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
430 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
431 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
432 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
433 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
434 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
435 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
436 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
437 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
438 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
439 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
440 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
441 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
442 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
443 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
444 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
445 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
446 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
447 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
448 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
449 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
450 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
452 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
453 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
454 #define kvm_set_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] |= (val))
455 #define kvm_clear_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] &= ~(val))
456 #define kvm_change_c0_guest_cause(cop0, change, val) \
458 kvm_clear_c0_guest_cause(cop0, change); \
459 kvm_set_c0_guest_cause(cop0, ((val) & (change))); \
461 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
462 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
463 #define kvm_change_c0_guest_ebase(cop0, change, val) \
465 kvm_clear_c0_guest_ebase(cop0, change); \
466 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
470 struct kvm_mips_callbacks {
471 int (*handle_cop_unusable) (struct kvm_vcpu *vcpu);
472 int (*handle_tlb_mod) (struct kvm_vcpu *vcpu);
473 int (*handle_tlb_ld_miss) (struct kvm_vcpu *vcpu);
474 int (*handle_tlb_st_miss) (struct kvm_vcpu *vcpu);
475 int (*handle_addr_err_st) (struct kvm_vcpu *vcpu);
476 int (*handle_addr_err_ld) (struct kvm_vcpu *vcpu);
477 int (*handle_syscall) (struct kvm_vcpu *vcpu);
478 int (*handle_res_inst) (struct kvm_vcpu *vcpu);
479 int (*handle_break) (struct kvm_vcpu *vcpu);
480 int (*vm_init) (struct kvm *kvm);
481 int (*vcpu_init) (struct kvm_vcpu *vcpu);
482 int (*vcpu_setup) (struct kvm_vcpu *vcpu);
483 gpa_t(*gva_to_gpa) (gva_t gva);
484 void (*queue_timer_int) (struct kvm_vcpu *vcpu);
485 void (*dequeue_timer_int) (struct kvm_vcpu *vcpu);
486 void (*queue_io_int) (struct kvm_vcpu *vcpu,
487 struct kvm_mips_interrupt *irq);
488 void (*dequeue_io_int) (struct kvm_vcpu *vcpu,
489 struct kvm_mips_interrupt *irq);
490 int (*irq_deliver) (struct kvm_vcpu *vcpu, unsigned int priority,
492 int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority,
495 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
496 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
498 /* Debug: dump vcpu state */
499 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
501 /* Trampoline ASM routine to start running in "Guest" context */
502 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
505 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
507 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
509 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
511 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
512 struct kvm_vcpu *vcpu);
514 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
515 struct kvm_vcpu *vcpu);
517 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
518 struct kvm_mips_tlb *tlb,
520 unsigned long *hpa1);
522 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
525 struct kvm_vcpu *vcpu);
527 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
530 struct kvm_vcpu *vcpu);
532 extern void kvm_mips_dump_host_tlbs(void);
533 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
534 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
535 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
536 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
538 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
539 unsigned long entryhi);
540 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
541 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
543 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
544 struct kvm_vcpu *vcpu);
545 extern void kvm_local_flush_tlb_all(void);
546 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
547 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
548 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
551 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
552 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
554 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
557 struct kvm_vcpu *vcpu);
559 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
562 struct kvm_vcpu *vcpu);
564 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
567 struct kvm_vcpu *vcpu);
569 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
572 struct kvm_vcpu *vcpu);
574 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
577 struct kvm_vcpu *vcpu);
579 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
582 struct kvm_vcpu *vcpu);
584 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
587 struct kvm_vcpu *vcpu);
589 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
592 struct kvm_vcpu *vcpu);
594 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
597 struct kvm_vcpu *vcpu);
599 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
602 struct kvm_vcpu *vcpu);
604 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
607 struct kvm_vcpu *vcpu);
609 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
610 struct kvm_run *run);
612 enum emulation_result kvm_mips_emulate_count(struct kvm_vcpu *vcpu);
614 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
617 struct kvm_vcpu *vcpu);
619 enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
623 struct kvm_vcpu *vcpu);
624 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
628 struct kvm_vcpu *vcpu);
629 enum emulation_result kvm_mips_emulate_store(uint32_t inst,
632 struct kvm_vcpu *vcpu);
633 enum emulation_result kvm_mips_emulate_load(uint32_t inst,
636 struct kvm_vcpu *vcpu);
638 /* Dynamic binary translation */
639 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
640 struct kvm_vcpu *vcpu);
641 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
642 struct kvm_vcpu *vcpu);
643 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
644 struct kvm_vcpu *vcpu);
645 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
646 struct kvm_vcpu *vcpu);
649 extern void mips32_SyncICache(unsigned long addr, unsigned long size);
650 extern int kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
651 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
654 #endif /* __MIPS_KVM_HOST_H__ */