3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
38 #ifndef _LANGUAGE_ASSEMBLY
40 #include <linux/delay.h>
41 #include <linux/types.h>
44 #include <linux/irq.h>
46 /* cpu pipeline flush */
47 void static inline au_sync(void)
49 __asm__ volatile ("sync");
52 void static inline au_sync_udelay(int us)
54 __asm__ volatile ("sync");
58 void static inline au_sync_delay(int ms)
60 __asm__ volatile ("sync");
64 void static inline au_writeb(u8 val, unsigned long reg)
66 *(volatile u8 *)reg = val;
69 void static inline au_writew(u16 val, unsigned long reg)
71 *(volatile u16 *)reg = val;
74 void static inline au_writel(u32 val, unsigned long reg)
76 *(volatile u32 *)reg = val;
79 static inline u8 au_readb(unsigned long reg)
81 return *(volatile u8 *)reg;
84 static inline u16 au_readw(unsigned long reg)
86 return *(volatile u16 *)reg;
89 static inline u32 au_readl(unsigned long reg)
91 return *(volatile u32 *)reg;
94 /* Early Au1000 have a write-only SYS_CPUPLL register. */
95 static inline int au1xxx_cpu_has_pll_wo(void)
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
106 /* does CPU need CONFIG[OD] set to fix tons of errata? */
107 static inline int au1xxx_cpu_needs_config_od(void)
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
133 /* arch/mips/au1000/common/clocks.c */
134 extern void set_au1x00_speed(unsigned int new_freq);
135 extern unsigned int get_au1x00_speed(void);
136 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
137 extern unsigned long get_au1x00_uart_baud_base(void);
138 extern unsigned long au1xxx_calc_clock(void);
140 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
141 void au1xxx_save_and_sleep(void);
143 void save_au1xxx_intctl(void);
144 void restore_au1xxx_intctl(void);
146 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
149 * SDRAM register offsets
151 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
152 defined(CONFIG_SOC_AU1100)
153 #define MEM_SDMODE0 0x0000
154 #define MEM_SDMODE1 0x0004
155 #define MEM_SDMODE2 0x0008
156 #define MEM_SDADDR0 0x000C
157 #define MEM_SDADDR1 0x0010
158 #define MEM_SDADDR2 0x0014
159 #define MEM_SDREFCFG 0x0018
160 #define MEM_SDPRECMD 0x001C
161 #define MEM_SDAUTOREF 0x0020
162 #define MEM_SDWRMD0 0x0024
163 #define MEM_SDWRMD1 0x0028
164 #define MEM_SDWRMD2 0x002C
165 #define MEM_SDSLEEP 0x0030
166 #define MEM_SDSMCKE 0x0034
169 * MEM_SDMODE register content definitions
171 #define MEM_SDMODE_F (1 << 22)
172 #define MEM_SDMODE_SR (1 << 21)
173 #define MEM_SDMODE_BS (1 << 20)
174 #define MEM_SDMODE_RS (3 << 18)
175 #define MEM_SDMODE_CS (7 << 15)
176 #define MEM_SDMODE_TRAS (15 << 11)
177 #define MEM_SDMODE_TMRD (3 << 9)
178 #define MEM_SDMODE_TWR (3 << 7)
179 #define MEM_SDMODE_TRP (3 << 5)
180 #define MEM_SDMODE_TRCD (3 << 3)
181 #define MEM_SDMODE_TCL (7 << 0)
183 #define MEM_SDMODE_BS_2Bank (0 << 20)
184 #define MEM_SDMODE_BS_4Bank (1 << 20)
185 #define MEM_SDMODE_RS_11Row (0 << 18)
186 #define MEM_SDMODE_RS_12Row (1 << 18)
187 #define MEM_SDMODE_RS_13Row (2 << 18)
188 #define MEM_SDMODE_RS_N(N) ((N) << 18)
189 #define MEM_SDMODE_CS_7Col (0 << 15)
190 #define MEM_SDMODE_CS_8Col (1 << 15)
191 #define MEM_SDMODE_CS_9Col (2 << 15)
192 #define MEM_SDMODE_CS_10Col (3 << 15)
193 #define MEM_SDMODE_CS_11Col (4 << 15)
194 #define MEM_SDMODE_CS_N(N) ((N) << 15)
195 #define MEM_SDMODE_TRAS_N(N) ((N) << 11)
196 #define MEM_SDMODE_TMRD_N(N) ((N) << 9)
197 #define MEM_SDMODE_TWR_N(N) ((N) << 7)
198 #define MEM_SDMODE_TRP_N(N) ((N) << 5)
199 #define MEM_SDMODE_TRCD_N(N) ((N) << 3)
200 #define MEM_SDMODE_TCL_N(N) ((N) << 0)
203 * MEM_SDADDR register contents definitions
205 #define MEM_SDADDR_E (1 << 20)
206 #define MEM_SDADDR_CSBA (0x03FF << 10)
207 #define MEM_SDADDR_CSMASK (0x03FF << 0)
208 #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
209 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
212 * MEM_SDREFCFG register content definitions
214 #define MEM_SDREFCFG_TRC (15 << 28)
215 #define MEM_SDREFCFG_TRPM (3 << 26)
216 #define MEM_SDREFCFG_E (1 << 25)
217 #define MEM_SDREFCFG_RE (0x1ffffff << 0)
218 #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
219 #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
220 #define MEM_SDREFCFG_REF_N(N) (N)
223 /***********************************************************************/
226 * Au1550 SDRAM Register Offsets
229 /***********************************************************************/
231 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
232 #define MEM_SDMODE0 0x0800
233 #define MEM_SDMODE1 0x0808
234 #define MEM_SDMODE2 0x0810
235 #define MEM_SDADDR0 0x0820
236 #define MEM_SDADDR1 0x0828
237 #define MEM_SDADDR2 0x0830
238 #define MEM_SDCONFIGA 0x0840
239 #define MEM_SDCONFIGB 0x0848
240 #define MEM_SDSTAT 0x0850
241 #define MEM_SDERRADDR 0x0858
242 #define MEM_SDSTRIDE0 0x0860
243 #define MEM_SDSTRIDE1 0x0868
244 #define MEM_SDSTRIDE2 0x0870
245 #define MEM_SDWRMD0 0x0880
246 #define MEM_SDWRMD1 0x0888
247 #define MEM_SDWRMD2 0x0890
248 #define MEM_SDPRECMD 0x08C0
249 #define MEM_SDAUTOREF 0x08C8
250 #define MEM_SDSREF 0x08D0
251 #define MEM_SDSLEEP MEM_SDSREF
256 * Physical base addresses for integrated peripherals
259 #ifdef CONFIG_SOC_AU1000
260 #define MEM_PHYS_ADDR 0x14000000
261 #define STATIC_MEM_PHYS_ADDR 0x14001000
262 #define DMA0_PHYS_ADDR 0x14002000
263 #define DMA1_PHYS_ADDR 0x14002100
264 #define DMA2_PHYS_ADDR 0x14002200
265 #define DMA3_PHYS_ADDR 0x14002300
266 #define DMA4_PHYS_ADDR 0x14002400
267 #define DMA5_PHYS_ADDR 0x14002500
268 #define DMA6_PHYS_ADDR 0x14002600
269 #define DMA7_PHYS_ADDR 0x14002700
270 #define IC0_PHYS_ADDR 0x10400000
271 #define IC1_PHYS_ADDR 0x11800000
272 #define AC97_PHYS_ADDR 0x10000000
273 #define USBH_PHYS_ADDR 0x10100000
274 #define USBD_PHYS_ADDR 0x10200000
275 #define IRDA_PHYS_ADDR 0x10300000
276 #define MAC0_PHYS_ADDR 0x10500000
277 #define MAC1_PHYS_ADDR 0x10510000
278 #define MACEN_PHYS_ADDR 0x10520000
279 #define MACDMA0_PHYS_ADDR 0x14004000
280 #define MACDMA1_PHYS_ADDR 0x14004200
281 #define I2S_PHYS_ADDR 0x11000000
282 #define UART0_PHYS_ADDR 0x11100000
283 #define UART1_PHYS_ADDR 0x11200000
284 #define UART2_PHYS_ADDR 0x11300000
285 #define UART3_PHYS_ADDR 0x11400000
286 #define SSI0_PHYS_ADDR 0x11600000
287 #define SSI1_PHYS_ADDR 0x11680000
288 #define SYS_PHYS_ADDR 0x11900000
289 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
290 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
291 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
294 /********************************************************************/
296 #ifdef CONFIG_SOC_AU1500
297 #define MEM_PHYS_ADDR 0x14000000
298 #define STATIC_MEM_PHYS_ADDR 0x14001000
299 #define DMA0_PHYS_ADDR 0x14002000
300 #define DMA1_PHYS_ADDR 0x14002100
301 #define DMA2_PHYS_ADDR 0x14002200
302 #define DMA3_PHYS_ADDR 0x14002300
303 #define DMA4_PHYS_ADDR 0x14002400
304 #define DMA5_PHYS_ADDR 0x14002500
305 #define DMA6_PHYS_ADDR 0x14002600
306 #define DMA7_PHYS_ADDR 0x14002700
307 #define IC0_PHYS_ADDR 0x10400000
308 #define IC1_PHYS_ADDR 0x11800000
309 #define AC97_PHYS_ADDR 0x10000000
310 #define USBH_PHYS_ADDR 0x10100000
311 #define USBD_PHYS_ADDR 0x10200000
312 #define PCI_PHYS_ADDR 0x14005000
313 #define MAC0_PHYS_ADDR 0x11500000
314 #define MAC1_PHYS_ADDR 0x11510000
315 #define MACEN_PHYS_ADDR 0x11520000
316 #define MACDMA0_PHYS_ADDR 0x14004000
317 #define MACDMA1_PHYS_ADDR 0x14004200
318 #define I2S_PHYS_ADDR 0x11000000
319 #define UART0_PHYS_ADDR 0x11100000
320 #define UART3_PHYS_ADDR 0x11400000
321 #define GPIO2_PHYS_ADDR 0x11700000
322 #define SYS_PHYS_ADDR 0x11900000
323 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
324 #define PCI_IO_PHYS_ADDR 0x500000000ULL
325 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
326 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
327 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
328 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
329 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
332 /********************************************************************/
334 #ifdef CONFIG_SOC_AU1100
335 #define MEM_PHYS_ADDR 0x14000000
336 #define STATIC_MEM_PHYS_ADDR 0x14001000
337 #define DMA0_PHYS_ADDR 0x14002000
338 #define DMA1_PHYS_ADDR 0x14002100
339 #define DMA2_PHYS_ADDR 0x14002200
340 #define DMA3_PHYS_ADDR 0x14002300
341 #define DMA4_PHYS_ADDR 0x14002400
342 #define DMA5_PHYS_ADDR 0x14002500
343 #define DMA6_PHYS_ADDR 0x14002600
344 #define DMA7_PHYS_ADDR 0x14002700
345 #define IC0_PHYS_ADDR 0x10400000
346 #define SD0_PHYS_ADDR 0x10600000
347 #define SD1_PHYS_ADDR 0x10680000
348 #define IC1_PHYS_ADDR 0x11800000
349 #define AC97_PHYS_ADDR 0x10000000
350 #define USBH_PHYS_ADDR 0x10100000
351 #define USBD_PHYS_ADDR 0x10200000
352 #define IRDA_PHYS_ADDR 0x10300000
353 #define MAC0_PHYS_ADDR 0x10500000
354 #define MACEN_PHYS_ADDR 0x10520000
355 #define MACDMA0_PHYS_ADDR 0x14004000
356 #define MACDMA1_PHYS_ADDR 0x14004200
357 #define I2S_PHYS_ADDR 0x11000000
358 #define UART0_PHYS_ADDR 0x11100000
359 #define UART1_PHYS_ADDR 0x11200000
360 #define UART3_PHYS_ADDR 0x11400000
361 #define SSI0_PHYS_ADDR 0x11600000
362 #define SSI1_PHYS_ADDR 0x11680000
363 #define GPIO2_PHYS_ADDR 0x11700000
364 #define SYS_PHYS_ADDR 0x11900000
365 #define LCD_PHYS_ADDR 0x15000000
366 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
367 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
368 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
371 /***********************************************************************/
373 #ifdef CONFIG_SOC_AU1550
374 #define MEM_PHYS_ADDR 0x14000000
375 #define STATIC_MEM_PHYS_ADDR 0x14001000
376 #define IC0_PHYS_ADDR 0x10400000
377 #define IC1_PHYS_ADDR 0x11800000
378 #define USBH_PHYS_ADDR 0x14020000
379 #define USBD_PHYS_ADDR 0x10200000
380 #define PCI_PHYS_ADDR 0x14005000
381 #define MAC0_PHYS_ADDR 0x10500000
382 #define MAC1_PHYS_ADDR 0x10510000
383 #define MACEN_PHYS_ADDR 0x10520000
384 #define MACDMA0_PHYS_ADDR 0x14004000
385 #define MACDMA1_PHYS_ADDR 0x14004200
386 #define UART0_PHYS_ADDR 0x11100000
387 #define UART1_PHYS_ADDR 0x11200000
388 #define UART3_PHYS_ADDR 0x11400000
389 #define GPIO2_PHYS_ADDR 0x11700000
390 #define SYS_PHYS_ADDR 0x11900000
391 #define DDMA_PHYS_ADDR 0x14002000
392 #define PE_PHYS_ADDR 0x14008000
393 #define PSC0_PHYS_ADDR 0x11A00000
394 #define PSC1_PHYS_ADDR 0x11B00000
395 #define PSC2_PHYS_ADDR 0x10A00000
396 #define PSC3_PHYS_ADDR 0x10B00000
397 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
398 #define PCI_IO_PHYS_ADDR 0x500000000ULL
399 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
400 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
401 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
402 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
403 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
406 /***********************************************************************/
408 #ifdef CONFIG_SOC_AU1200
409 #define MEM_PHYS_ADDR 0x14000000
410 #define STATIC_MEM_PHYS_ADDR 0x14001000
411 #define AES_PHYS_ADDR 0x10300000
412 #define CIM_PHYS_ADDR 0x14004000
413 #define IC0_PHYS_ADDR 0x10400000
414 #define IC1_PHYS_ADDR 0x11800000
415 #define USBM_PHYS_ADDR 0x14020000
416 #define USBH_PHYS_ADDR 0x14020100
417 #define UART0_PHYS_ADDR 0x11100000
418 #define UART1_PHYS_ADDR 0x11200000
419 #define GPIO2_PHYS_ADDR 0x11700000
420 #define SYS_PHYS_ADDR 0x11900000
421 #define DDMA_PHYS_ADDR 0x14002000
422 #define PSC0_PHYS_ADDR 0x11A00000
423 #define PSC1_PHYS_ADDR 0x11B00000
424 #define SD0_PHYS_ADDR 0x10600000
425 #define SD1_PHYS_ADDR 0x10680000
426 #define LCD_PHYS_ADDR 0x15000000
427 #define SWCNT_PHYS_ADDR 0x1110010C
428 #define MAEFE_PHYS_ADDR 0x14012000
429 #define MAEBE_PHYS_ADDR 0x14010000
430 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
431 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
432 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
435 /* Static Bus Controller */
436 #define MEM_STCFG0 0xB4001000
437 #define MEM_STTIME0 0xB4001004
438 #define MEM_STADDR0 0xB4001008
440 #define MEM_STCFG1 0xB4001010
441 #define MEM_STTIME1 0xB4001014
442 #define MEM_STADDR1 0xB4001018
444 #define MEM_STCFG2 0xB4001020
445 #define MEM_STTIME2 0xB4001024
446 #define MEM_STADDR2 0xB4001028
448 #define MEM_STCFG3 0xB4001030
449 #define MEM_STTIME3 0xB4001034
450 #define MEM_STADDR3 0xB4001038
452 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
453 #define MEM_STNDCTL 0xB4001100
454 #define MEM_STSTAT 0xB4001104
456 #define MEM_STNAND_CMD 0x0
457 #define MEM_STNAND_ADDR 0x4
458 #define MEM_STNAND_DATA 0x20
461 /* Interrupt Controller 0 */
462 #define IC0_CFG0RD 0xB0400040
463 #define IC0_CFG0SET 0xB0400040
464 #define IC0_CFG0CLR 0xB0400044
466 #define IC0_CFG1RD 0xB0400048
467 #define IC0_CFG1SET 0xB0400048
468 #define IC0_CFG1CLR 0xB040004C
470 #define IC0_CFG2RD 0xB0400050
471 #define IC0_CFG2SET 0xB0400050
472 #define IC0_CFG2CLR 0xB0400054
474 #define IC0_REQ0INT 0xB0400054
475 #define IC0_SRCRD 0xB0400058
476 #define IC0_SRCSET 0xB0400058
477 #define IC0_SRCCLR 0xB040005C
478 #define IC0_REQ1INT 0xB040005C
480 #define IC0_ASSIGNRD 0xB0400060
481 #define IC0_ASSIGNSET 0xB0400060
482 #define IC0_ASSIGNCLR 0xB0400064
484 #define IC0_WAKERD 0xB0400068
485 #define IC0_WAKESET 0xB0400068
486 #define IC0_WAKECLR 0xB040006C
488 #define IC0_MASKRD 0xB0400070
489 #define IC0_MASKSET 0xB0400070
490 #define IC0_MASKCLR 0xB0400074
492 #define IC0_RISINGRD 0xB0400078
493 #define IC0_RISINGCLR 0xB0400078
494 #define IC0_FALLINGRD 0xB040007C
495 #define IC0_FALLINGCLR 0xB040007C
497 #define IC0_TESTBIT 0xB0400080
499 /* Interrupt Controller 1 */
500 #define IC1_CFG0RD 0xB1800040
501 #define IC1_CFG0SET 0xB1800040
502 #define IC1_CFG0CLR 0xB1800044
504 #define IC1_CFG1RD 0xB1800048
505 #define IC1_CFG1SET 0xB1800048
506 #define IC1_CFG1CLR 0xB180004C
508 #define IC1_CFG2RD 0xB1800050
509 #define IC1_CFG2SET 0xB1800050
510 #define IC1_CFG2CLR 0xB1800054
512 #define IC1_REQ0INT 0xB1800054
513 #define IC1_SRCRD 0xB1800058
514 #define IC1_SRCSET 0xB1800058
515 #define IC1_SRCCLR 0xB180005C
516 #define IC1_REQ1INT 0xB180005C
518 #define IC1_ASSIGNRD 0xB1800060
519 #define IC1_ASSIGNSET 0xB1800060
520 #define IC1_ASSIGNCLR 0xB1800064
522 #define IC1_WAKERD 0xB1800068
523 #define IC1_WAKESET 0xB1800068
524 #define IC1_WAKECLR 0xB180006C
526 #define IC1_MASKRD 0xB1800070
527 #define IC1_MASKSET 0xB1800070
528 #define IC1_MASKCLR 0xB1800074
530 #define IC1_RISINGRD 0xB1800078
531 #define IC1_RISINGCLR 0xB1800078
532 #define IC1_FALLINGRD 0xB180007C
533 #define IC1_FALLINGCLR 0xB180007C
535 #define IC1_TESTBIT 0xB1800080
537 /* Interrupt Numbers */
539 #ifdef CONFIG_SOC_AU1000
540 enum soc_au1000_ints {
541 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
542 AU1000_UART0_INT = AU1000_FIRST_INT,
543 AU1000_UART1_INT, /* au1000 */
544 AU1000_UART2_INT, /* au1000 */
546 AU1000_SSI0_INT, /* au1000 */
547 AU1000_SSI1_INT, /* au1000 */
550 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
551 AU1000_TOY_MATCH0_INT,
552 AU1000_TOY_MATCH1_INT,
553 AU1000_TOY_MATCH2_INT,
555 AU1000_RTC_MATCH0_INT,
556 AU1000_RTC_MATCH1_INT,
557 AU1000_RTC_MATCH2_INT,
558 AU1000_IRDA_TX_INT, /* au1000 */
559 AU1000_IRDA_RX_INT, /* au1000 */
560 AU1000_USB_DEV_REQ_INT,
561 AU1000_USB_DEV_SUS_INT,
566 AU1000_I2S_UO_INT, /* au1000 */
602 #define UART0_ADDR 0xB1100000
603 #define UART1_ADDR 0xB1200000
604 #define UART2_ADDR 0xB1300000
605 #define UART3_ADDR 0xB1400000
607 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
608 #define USB_HOST_CONFIG 0xB017FFFC
610 #define AU1000_ETH0_BASE 0xB0500000
611 #define AU1000_ETH1_BASE 0xB0510000
612 #define AU1000_MAC0_ENABLE 0xB0520000
613 #define AU1000_MAC1_ENABLE 0xB0520004
614 #define NUM_ETH_INTERFACES 2
615 #endif /* CONFIG_SOC_AU1000 */
618 #ifdef CONFIG_SOC_AU1500
619 enum soc_au1500_ints {
620 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
621 AU1500_UART0_INT = AU1500_FIRST_INT,
622 AU1000_PCI_INTA, /* au1500 */
623 AU1000_PCI_INTB, /* au1500 */
625 AU1000_PCI_INTC, /* au1500 */
626 AU1000_PCI_INTD, /* au1500 */
629 AU1000_TOY_INT = AU1500_FIRST_INT + 14,
630 AU1000_TOY_MATCH0_INT,
631 AU1000_TOY_MATCH1_INT,
632 AU1000_TOY_MATCH2_INT,
634 AU1000_RTC_MATCH0_INT,
635 AU1000_RTC_MATCH1_INT,
636 AU1000_RTC_MATCH2_INT,
639 AU1000_USB_DEV_REQ_INT,
640 AU1000_USB_DEV_SUS_INT,
645 AU1000_AC97C_INT = AU1500_FIRST_INT + 31,
681 #define INTA AU1000_PCI_INTA
682 #define INTB AU1000_PCI_INTB
683 #define INTC AU1000_PCI_INTC
684 #define INTD AU1000_PCI_INTD
686 #define UART0_ADDR 0xB1100000
687 #define UART3_ADDR 0xB1400000
689 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
690 #define USB_HOST_CONFIG 0xB017fffc
692 #define AU1500_ETH0_BASE 0xB1500000
693 #define AU1500_ETH1_BASE 0xB1510000
694 #define AU1500_MAC0_ENABLE 0xB1520000
695 #define AU1500_MAC1_ENABLE 0xB1520004
696 #define NUM_ETH_INTERFACES 2
697 #endif /* CONFIG_SOC_AU1500 */
700 #ifdef CONFIG_SOC_AU1100
701 enum soc_au1100_ints {
702 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
703 AU1100_UART0_INT = AU1100_FIRST_INT,
711 AU1000_TOY_INT = AU1100_FIRST_INT + 14,
712 AU1000_TOY_MATCH0_INT,
713 AU1000_TOY_MATCH1_INT,
714 AU1000_TOY_MATCH2_INT,
716 AU1000_RTC_MATCH0_INT,
717 AU1000_RTC_MATCH1_INT,
718 AU1000_RTC_MATCH2_INT,
721 AU1000_USB_DEV_REQ_INT,
722 AU1000_USB_DEV_SUS_INT,
763 #define UART0_ADDR 0xB1100000
764 #define UART1_ADDR 0xB1200000
765 #define UART3_ADDR 0xB1400000
767 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
768 #define USB_HOST_CONFIG 0xB017FFFC
770 #define AU1100_ETH0_BASE 0xB0500000
771 #define AU1100_MAC0_ENABLE 0xB0520000
772 #define NUM_ETH_INTERFACES 1
773 #endif /* CONFIG_SOC_AU1100 */
775 #ifdef CONFIG_SOC_AU1550
776 enum soc_au1550_ints {
777 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
778 AU1550_UART0_INT = AU1550_FIRST_INT,
793 AU1000_TOY_MATCH0_INT,
794 AU1000_TOY_MATCH1_INT,
795 AU1000_TOY_MATCH2_INT,
797 AU1000_RTC_MATCH0_INT,
798 AU1000_RTC_MATCH1_INT,
799 AU1000_RTC_MATCH2_INT,
801 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
802 AU1550_USB_DEV_REQ_INT,
803 AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT,
804 AU1550_USB_DEV_SUS_INT,
805 AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT,
807 AU1000_USB_HOST_INT = AU1550_USB_HOST_INT,
810 AU1000_GPIO_0 = AU1550_FIRST_INT + 32,
827 AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */
841 AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */
845 #define INTA AU1550_PCI_INTA
846 #define INTB AU1550_PCI_INTB
847 #define INTC AU1550_PCI_INTC
848 #define INTD AU1550_PCI_INTD
850 #define UART0_ADDR 0xB1100000
851 #define UART1_ADDR 0xB1200000
852 #define UART3_ADDR 0xB1400000
854 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
855 #define USB_OHCI_LEN 0x00060000
856 #define USB_HOST_CONFIG 0xB4027ffc
858 #define AU1550_ETH0_BASE 0xB0500000
859 #define AU1550_ETH1_BASE 0xB0510000
860 #define AU1550_MAC0_ENABLE 0xB0520000
861 #define AU1550_MAC1_ENABLE 0xB0520004
862 #define NUM_ETH_INTERFACES 2
863 #endif /* CONFIG_SOC_AU1550 */
865 #ifdef CONFIG_SOC_AU1200
866 enum soc_au1200_ints {
867 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
868 AU1200_UART0_INT = AU1200_FIRST_INT,
883 AU1000_TOY_MATCH0_INT,
884 AU1000_TOY_MATCH1_INT,
885 AU1000_TOY_MATCH2_INT,
887 AU1000_RTC_MATCH0_INT,
888 AU1000_RTC_MATCH1_INT,
889 AU1000_RTC_MATCH2_INT,
896 AU1200_GPIO_208_215, /* Logical OR of 208:215 */
898 AU1000_USB_HOST_INT = AU1200_USB_INT,
935 #define UART0_ADDR 0xB1100000
936 #define UART1_ADDR 0xB1200000
938 #define USB_UOC_BASE 0x14020020
939 #define USB_UOC_LEN 0x20
940 #define USB_OHCI_BASE 0x14020100
941 #define USB_OHCI_LEN 0x100
942 #define USB_EHCI_BASE 0x14020200
943 #define USB_EHCI_LEN 0x100
944 #define USB_UDC_BASE 0x14022000
945 #define USB_UDC_LEN 0x2000
946 #define USB_MSR_BASE 0xB4020000
947 #define USB_MSR_MCFG 4
948 #define USBMSRMCFG_OMEMEN 0
949 #define USBMSRMCFG_OBMEN 1
950 #define USBMSRMCFG_EMEMEN 2
951 #define USBMSRMCFG_EBMEN 3
952 #define USBMSRMCFG_DMEMEN 4
953 #define USBMSRMCFG_DBMEN 5
954 #define USBMSRMCFG_GMEMEN 6
955 #define USBMSRMCFG_OHCCLKEN 16
956 #define USBMSRMCFG_EHCCLKEN 17
957 #define USBMSRMCFG_UDCCLKEN 18
958 #define USBMSRMCFG_PHYPLLEN 19
959 #define USBMSRMCFG_RDCOMB 30
960 #define USBMSRMCFG_PFEN 31
962 #endif /* CONFIG_SOC_AU1200 */
964 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
965 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
966 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
967 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
969 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
970 #define INTX 0xFF /* not valid */
972 /* Programmable Counters 0 and 1 */
973 #define SYS_BASE 0xB1900000
974 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
975 # define SYS_CNTRL_E1S (1 << 23)
976 # define SYS_CNTRL_T1S (1 << 20)
977 # define SYS_CNTRL_M21 (1 << 19)
978 # define SYS_CNTRL_M11 (1 << 18)
979 # define SYS_CNTRL_M01 (1 << 17)
980 # define SYS_CNTRL_C1S (1 << 16)
981 # define SYS_CNTRL_BP (1 << 14)
982 # define SYS_CNTRL_EN1 (1 << 13)
983 # define SYS_CNTRL_BT1 (1 << 12)
984 # define SYS_CNTRL_EN0 (1 << 11)
985 # define SYS_CNTRL_BT0 (1 << 10)
986 # define SYS_CNTRL_E0 (1 << 8)
987 # define SYS_CNTRL_E0S (1 << 7)
988 # define SYS_CNTRL_32S (1 << 5)
989 # define SYS_CNTRL_T0S (1 << 4)
990 # define SYS_CNTRL_M20 (1 << 3)
991 # define SYS_CNTRL_M10 (1 << 2)
992 # define SYS_CNTRL_M00 (1 << 1)
993 # define SYS_CNTRL_C0S (1 << 0)
995 /* Programmable Counter 0 Registers */
996 #define SYS_TOYTRIM (SYS_BASE + 0)
997 #define SYS_TOYWRITE (SYS_BASE + 4)
998 #define SYS_TOYMATCH0 (SYS_BASE + 8)
999 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
1000 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
1001 #define SYS_TOYREAD (SYS_BASE + 0x40)
1003 /* Programmable Counter 1 Registers */
1004 #define SYS_RTCTRIM (SYS_BASE + 0x44)
1005 #define SYS_RTCWRITE (SYS_BASE + 0x48)
1006 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
1007 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
1008 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
1009 #define SYS_RTCREAD (SYS_BASE + 0x58)
1011 /* I2S Controller */
1012 #define I2S_DATA 0xB1000000
1013 # define I2S_DATA_MASK 0xffffff
1014 #define I2S_CONFIG 0xB1000004
1015 # define I2S_CONFIG_XU (1 << 25)
1016 # define I2S_CONFIG_XO (1 << 24)
1017 # define I2S_CONFIG_RU (1 << 23)
1018 # define I2S_CONFIG_RO (1 << 22)
1019 # define I2S_CONFIG_TR (1 << 21)
1020 # define I2S_CONFIG_TE (1 << 20)
1021 # define I2S_CONFIG_TF (1 << 19)
1022 # define I2S_CONFIG_RR (1 << 18)
1023 # define I2S_CONFIG_RE (1 << 17)
1024 # define I2S_CONFIG_RF (1 << 16)
1025 # define I2S_CONFIG_PD (1 << 11)
1026 # define I2S_CONFIG_LB (1 << 10)
1027 # define I2S_CONFIG_IC (1 << 9)
1028 # define I2S_CONFIG_FM_BIT 7
1029 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1030 # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1031 # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1032 # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1033 # define I2S_CONFIG_TN (1 << 6)
1034 # define I2S_CONFIG_RN (1 << 5)
1035 # define I2S_CONFIG_SZ_BIT 0
1036 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1038 #define I2S_CONTROL 0xB1000008
1039 # define I2S_CONTROL_D (1 << 1)
1040 # define I2S_CONTROL_CE (1 << 0)
1042 /* USB Host Controller */
1043 #ifndef USB_OHCI_LEN
1044 #define USB_OHCI_LEN 0x00100000
1047 #ifndef CONFIG_SOC_AU1200
1049 /* USB Device Controller */
1050 #define USBD_EP0RD 0xB0200000
1051 #define USBD_EP0WR 0xB0200004
1052 #define USBD_EP2WR 0xB0200008
1053 #define USBD_EP3WR 0xB020000C
1054 #define USBD_EP4RD 0xB0200010
1055 #define USBD_EP5RD 0xB0200014
1056 #define USBD_INTEN 0xB0200018
1057 #define USBD_INTSTAT 0xB020001C
1058 # define USBDEV_INT_SOF (1 << 12)
1059 # define USBDEV_INT_HF_BIT 6
1060 # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1061 # define USBDEV_INT_CMPLT_BIT 0
1062 # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1063 #define USBD_CONFIG 0xB0200020
1064 #define USBD_EP0CS 0xB0200024
1065 #define USBD_EP2CS 0xB0200028
1066 #define USBD_EP3CS 0xB020002C
1067 #define USBD_EP4CS 0xB0200030
1068 #define USBD_EP5CS 0xB0200034
1069 # define USBDEV_CS_SU (1 << 14)
1070 # define USBDEV_CS_NAK (1 << 13)
1071 # define USBDEV_CS_ACK (1 << 12)
1072 # define USBDEV_CS_BUSY (1 << 11)
1073 # define USBDEV_CS_TSIZE_BIT 1
1074 # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1075 # define USBDEV_CS_STALL (1 << 0)
1076 #define USBD_EP0RDSTAT 0xB0200040
1077 #define USBD_EP0WRSTAT 0xB0200044
1078 #define USBD_EP2WRSTAT 0xB0200048
1079 #define USBD_EP3WRSTAT 0xB020004C
1080 #define USBD_EP4RDSTAT 0xB0200050
1081 #define USBD_EP5RDSTAT 0xB0200054
1082 # define USBDEV_FSTAT_FLUSH (1 << 6)
1083 # define USBDEV_FSTAT_UF (1 << 5)
1084 # define USBDEV_FSTAT_OF (1 << 4)
1085 # define USBDEV_FSTAT_FCNT_BIT 0
1086 # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1087 #define USBD_ENABLE 0xB0200058
1088 # define USBDEV_ENABLE (1 << 1)
1089 # define USBDEV_CE (1 << 0)
1091 #endif /* !CONFIG_SOC_AU1200 */
1093 /* Ethernet Controllers */
1095 /* 4 byte offsets from AU1000_ETH_BASE */
1096 #define MAC_CONTROL 0x0
1097 # define MAC_RX_ENABLE (1 << 2)
1098 # define MAC_TX_ENABLE (1 << 3)
1099 # define MAC_DEF_CHECK (1 << 5)
1100 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
1101 # define MAC_AUTO_PAD (1 << 8)
1102 # define MAC_DISABLE_RETRY (1 << 10)
1103 # define MAC_DISABLE_BCAST (1 << 11)
1104 # define MAC_LATE_COL (1 << 12)
1105 # define MAC_HASH_MODE (1 << 13)
1106 # define MAC_HASH_ONLY (1 << 15)
1107 # define MAC_PASS_ALL (1 << 16)
1108 # define MAC_INVERSE_FILTER (1 << 17)
1109 # define MAC_PROMISCUOUS (1 << 18)
1110 # define MAC_PASS_ALL_MULTI (1 << 19)
1111 # define MAC_FULL_DUPLEX (1 << 20)
1112 # define MAC_NORMAL_MODE 0
1113 # define MAC_INT_LOOPBACK (1 << 21)
1114 # define MAC_EXT_LOOPBACK (1 << 22)
1115 # define MAC_DISABLE_RX_OWN (1 << 23)
1116 # define MAC_BIG_ENDIAN (1 << 30)
1117 # define MAC_RX_ALL (1 << 31)
1118 #define MAC_ADDRESS_HIGH 0x4
1119 #define MAC_ADDRESS_LOW 0x8
1120 #define MAC_MCAST_HIGH 0xC
1121 #define MAC_MCAST_LOW 0x10
1122 #define MAC_MII_CNTRL 0x14
1123 # define MAC_MII_BUSY (1 << 0)
1124 # define MAC_MII_READ 0
1125 # define MAC_MII_WRITE (1 << 1)
1126 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1127 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1128 #define MAC_MII_DATA 0x18
1129 #define MAC_FLOW_CNTRL 0x1C
1130 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
1131 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1132 # define MAC_PASS_CONTROL (1 << 2)
1133 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1134 #define MAC_VLAN1_TAG 0x20
1135 #define MAC_VLAN2_TAG 0x24
1137 /* Ethernet Controller Enable */
1139 # define MAC_EN_CLOCK_ENABLE (1 << 0)
1140 # define MAC_EN_RESET0 (1 << 1)
1141 # define MAC_EN_TOSS (0 << 2)
1142 # define MAC_EN_CACHEABLE (1 << 3)
1143 # define MAC_EN_RESET1 (1 << 4)
1144 # define MAC_EN_RESET2 (1 << 5)
1145 # define MAC_DMA_RESET (1 << 6)
1147 /* Ethernet Controller DMA Channels */
1149 #define MAC0_TX_DMA_ADDR 0xB4004000
1150 #define MAC1_TX_DMA_ADDR 0xB4004200
1151 /* offsets from MAC_TX_RING_ADDR address */
1152 #define MAC_TX_BUFF0_STATUS 0x0
1153 # define TX_FRAME_ABORTED (1 << 0)
1154 # define TX_JAB_TIMEOUT (1 << 1)
1155 # define TX_NO_CARRIER (1 << 2)
1156 # define TX_LOSS_CARRIER (1 << 3)
1157 # define TX_EXC_DEF (1 << 4)
1158 # define TX_LATE_COLL_ABORT (1 << 5)
1159 # define TX_EXC_COLL (1 << 6)
1160 # define TX_UNDERRUN (1 << 7)
1161 # define TX_DEFERRED (1 << 8)
1162 # define TX_LATE_COLL (1 << 9)
1163 # define TX_COLL_CNT_MASK (0xF << 10)
1164 # define TX_PKT_RETRY (1 << 31)
1165 #define MAC_TX_BUFF0_ADDR 0x4
1166 # define TX_DMA_ENABLE (1 << 0)
1167 # define TX_T_DONE (1 << 1)
1168 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1169 #define MAC_TX_BUFF0_LEN 0x8
1170 #define MAC_TX_BUFF1_STATUS 0x10
1171 #define MAC_TX_BUFF1_ADDR 0x14
1172 #define MAC_TX_BUFF1_LEN 0x18
1173 #define MAC_TX_BUFF2_STATUS 0x20
1174 #define MAC_TX_BUFF2_ADDR 0x24
1175 #define MAC_TX_BUFF2_LEN 0x28
1176 #define MAC_TX_BUFF3_STATUS 0x30
1177 #define MAC_TX_BUFF3_ADDR 0x34
1178 #define MAC_TX_BUFF3_LEN 0x38
1180 #define MAC0_RX_DMA_ADDR 0xB4004100
1181 #define MAC1_RX_DMA_ADDR 0xB4004300
1182 /* offsets from MAC_RX_RING_ADDR */
1183 #define MAC_RX_BUFF0_STATUS 0x0
1184 # define RX_FRAME_LEN_MASK 0x3fff
1185 # define RX_WDOG_TIMER (1 << 14)
1186 # define RX_RUNT (1 << 15)
1187 # define RX_OVERLEN (1 << 16)
1188 # define RX_COLL (1 << 17)
1189 # define RX_ETHER (1 << 18)
1190 # define RX_MII_ERROR (1 << 19)
1191 # define RX_DRIBBLING (1 << 20)
1192 # define RX_CRC_ERROR (1 << 21)
1193 # define RX_VLAN1 (1 << 22)
1194 # define RX_VLAN2 (1 << 23)
1195 # define RX_LEN_ERROR (1 << 24)
1196 # define RX_CNTRL_FRAME (1 << 25)
1197 # define RX_U_CNTRL_FRAME (1 << 26)
1198 # define RX_MCAST_FRAME (1 << 27)
1199 # define RX_BCAST_FRAME (1 << 28)
1200 # define RX_FILTER_FAIL (1 << 29)
1201 # define RX_PACKET_FILTER (1 << 30)
1202 # define RX_MISSED_FRAME (1 << 31)
1204 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1205 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1206 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1207 #define MAC_RX_BUFF0_ADDR 0x4
1208 # define RX_DMA_ENABLE (1 << 0)
1209 # define RX_T_DONE (1 << 1)
1210 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1211 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1212 #define MAC_RX_BUFF1_STATUS 0x10
1213 #define MAC_RX_BUFF1_ADDR 0x14
1214 #define MAC_RX_BUFF2_STATUS 0x20
1215 #define MAC_RX_BUFF2_ADDR 0x24
1216 #define MAC_RX_BUFF3_STATUS 0x30
1217 #define MAC_RX_BUFF3_ADDR 0x34
1220 #define UART_BASE UART0_ADDR
1221 #ifdef CONFIG_SOC_AU1200
1222 #define UART_DEBUG_BASE UART1_ADDR
1224 #define UART_DEBUG_BASE UART3_ADDR
1227 #define UART_RX 0 /* Receive buffer */
1228 #define UART_TX 4 /* Transmit buffer */
1229 #define UART_IER 8 /* Interrupt Enable Register */
1230 #define UART_IIR 0xC /* Interrupt ID Register */
1231 #define UART_FCR 0x10 /* FIFO Control Register */
1232 #define UART_LCR 0x14 /* Line Control Register */
1233 #define UART_MCR 0x18 /* Modem Control Register */
1234 #define UART_LSR 0x1C /* Line Status Register */
1235 #define UART_MSR 0x20 /* Modem Status Register */
1236 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
1237 #define UART_MOD_CNTRL 0x100 /* Module Control */
1239 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1240 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1241 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1242 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1243 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1244 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1245 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1246 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1247 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1248 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1249 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1250 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1251 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1254 * These are the definitions for the Line Control Register
1256 #define UART_LCR_SBC 0x40 /* Set break control */
1257 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1258 #define UART_LCR_EPAR 0x10 /* Even parity select */
1259 #define UART_LCR_PARITY 0x08 /* Parity Enable */
1260 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1261 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1262 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1263 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1264 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1267 * These are the definitions for the Line Status Register
1269 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1270 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1271 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1272 #define UART_LSR_FE 0x08 /* Frame error indicator */
1273 #define UART_LSR_PE 0x04 /* Parity error indicator */
1274 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1275 #define UART_LSR_DR 0x01 /* Receiver data ready */
1278 * These are the definitions for the Interrupt Identification Register
1280 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1281 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1282 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1283 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1284 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1285 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1288 * These are the definitions for the Interrupt Enable Register
1290 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1291 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1292 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1293 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1296 * These are the definitions for the Modem Control Register
1298 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1299 #define UART_MCR_OUT2 0x08 /* Out2 complement */
1300 #define UART_MCR_OUT1 0x04 /* Out1 complement */
1301 #define UART_MCR_RTS 0x02 /* RTS complement */
1302 #define UART_MCR_DTR 0x01 /* DTR complement */
1305 * These are the definitions for the Modem Status Register
1307 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1308 #define UART_MSR_RI 0x40 /* Ring Indicator */
1309 #define UART_MSR_DSR 0x20 /* Data Set Ready */
1310 #define UART_MSR_CTS 0x10 /* Clear to Send */
1311 #define UART_MSR_DDCD 0x08 /* Delta DCD */
1312 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1313 #define UART_MSR_DDSR 0x02 /* Delta DSR */
1314 #define UART_MSR_DCTS 0x01 /* Delta CTS */
1315 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1318 #define SSI0_STATUS 0xB1600000
1319 # define SSI_STATUS_BF (1 << 4)
1320 # define SSI_STATUS_OF (1 << 3)
1321 # define SSI_STATUS_UF (1 << 2)
1322 # define SSI_STATUS_D (1 << 1)
1323 # define SSI_STATUS_B (1 << 0)
1324 #define SSI0_INT 0xB1600004
1325 # define SSI_INT_OI (1 << 3)
1326 # define SSI_INT_UI (1 << 2)
1327 # define SSI_INT_DI (1 << 1)
1328 #define SSI0_INT_ENABLE 0xB1600008
1329 # define SSI_INTE_OIE (1 << 3)
1330 # define SSI_INTE_UIE (1 << 2)
1331 # define SSI_INTE_DIE (1 << 1)
1332 #define SSI0_CONFIG 0xB1600020
1333 # define SSI_CONFIG_AO (1 << 24)
1334 # define SSI_CONFIG_DO (1 << 23)
1335 # define SSI_CONFIG_ALEN_BIT 20
1336 # define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1337 # define SSI_CONFIG_DLEN_BIT 16
1338 # define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1339 # define SSI_CONFIG_DD (1 << 11)
1340 # define SSI_CONFIG_AD (1 << 10)
1341 # define SSI_CONFIG_BM_BIT 8
1342 # define SSI_CONFIG_BM_MASK (0x3 << 8)
1343 # define SSI_CONFIG_CE (1 << 7)
1344 # define SSI_CONFIG_DP (1 << 6)
1345 # define SSI_CONFIG_DL (1 << 5)
1346 # define SSI_CONFIG_EP (1 << 4)
1347 #define SSI0_ADATA 0xB1600024
1348 # define SSI_AD_D (1 << 24)
1349 # define SSI_AD_ADDR_BIT 16
1350 # define SSI_AD_ADDR_MASK (0xff << 16)
1351 # define SSI_AD_DATA_BIT 0
1352 # define SSI_AD_DATA_MASK (0xfff << 0)
1353 #define SSI0_CLKDIV 0xB1600028
1354 #define SSI0_CONTROL 0xB1600100
1355 # define SSI_CONTROL_CD (1 << 1)
1356 # define SSI_CONTROL_E (1 << 0)
1359 #define SSI1_STATUS 0xB1680000
1360 #define SSI1_INT 0xB1680004
1361 #define SSI1_INT_ENABLE 0xB1680008
1362 #define SSI1_CONFIG 0xB1680020
1363 #define SSI1_ADATA 0xB1680024
1364 #define SSI1_CLKDIV 0xB1680028
1365 #define SSI1_ENABLE 0xB1680100
1368 * Register content definitions
1370 #define SSI_STATUS_BF (1 << 4)
1371 #define SSI_STATUS_OF (1 << 3)
1372 #define SSI_STATUS_UF (1 << 2)
1373 #define SSI_STATUS_D (1 << 1)
1374 #define SSI_STATUS_B (1 << 0)
1377 #define SSI_INT_OI (1 << 3)
1378 #define SSI_INT_UI (1 << 2)
1379 #define SSI_INT_DI (1 << 1)
1382 #define SSI_INTEN_OIE (1 << 3)
1383 #define SSI_INTEN_UIE (1 << 2)
1384 #define SSI_INTEN_DIE (1 << 1)
1386 #define SSI_CONFIG_AO (1 << 24)
1387 #define SSI_CONFIG_DO (1 << 23)
1388 #define SSI_CONFIG_ALEN (7 << 20)
1389 #define SSI_CONFIG_DLEN (15 << 16)
1390 #define SSI_CONFIG_DD (1 << 11)
1391 #define SSI_CONFIG_AD (1 << 10)
1392 #define SSI_CONFIG_BM (3 << 8)
1393 #define SSI_CONFIG_CE (1 << 7)
1394 #define SSI_CONFIG_DP (1 << 6)
1395 #define SSI_CONFIG_DL (1 << 5)
1396 #define SSI_CONFIG_EP (1 << 4)
1397 #define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1398 #define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1399 #define SSI_CONFIG_BM_HI (0 << 8)
1400 #define SSI_CONFIG_BM_LO (1 << 8)
1401 #define SSI_CONFIG_BM_CY (2 << 8)
1403 #define SSI_ADATA_D (1 << 24)
1404 #define SSI_ADATA_ADDR (0xFF << 16)
1405 #define SSI_ADATA_DATA 0x0FFF
1406 #define SSI_ADATA_ADDR_N(N) (N << 16)
1408 #define SSI_ENABLE_CD (1 << 1)
1409 #define SSI_ENABLE_E (1 << 0)
1411 /* IrDA Controller */
1412 #define IRDA_BASE 0xB0300000
1413 #define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1414 #define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1415 #define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1416 #define IR_RING_SIZE (IRDA_BASE + 0x0C)
1417 #define IR_RING_PROMPT (IRDA_BASE + 0x10)
1418 #define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1419 #define IR_INT_CLEAR (IRDA_BASE + 0x18)
1420 #define IR_CONFIG_1 (IRDA_BASE + 0x20)
1421 # define IR_RX_INVERT_LED (1 << 0)
1422 # define IR_TX_INVERT_LED (1 << 1)
1423 # define IR_ST (1 << 2)
1424 # define IR_SF (1 << 3)
1425 # define IR_SIR (1 << 4)
1426 # define IR_MIR (1 << 5)
1427 # define IR_FIR (1 << 6)
1428 # define IR_16CRC (1 << 7)
1429 # define IR_TD (1 << 8)
1430 # define IR_RX_ALL (1 << 9)
1431 # define IR_DMA_ENABLE (1 << 10)
1432 # define IR_RX_ENABLE (1 << 11)
1433 # define IR_TX_ENABLE (1 << 12)
1434 # define IR_LOOPBACK (1 << 14)
1435 # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1436 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1437 #define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1438 #define IR_ENABLE (IRDA_BASE + 0x28)
1439 # define IR_RX_STATUS (1 << 9)
1440 # define IR_TX_STATUS (1 << 10)
1441 #define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1442 #define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1443 #define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1444 #define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1445 #define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1446 # define IR_MODE_INV (1 << 0)
1447 # define IR_ONE_PIN (1 << 1)
1448 #define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1451 #define SYS_PINFUNC 0xB190002C
1452 # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1453 # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1454 # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1455 # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1456 # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1457 # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1458 # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1459 # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1460 # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1461 # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1462 # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1463 # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1464 # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1465 # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1466 # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1467 # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1470 # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1471 # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1472 # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1473 # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1475 /* Au1550 only. Redefines lots of pins */
1476 # define SYS_PF_PSC2_MASK (7 << 17)
1477 # define SYS_PF_PSC2_AC97 0
1478 # define SYS_PF_PSC2_SPI 0
1479 # define SYS_PF_PSC2_I2S (1 << 17)
1480 # define SYS_PF_PSC2_SMBUS (3 << 17)
1481 # define SYS_PF_PSC2_GPIO (7 << 17)
1482 # define SYS_PF_PSC3_MASK (7 << 20)
1483 # define SYS_PF_PSC3_AC97 0
1484 # define SYS_PF_PSC3_SPI 0
1485 # define SYS_PF_PSC3_I2S (1 << 20)
1486 # define SYS_PF_PSC3_SMBUS (3 << 20)
1487 # define SYS_PF_PSC3_GPIO (7 << 20)
1488 # define SYS_PF_PSC1_S1 (1 << 1)
1489 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1492 #ifdef CONFIG_SOC_AU1200
1493 #define SYS_PINFUNC_DMA (1 << 31)
1494 #define SYS_PINFUNC_S0A (1 << 30)
1495 #define SYS_PINFUNC_S1A (1 << 29)
1496 #define SYS_PINFUNC_LP0 (1 << 28)
1497 #define SYS_PINFUNC_LP1 (1 << 27)
1498 #define SYS_PINFUNC_LD16 (1 << 26)
1499 #define SYS_PINFUNC_LD8 (1 << 25)
1500 #define SYS_PINFUNC_LD1 (1 << 24)
1501 #define SYS_PINFUNC_LD0 (1 << 23)
1502 #define SYS_PINFUNC_P1A (3 << 21)
1503 #define SYS_PINFUNC_P1B (1 << 20)
1504 #define SYS_PINFUNC_FS3 (1 << 19)
1505 #define SYS_PINFUNC_P0A (3 << 17)
1506 #define SYS_PINFUNC_CS (1 << 16)
1507 #define SYS_PINFUNC_CIM (1 << 15)
1508 #define SYS_PINFUNC_P1C (1 << 14)
1509 #define SYS_PINFUNC_U1T (1 << 12)
1510 #define SYS_PINFUNC_U1R (1 << 11)
1511 #define SYS_PINFUNC_EX1 (1 << 10)
1512 #define SYS_PINFUNC_EX0 (1 << 9)
1513 #define SYS_PINFUNC_U0R (1 << 8)
1514 #define SYS_PINFUNC_MC (1 << 7)
1515 #define SYS_PINFUNC_S0B (1 << 6)
1516 #define SYS_PINFUNC_S0C (1 << 5)
1517 #define SYS_PINFUNC_P0B (1 << 4)
1518 #define SYS_PINFUNC_U0T (1 << 3)
1519 #define SYS_PINFUNC_S1B (1 << 2)
1522 #define SYS_TRIOUTRD 0xB1900100
1523 #define SYS_TRIOUTCLR 0xB1900100
1524 #define SYS_OUTPUTRD 0xB1900108
1525 #define SYS_OUTPUTSET 0xB1900108
1526 #define SYS_OUTPUTCLR 0xB190010C
1527 #define SYS_PINSTATERD 0xB1900110
1528 #define SYS_PININPUTEN 0xB1900110
1530 /* GPIO2, Au1500, Au1550 only */
1531 #define GPIO2_BASE 0xB1700000
1532 #define GPIO2_DIR (GPIO2_BASE + 0)
1533 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
1534 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1535 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1536 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1538 /* Power Management */
1539 #define SYS_SCRATCH0 0xB1900018
1540 #define SYS_SCRATCH1 0xB190001C
1541 #define SYS_WAKEMSK 0xB1900034
1542 #define SYS_ENDIAN 0xB1900038
1543 #define SYS_POWERCTRL 0xB190003C
1544 #define SYS_WAKESRC 0xB190005C
1545 #define SYS_SLPPWR 0xB1900078
1546 #define SYS_SLEEP 0xB190007C
1548 #define SYS_WAKEMSK_D2 (1 << 9)
1549 #define SYS_WAKEMSK_M2 (1 << 8)
1550 #define SYS_WAKEMSK_GPIO(x) (1 << (x))
1552 /* Clock Controller */
1553 #define SYS_FREQCTRL0 0xB1900020
1554 # define SYS_FC_FRDIV2_BIT 22
1555 # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1556 # define SYS_FC_FE2 (1 << 21)
1557 # define SYS_FC_FS2 (1 << 20)
1558 # define SYS_FC_FRDIV1_BIT 12
1559 # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1560 # define SYS_FC_FE1 (1 << 11)
1561 # define SYS_FC_FS1 (1 << 10)
1562 # define SYS_FC_FRDIV0_BIT 2
1563 # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1564 # define SYS_FC_FE0 (1 << 1)
1565 # define SYS_FC_FS0 (1 << 0)
1566 #define SYS_FREQCTRL1 0xB1900024
1567 # define SYS_FC_FRDIV5_BIT 22
1568 # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1569 # define SYS_FC_FE5 (1 << 21)
1570 # define SYS_FC_FS5 (1 << 20)
1571 # define SYS_FC_FRDIV4_BIT 12
1572 # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1573 # define SYS_FC_FE4 (1 << 11)
1574 # define SYS_FC_FS4 (1 << 10)
1575 # define SYS_FC_FRDIV3_BIT 2
1576 # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1577 # define SYS_FC_FE3 (1 << 1)
1578 # define SYS_FC_FS3 (1 << 0)
1579 #define SYS_CLKSRC 0xB1900028
1580 # define SYS_CS_ME1_BIT 27
1581 # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1582 # define SYS_CS_DE1 (1 << 26)
1583 # define SYS_CS_CE1 (1 << 25)
1584 # define SYS_CS_ME0_BIT 22
1585 # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1586 # define SYS_CS_DE0 (1 << 21)
1587 # define SYS_CS_CE0 (1 << 20)
1588 # define SYS_CS_MI2_BIT 17
1589 # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1590 # define SYS_CS_DI2 (1 << 16)
1591 # define SYS_CS_CI2 (1 << 15)
1592 #ifdef CONFIG_SOC_AU1100
1593 # define SYS_CS_ML_BIT 7
1594 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1595 # define SYS_CS_DL (1 << 6)
1596 # define SYS_CS_CL (1 << 5)
1598 # define SYS_CS_MUH_BIT 12
1599 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1600 # define SYS_CS_DUH (1 << 11)
1601 # define SYS_CS_CUH (1 << 10)
1602 # define SYS_CS_MUD_BIT 7
1603 # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1604 # define SYS_CS_DUD (1 << 6)
1605 # define SYS_CS_CUD (1 << 5)
1607 # define SYS_CS_MIR_BIT 2
1608 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1609 # define SYS_CS_DIR (1 << 1)
1610 # define SYS_CS_CIR (1 << 0)
1612 # define SYS_CS_MUX_AUX 0x1
1613 # define SYS_CS_MUX_FQ0 0x2
1614 # define SYS_CS_MUX_FQ1 0x3
1615 # define SYS_CS_MUX_FQ2 0x4
1616 # define SYS_CS_MUX_FQ3 0x5
1617 # define SYS_CS_MUX_FQ4 0x6
1618 # define SYS_CS_MUX_FQ5 0x7
1619 #define SYS_CPUPLL 0xB1900060
1620 #define SYS_AUXPLL 0xB1900064
1622 /* AC97 Controller */
1623 #define AC97C_CONFIG 0xB0000000
1624 # define AC97C_RECV_SLOTS_BIT 13
1625 # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1626 # define AC97C_XMIT_SLOTS_BIT 3
1627 # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1628 # define AC97C_SG (1 << 2)
1629 # define AC97C_SYNC (1 << 1)
1630 # define AC97C_RESET (1 << 0)
1631 #define AC97C_STATUS 0xB0000004
1632 # define AC97C_XU (1 << 11)
1633 # define AC97C_XO (1 << 10)
1634 # define AC97C_RU (1 << 9)
1635 # define AC97C_RO (1 << 8)
1636 # define AC97C_READY (1 << 7)
1637 # define AC97C_CP (1 << 6)
1638 # define AC97C_TR (1 << 5)
1639 # define AC97C_TE (1 << 4)
1640 # define AC97C_TF (1 << 3)
1641 # define AC97C_RR (1 << 2)
1642 # define AC97C_RE (1 << 1)
1643 # define AC97C_RF (1 << 0)
1644 #define AC97C_DATA 0xB0000008
1645 #define AC97C_CMD 0xB000000C
1646 # define AC97C_WD_BIT 16
1647 # define AC97C_READ (1 << 7)
1648 # define AC97C_INDEX_MASK 0x7f
1649 #define AC97C_CNTRL 0xB0000010
1650 # define AC97C_RS (1 << 1)
1651 # define AC97C_CE (1 << 0)
1653 /* Secure Digital (SD) Controller */
1654 #define SD0_XMIT_FIFO 0xB0600000
1655 #define SD0_RECV_FIFO 0xB0600004
1656 #define SD1_XMIT_FIFO 0xB0680000
1657 #define SD1_RECV_FIFO 0xB0680004
1659 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1660 /* Au1500 PCI Controller */
1661 #define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1662 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1663 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1664 # define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1665 (1 << 25) | (1 << 26) | (1 << 27))
1666 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1667 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1668 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1669 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1670 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1671 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1672 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1673 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1674 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1675 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1676 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1677 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1679 #define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1682 * All of our structures, like PCI resource, have 32-bit members.
1683 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1684 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1685 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1686 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1687 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1688 * ourselves and then adjust the device's resources.
1690 #define Au1500_EXT_CFG 0x600000000ULL
1691 #define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1692 #define Au1500_PCI_IO_START 0x500000000ULL
1693 #define Au1500_PCI_IO_END 0x5000FFFFFULL
1694 #define Au1500_PCI_MEM_START 0x440000000ULL
1695 #define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1697 #define PCI_IO_START 0x00001000
1698 #define PCI_IO_END 0x000FFFFF
1699 #define PCI_MEM_START 0x40000000
1700 #define PCI_MEM_END 0x4FFFFFFF
1702 #define PCI_FIRST_DEVFN (0 << 3)
1703 #define PCI_LAST_DEVFN (19 << 3)
1705 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1706 #define IOPORT_RESOURCE_END 0xffffffff
1707 #define IOMEM_RESOURCE_START 0x10000000
1708 #define IOMEM_RESOURCE_END 0xffffffff
1710 #else /* Au1000 and Au1100 and Au1200 */
1712 /* Don't allow any legacy ports probing */
1713 #define IOPORT_RESOURCE_START 0x10000000
1714 #define IOPORT_RESOURCE_END 0xffffffff
1715 #define IOMEM_RESOURCE_START 0x10000000
1716 #define IOMEM_RESOURCE_END 0xffffffff
1718 #define PCI_IO_START 0
1719 #define PCI_IO_END 0
1720 #define PCI_MEM_START 0
1721 #define PCI_MEM_END 0
1722 #define PCI_FIRST_DEVFN 0
1723 #define PCI_LAST_DEVFN 0
1727 #ifndef _LANGUAGE_ASSEMBLY
1728 typedef volatile struct {
1729 /* 0x0000 */ u32 toytrim;
1730 /* 0x0004 */ u32 toywrite;
1731 /* 0x0008 */ u32 toymatch0;
1732 /* 0x000C */ u32 toymatch1;
1733 /* 0x0010 */ u32 toymatch2;
1734 /* 0x0014 */ u32 cntrctrl;
1735 /* 0x0018 */ u32 scratch0;
1736 /* 0x001C */ u32 scratch1;
1737 /* 0x0020 */ u32 freqctrl0;
1738 /* 0x0024 */ u32 freqctrl1;
1739 /* 0x0028 */ u32 clksrc;
1740 /* 0x002C */ u32 pinfunc;
1741 /* 0x0030 */ u32 reserved0;
1742 /* 0x0034 */ u32 wakemsk;
1743 /* 0x0038 */ u32 endian;
1744 /* 0x003C */ u32 powerctrl;
1745 /* 0x0040 */ u32 toyread;
1746 /* 0x0044 */ u32 rtctrim;
1747 /* 0x0048 */ u32 rtcwrite;
1748 /* 0x004C */ u32 rtcmatch0;
1749 /* 0x0050 */ u32 rtcmatch1;
1750 /* 0x0054 */ u32 rtcmatch2;
1751 /* 0x0058 */ u32 rtcread;
1752 /* 0x005C */ u32 wakesrc;
1753 /* 0x0060 */ u32 cpupll;
1754 /* 0x0064 */ u32 auxpll;
1755 /* 0x0068 */ u32 reserved1;
1756 /* 0x006C */ u32 reserved2;
1757 /* 0x0070 */ u32 reserved3;
1758 /* 0x0074 */ u32 reserved4;
1759 /* 0x0078 */ u32 slppwr;
1760 /* 0x007C */ u32 sleep;
1761 /* 0x0080 */ u32 reserved5[32];
1762 /* 0x0100 */ u32 trioutrd;
1763 #define trioutclr trioutrd
1764 /* 0x0104 */ u32 reserved6;
1765 /* 0x0108 */ u32 outputrd;
1766 #define outputset outputrd
1767 /* 0x010C */ u32 outputclr;
1768 /* 0x0110 */ u32 pinstaterd;
1769 #define pininputen pinstaterd
1772 static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;