3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
38 #ifndef _LANGUAGE_ASSEMBLY
40 #include <linux/delay.h>
41 #include <linux/types.h>
44 #include <linux/irq.h>
46 /* cpu pipeline flush */
47 void static inline au_sync(void)
49 __asm__ volatile ("sync");
52 void static inline au_sync_udelay(int us)
54 __asm__ volatile ("sync");
58 void static inline au_sync_delay(int ms)
60 __asm__ volatile ("sync");
64 void static inline au_writeb(u8 val, unsigned long reg)
66 *(volatile u8 *)reg = val;
69 void static inline au_writew(u16 val, unsigned long reg)
71 *(volatile u16 *)reg = val;
74 void static inline au_writel(u32 val, unsigned long reg)
76 *(volatile u32 *)reg = val;
79 static inline u8 au_readb(unsigned long reg)
81 return *(volatile u8 *)reg;
84 static inline u16 au_readw(unsigned long reg)
86 return *(volatile u16 *)reg;
89 static inline u32 au_readl(unsigned long reg)
91 return *(volatile u32 *)reg;
94 /* Early Au1000 have a write-only SYS_CPUPLL register. */
95 static inline int au1xxx_cpu_has_pll_wo(void)
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
106 /* does CPU need CONFIG[OD] set to fix tons of errata? */
107 static inline int au1xxx_cpu_needs_config_od(void)
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
133 #define ALCHEMY_CPU_UNKNOWN -1
134 #define ALCHEMY_CPU_AU1000 0
135 #define ALCHEMY_CPU_AU1500 1
136 #define ALCHEMY_CPU_AU1100 2
137 #define ALCHEMY_CPU_AU1550 3
138 #define ALCHEMY_CPU_AU1200 4
140 static inline int alchemy_get_cputype(void)
142 switch (read_c0_prid() & 0xffff0000) {
144 return ALCHEMY_CPU_AU1000;
147 return ALCHEMY_CPU_AU1500;
150 return ALCHEMY_CPU_AU1100;
153 return ALCHEMY_CPU_AU1550;
157 return ALCHEMY_CPU_AU1200;
161 return ALCHEMY_CPU_UNKNOWN;
164 /* arch/mips/au1000/common/clocks.c */
165 extern void set_au1x00_speed(unsigned int new_freq);
166 extern unsigned int get_au1x00_speed(void);
167 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
168 extern unsigned long get_au1x00_uart_baud_base(void);
169 extern unsigned long au1xxx_calc_clock(void);
171 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
172 void au1xxx_save_and_sleep(void);
174 void save_au1xxx_intctl(void);
175 void restore_au1xxx_intctl(void);
177 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
180 * SDRAM register offsets
182 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
183 defined(CONFIG_SOC_AU1100)
184 #define MEM_SDMODE0 0x0000
185 #define MEM_SDMODE1 0x0004
186 #define MEM_SDMODE2 0x0008
187 #define MEM_SDADDR0 0x000C
188 #define MEM_SDADDR1 0x0010
189 #define MEM_SDADDR2 0x0014
190 #define MEM_SDREFCFG 0x0018
191 #define MEM_SDPRECMD 0x001C
192 #define MEM_SDAUTOREF 0x0020
193 #define MEM_SDWRMD0 0x0024
194 #define MEM_SDWRMD1 0x0028
195 #define MEM_SDWRMD2 0x002C
196 #define MEM_SDSLEEP 0x0030
197 #define MEM_SDSMCKE 0x0034
200 * MEM_SDMODE register content definitions
202 #define MEM_SDMODE_F (1 << 22)
203 #define MEM_SDMODE_SR (1 << 21)
204 #define MEM_SDMODE_BS (1 << 20)
205 #define MEM_SDMODE_RS (3 << 18)
206 #define MEM_SDMODE_CS (7 << 15)
207 #define MEM_SDMODE_TRAS (15 << 11)
208 #define MEM_SDMODE_TMRD (3 << 9)
209 #define MEM_SDMODE_TWR (3 << 7)
210 #define MEM_SDMODE_TRP (3 << 5)
211 #define MEM_SDMODE_TRCD (3 << 3)
212 #define MEM_SDMODE_TCL (7 << 0)
214 #define MEM_SDMODE_BS_2Bank (0 << 20)
215 #define MEM_SDMODE_BS_4Bank (1 << 20)
216 #define MEM_SDMODE_RS_11Row (0 << 18)
217 #define MEM_SDMODE_RS_12Row (1 << 18)
218 #define MEM_SDMODE_RS_13Row (2 << 18)
219 #define MEM_SDMODE_RS_N(N) ((N) << 18)
220 #define MEM_SDMODE_CS_7Col (0 << 15)
221 #define MEM_SDMODE_CS_8Col (1 << 15)
222 #define MEM_SDMODE_CS_9Col (2 << 15)
223 #define MEM_SDMODE_CS_10Col (3 << 15)
224 #define MEM_SDMODE_CS_11Col (4 << 15)
225 #define MEM_SDMODE_CS_N(N) ((N) << 15)
226 #define MEM_SDMODE_TRAS_N(N) ((N) << 11)
227 #define MEM_SDMODE_TMRD_N(N) ((N) << 9)
228 #define MEM_SDMODE_TWR_N(N) ((N) << 7)
229 #define MEM_SDMODE_TRP_N(N) ((N) << 5)
230 #define MEM_SDMODE_TRCD_N(N) ((N) << 3)
231 #define MEM_SDMODE_TCL_N(N) ((N) << 0)
234 * MEM_SDADDR register contents definitions
236 #define MEM_SDADDR_E (1 << 20)
237 #define MEM_SDADDR_CSBA (0x03FF << 10)
238 #define MEM_SDADDR_CSMASK (0x03FF << 0)
239 #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
240 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
243 * MEM_SDREFCFG register content definitions
245 #define MEM_SDREFCFG_TRC (15 << 28)
246 #define MEM_SDREFCFG_TRPM (3 << 26)
247 #define MEM_SDREFCFG_E (1 << 25)
248 #define MEM_SDREFCFG_RE (0x1ffffff << 0)
249 #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
250 #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
251 #define MEM_SDREFCFG_REF_N(N) (N)
254 /***********************************************************************/
257 * Au1550 SDRAM Register Offsets
260 /***********************************************************************/
262 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
263 #define MEM_SDMODE0 0x0800
264 #define MEM_SDMODE1 0x0808
265 #define MEM_SDMODE2 0x0810
266 #define MEM_SDADDR0 0x0820
267 #define MEM_SDADDR1 0x0828
268 #define MEM_SDADDR2 0x0830
269 #define MEM_SDCONFIGA 0x0840
270 #define MEM_SDCONFIGB 0x0848
271 #define MEM_SDSTAT 0x0850
272 #define MEM_SDERRADDR 0x0858
273 #define MEM_SDSTRIDE0 0x0860
274 #define MEM_SDSTRIDE1 0x0868
275 #define MEM_SDSTRIDE2 0x0870
276 #define MEM_SDWRMD0 0x0880
277 #define MEM_SDWRMD1 0x0888
278 #define MEM_SDWRMD2 0x0890
279 #define MEM_SDPRECMD 0x08C0
280 #define MEM_SDAUTOREF 0x08C8
281 #define MEM_SDSREF 0x08D0
282 #define MEM_SDSLEEP MEM_SDSREF
287 * Physical base addresses for integrated peripherals
290 #ifdef CONFIG_SOC_AU1000
291 #define MEM_PHYS_ADDR 0x14000000
292 #define STATIC_MEM_PHYS_ADDR 0x14001000
293 #define DMA0_PHYS_ADDR 0x14002000
294 #define DMA1_PHYS_ADDR 0x14002100
295 #define DMA2_PHYS_ADDR 0x14002200
296 #define DMA3_PHYS_ADDR 0x14002300
297 #define DMA4_PHYS_ADDR 0x14002400
298 #define DMA5_PHYS_ADDR 0x14002500
299 #define DMA6_PHYS_ADDR 0x14002600
300 #define DMA7_PHYS_ADDR 0x14002700
301 #define IC0_PHYS_ADDR 0x10400000
302 #define IC1_PHYS_ADDR 0x11800000
303 #define AC97_PHYS_ADDR 0x10000000
304 #define USBH_PHYS_ADDR 0x10100000
305 #define USBD_PHYS_ADDR 0x10200000
306 #define IRDA_PHYS_ADDR 0x10300000
307 #define MAC0_PHYS_ADDR 0x10500000
308 #define MAC1_PHYS_ADDR 0x10510000
309 #define MACEN_PHYS_ADDR 0x10520000
310 #define MACDMA0_PHYS_ADDR 0x14004000
311 #define MACDMA1_PHYS_ADDR 0x14004200
312 #define I2S_PHYS_ADDR 0x11000000
313 #define UART0_PHYS_ADDR 0x11100000
314 #define UART1_PHYS_ADDR 0x11200000
315 #define UART2_PHYS_ADDR 0x11300000
316 #define UART3_PHYS_ADDR 0x11400000
317 #define SSI0_PHYS_ADDR 0x11600000
318 #define SSI1_PHYS_ADDR 0x11680000
319 #define SYS_PHYS_ADDR 0x11900000
320 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
321 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
322 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
325 /********************************************************************/
327 #ifdef CONFIG_SOC_AU1500
328 #define MEM_PHYS_ADDR 0x14000000
329 #define STATIC_MEM_PHYS_ADDR 0x14001000
330 #define DMA0_PHYS_ADDR 0x14002000
331 #define DMA1_PHYS_ADDR 0x14002100
332 #define DMA2_PHYS_ADDR 0x14002200
333 #define DMA3_PHYS_ADDR 0x14002300
334 #define DMA4_PHYS_ADDR 0x14002400
335 #define DMA5_PHYS_ADDR 0x14002500
336 #define DMA6_PHYS_ADDR 0x14002600
337 #define DMA7_PHYS_ADDR 0x14002700
338 #define IC0_PHYS_ADDR 0x10400000
339 #define IC1_PHYS_ADDR 0x11800000
340 #define AC97_PHYS_ADDR 0x10000000
341 #define USBH_PHYS_ADDR 0x10100000
342 #define USBD_PHYS_ADDR 0x10200000
343 #define PCI_PHYS_ADDR 0x14005000
344 #define MAC0_PHYS_ADDR 0x11500000
345 #define MAC1_PHYS_ADDR 0x11510000
346 #define MACEN_PHYS_ADDR 0x11520000
347 #define MACDMA0_PHYS_ADDR 0x14004000
348 #define MACDMA1_PHYS_ADDR 0x14004200
349 #define I2S_PHYS_ADDR 0x11000000
350 #define UART0_PHYS_ADDR 0x11100000
351 #define UART3_PHYS_ADDR 0x11400000
352 #define GPIO2_PHYS_ADDR 0x11700000
353 #define SYS_PHYS_ADDR 0x11900000
354 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
355 #define PCI_IO_PHYS_ADDR 0x500000000ULL
356 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
357 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
358 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
359 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
360 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
363 /********************************************************************/
365 #ifdef CONFIG_SOC_AU1100
366 #define MEM_PHYS_ADDR 0x14000000
367 #define STATIC_MEM_PHYS_ADDR 0x14001000
368 #define DMA0_PHYS_ADDR 0x14002000
369 #define DMA1_PHYS_ADDR 0x14002100
370 #define DMA2_PHYS_ADDR 0x14002200
371 #define DMA3_PHYS_ADDR 0x14002300
372 #define DMA4_PHYS_ADDR 0x14002400
373 #define DMA5_PHYS_ADDR 0x14002500
374 #define DMA6_PHYS_ADDR 0x14002600
375 #define DMA7_PHYS_ADDR 0x14002700
376 #define IC0_PHYS_ADDR 0x10400000
377 #define SD0_PHYS_ADDR 0x10600000
378 #define SD1_PHYS_ADDR 0x10680000
379 #define IC1_PHYS_ADDR 0x11800000
380 #define AC97_PHYS_ADDR 0x10000000
381 #define USBH_PHYS_ADDR 0x10100000
382 #define USBD_PHYS_ADDR 0x10200000
383 #define IRDA_PHYS_ADDR 0x10300000
384 #define MAC0_PHYS_ADDR 0x10500000
385 #define MACEN_PHYS_ADDR 0x10520000
386 #define MACDMA0_PHYS_ADDR 0x14004000
387 #define MACDMA1_PHYS_ADDR 0x14004200
388 #define I2S_PHYS_ADDR 0x11000000
389 #define UART0_PHYS_ADDR 0x11100000
390 #define UART1_PHYS_ADDR 0x11200000
391 #define UART3_PHYS_ADDR 0x11400000
392 #define SSI0_PHYS_ADDR 0x11600000
393 #define SSI1_PHYS_ADDR 0x11680000
394 #define GPIO2_PHYS_ADDR 0x11700000
395 #define SYS_PHYS_ADDR 0x11900000
396 #define LCD_PHYS_ADDR 0x15000000
397 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
398 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
399 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
402 /***********************************************************************/
404 #ifdef CONFIG_SOC_AU1550
405 #define MEM_PHYS_ADDR 0x14000000
406 #define STATIC_MEM_PHYS_ADDR 0x14001000
407 #define IC0_PHYS_ADDR 0x10400000
408 #define IC1_PHYS_ADDR 0x11800000
409 #define USBH_PHYS_ADDR 0x14020000
410 #define USBD_PHYS_ADDR 0x10200000
411 #define PCI_PHYS_ADDR 0x14005000
412 #define MAC0_PHYS_ADDR 0x10500000
413 #define MAC1_PHYS_ADDR 0x10510000
414 #define MACEN_PHYS_ADDR 0x10520000
415 #define MACDMA0_PHYS_ADDR 0x14004000
416 #define MACDMA1_PHYS_ADDR 0x14004200
417 #define UART0_PHYS_ADDR 0x11100000
418 #define UART1_PHYS_ADDR 0x11200000
419 #define UART3_PHYS_ADDR 0x11400000
420 #define GPIO2_PHYS_ADDR 0x11700000
421 #define SYS_PHYS_ADDR 0x11900000
422 #define DDMA_PHYS_ADDR 0x14002000
423 #define PE_PHYS_ADDR 0x14008000
424 #define PSC0_PHYS_ADDR 0x11A00000
425 #define PSC1_PHYS_ADDR 0x11B00000
426 #define PSC2_PHYS_ADDR 0x10A00000
427 #define PSC3_PHYS_ADDR 0x10B00000
428 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
429 #define PCI_IO_PHYS_ADDR 0x500000000ULL
430 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
431 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
432 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
433 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
434 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
437 /***********************************************************************/
439 #ifdef CONFIG_SOC_AU1200
440 #define MEM_PHYS_ADDR 0x14000000
441 #define STATIC_MEM_PHYS_ADDR 0x14001000
442 #define AES_PHYS_ADDR 0x10300000
443 #define CIM_PHYS_ADDR 0x14004000
444 #define IC0_PHYS_ADDR 0x10400000
445 #define IC1_PHYS_ADDR 0x11800000
446 #define USBM_PHYS_ADDR 0x14020000
447 #define USBH_PHYS_ADDR 0x14020100
448 #define UART0_PHYS_ADDR 0x11100000
449 #define UART1_PHYS_ADDR 0x11200000
450 #define GPIO2_PHYS_ADDR 0x11700000
451 #define SYS_PHYS_ADDR 0x11900000
452 #define DDMA_PHYS_ADDR 0x14002000
453 #define PSC0_PHYS_ADDR 0x11A00000
454 #define PSC1_PHYS_ADDR 0x11B00000
455 #define SD0_PHYS_ADDR 0x10600000
456 #define SD1_PHYS_ADDR 0x10680000
457 #define LCD_PHYS_ADDR 0x15000000
458 #define SWCNT_PHYS_ADDR 0x1110010C
459 #define MAEFE_PHYS_ADDR 0x14012000
460 #define MAEBE_PHYS_ADDR 0x14010000
461 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
462 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
463 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
466 /* Static Bus Controller */
467 #define MEM_STCFG0 0xB4001000
468 #define MEM_STTIME0 0xB4001004
469 #define MEM_STADDR0 0xB4001008
471 #define MEM_STCFG1 0xB4001010
472 #define MEM_STTIME1 0xB4001014
473 #define MEM_STADDR1 0xB4001018
475 #define MEM_STCFG2 0xB4001020
476 #define MEM_STTIME2 0xB4001024
477 #define MEM_STADDR2 0xB4001028
479 #define MEM_STCFG3 0xB4001030
480 #define MEM_STTIME3 0xB4001034
481 #define MEM_STADDR3 0xB4001038
483 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
484 #define MEM_STNDCTL 0xB4001100
485 #define MEM_STSTAT 0xB4001104
487 #define MEM_STNAND_CMD 0x0
488 #define MEM_STNAND_ADDR 0x4
489 #define MEM_STNAND_DATA 0x20
492 /* Interrupt Controller 0 */
493 #define IC0_CFG0RD 0xB0400040
494 #define IC0_CFG0SET 0xB0400040
495 #define IC0_CFG0CLR 0xB0400044
497 #define IC0_CFG1RD 0xB0400048
498 #define IC0_CFG1SET 0xB0400048
499 #define IC0_CFG1CLR 0xB040004C
501 #define IC0_CFG2RD 0xB0400050
502 #define IC0_CFG2SET 0xB0400050
503 #define IC0_CFG2CLR 0xB0400054
505 #define IC0_REQ0INT 0xB0400054
506 #define IC0_SRCRD 0xB0400058
507 #define IC0_SRCSET 0xB0400058
508 #define IC0_SRCCLR 0xB040005C
509 #define IC0_REQ1INT 0xB040005C
511 #define IC0_ASSIGNRD 0xB0400060
512 #define IC0_ASSIGNSET 0xB0400060
513 #define IC0_ASSIGNCLR 0xB0400064
515 #define IC0_WAKERD 0xB0400068
516 #define IC0_WAKESET 0xB0400068
517 #define IC0_WAKECLR 0xB040006C
519 #define IC0_MASKRD 0xB0400070
520 #define IC0_MASKSET 0xB0400070
521 #define IC0_MASKCLR 0xB0400074
523 #define IC0_RISINGRD 0xB0400078
524 #define IC0_RISINGCLR 0xB0400078
525 #define IC0_FALLINGRD 0xB040007C
526 #define IC0_FALLINGCLR 0xB040007C
528 #define IC0_TESTBIT 0xB0400080
530 /* Interrupt Controller 1 */
531 #define IC1_CFG0RD 0xB1800040
532 #define IC1_CFG0SET 0xB1800040
533 #define IC1_CFG0CLR 0xB1800044
535 #define IC1_CFG1RD 0xB1800048
536 #define IC1_CFG1SET 0xB1800048
537 #define IC1_CFG1CLR 0xB180004C
539 #define IC1_CFG2RD 0xB1800050
540 #define IC1_CFG2SET 0xB1800050
541 #define IC1_CFG2CLR 0xB1800054
543 #define IC1_REQ0INT 0xB1800054
544 #define IC1_SRCRD 0xB1800058
545 #define IC1_SRCSET 0xB1800058
546 #define IC1_SRCCLR 0xB180005C
547 #define IC1_REQ1INT 0xB180005C
549 #define IC1_ASSIGNRD 0xB1800060
550 #define IC1_ASSIGNSET 0xB1800060
551 #define IC1_ASSIGNCLR 0xB1800064
553 #define IC1_WAKERD 0xB1800068
554 #define IC1_WAKESET 0xB1800068
555 #define IC1_WAKECLR 0xB180006C
557 #define IC1_MASKRD 0xB1800070
558 #define IC1_MASKSET 0xB1800070
559 #define IC1_MASKCLR 0xB1800074
561 #define IC1_RISINGRD 0xB1800078
562 #define IC1_RISINGCLR 0xB1800078
563 #define IC1_FALLINGRD 0xB180007C
564 #define IC1_FALLINGCLR 0xB180007C
566 #define IC1_TESTBIT 0xB1800080
568 /* Interrupt Numbers */
570 #ifdef CONFIG_SOC_AU1000
571 enum soc_au1000_ints {
572 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
573 AU1000_UART0_INT = AU1000_FIRST_INT,
574 AU1000_UART1_INT, /* au1000 */
575 AU1000_UART2_INT, /* au1000 */
577 AU1000_SSI0_INT, /* au1000 */
578 AU1000_SSI1_INT, /* au1000 */
581 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
582 AU1000_TOY_MATCH0_INT,
583 AU1000_TOY_MATCH1_INT,
584 AU1000_TOY_MATCH2_INT,
586 AU1000_RTC_MATCH0_INT,
587 AU1000_RTC_MATCH1_INT,
588 AU1000_RTC_MATCH2_INT,
589 AU1000_IRDA_TX_INT, /* au1000 */
590 AU1000_IRDA_RX_INT, /* au1000 */
591 AU1000_USB_DEV_REQ_INT,
592 AU1000_USB_DEV_SUS_INT,
597 AU1000_I2S_UO_INT, /* au1000 */
633 #define UART0_ADDR 0xB1100000
634 #define UART1_ADDR 0xB1200000
635 #define UART2_ADDR 0xB1300000
636 #define UART3_ADDR 0xB1400000
638 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
639 #define USB_HOST_CONFIG 0xB017FFFC
641 #define AU1000_ETH0_BASE 0xB0500000
642 #define AU1000_ETH1_BASE 0xB0510000
643 #define AU1000_MAC0_ENABLE 0xB0520000
644 #define AU1000_MAC1_ENABLE 0xB0520004
645 #define NUM_ETH_INTERFACES 2
646 #endif /* CONFIG_SOC_AU1000 */
649 #ifdef CONFIG_SOC_AU1500
650 enum soc_au1500_ints {
651 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
652 AU1500_UART0_INT = AU1500_FIRST_INT,
653 AU1000_PCI_INTA, /* au1500 */
654 AU1000_PCI_INTB, /* au1500 */
656 AU1000_PCI_INTC, /* au1500 */
657 AU1000_PCI_INTD, /* au1500 */
660 AU1000_TOY_INT = AU1500_FIRST_INT + 14,
661 AU1000_TOY_MATCH0_INT,
662 AU1000_TOY_MATCH1_INT,
663 AU1000_TOY_MATCH2_INT,
665 AU1000_RTC_MATCH0_INT,
666 AU1000_RTC_MATCH1_INT,
667 AU1000_RTC_MATCH2_INT,
670 AU1000_USB_DEV_REQ_INT,
671 AU1000_USB_DEV_SUS_INT,
676 AU1000_AC97C_INT = AU1500_FIRST_INT + 31,
712 #define INTA AU1000_PCI_INTA
713 #define INTB AU1000_PCI_INTB
714 #define INTC AU1000_PCI_INTC
715 #define INTD AU1000_PCI_INTD
717 #define UART0_ADDR 0xB1100000
718 #define UART3_ADDR 0xB1400000
720 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
721 #define USB_HOST_CONFIG 0xB017fffc
723 #define AU1500_ETH0_BASE 0xB1500000
724 #define AU1500_ETH1_BASE 0xB1510000
725 #define AU1500_MAC0_ENABLE 0xB1520000
726 #define AU1500_MAC1_ENABLE 0xB1520004
727 #define NUM_ETH_INTERFACES 2
728 #endif /* CONFIG_SOC_AU1500 */
731 #ifdef CONFIG_SOC_AU1100
732 enum soc_au1100_ints {
733 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
734 AU1100_UART0_INT = AU1100_FIRST_INT,
742 AU1000_TOY_INT = AU1100_FIRST_INT + 14,
743 AU1000_TOY_MATCH0_INT,
744 AU1000_TOY_MATCH1_INT,
745 AU1000_TOY_MATCH2_INT,
747 AU1000_RTC_MATCH0_INT,
748 AU1000_RTC_MATCH1_INT,
749 AU1000_RTC_MATCH2_INT,
752 AU1000_USB_DEV_REQ_INT,
753 AU1000_USB_DEV_SUS_INT,
794 #define UART0_ADDR 0xB1100000
795 #define UART1_ADDR 0xB1200000
796 #define UART3_ADDR 0xB1400000
798 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
799 #define USB_HOST_CONFIG 0xB017FFFC
801 #define AU1100_ETH0_BASE 0xB0500000
802 #define AU1100_MAC0_ENABLE 0xB0520000
803 #define NUM_ETH_INTERFACES 1
804 #endif /* CONFIG_SOC_AU1100 */
806 #ifdef CONFIG_SOC_AU1550
807 enum soc_au1550_ints {
808 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
809 AU1550_UART0_INT = AU1550_FIRST_INT,
824 AU1000_TOY_MATCH0_INT,
825 AU1000_TOY_MATCH1_INT,
826 AU1000_TOY_MATCH2_INT,
828 AU1000_RTC_MATCH0_INT,
829 AU1000_RTC_MATCH1_INT,
830 AU1000_RTC_MATCH2_INT,
832 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
833 AU1550_USB_DEV_REQ_INT,
834 AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT,
835 AU1550_USB_DEV_SUS_INT,
836 AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT,
838 AU1000_USB_HOST_INT = AU1550_USB_HOST_INT,
841 AU1000_GPIO_0 = AU1550_FIRST_INT + 32,
858 AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */
872 AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */
876 #define INTA AU1550_PCI_INTA
877 #define INTB AU1550_PCI_INTB
878 #define INTC AU1550_PCI_INTC
879 #define INTD AU1550_PCI_INTD
881 #define UART0_ADDR 0xB1100000
882 #define UART1_ADDR 0xB1200000
883 #define UART3_ADDR 0xB1400000
885 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
886 #define USB_OHCI_LEN 0x00060000
887 #define USB_HOST_CONFIG 0xB4027ffc
889 #define AU1550_ETH0_BASE 0xB0500000
890 #define AU1550_ETH1_BASE 0xB0510000
891 #define AU1550_MAC0_ENABLE 0xB0520000
892 #define AU1550_MAC1_ENABLE 0xB0520004
893 #define NUM_ETH_INTERFACES 2
894 #endif /* CONFIG_SOC_AU1550 */
896 #ifdef CONFIG_SOC_AU1200
897 enum soc_au1200_ints {
898 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
899 AU1200_UART0_INT = AU1200_FIRST_INT,
914 AU1000_TOY_MATCH0_INT,
915 AU1000_TOY_MATCH1_INT,
916 AU1000_TOY_MATCH2_INT,
918 AU1000_RTC_MATCH0_INT,
919 AU1000_RTC_MATCH1_INT,
920 AU1000_RTC_MATCH2_INT,
927 AU1200_GPIO_208_215, /* Logical OR of 208:215 */
929 AU1000_USB_HOST_INT = AU1200_USB_INT,
966 #define UART0_ADDR 0xB1100000
967 #define UART1_ADDR 0xB1200000
969 #define USB_UOC_BASE 0x14020020
970 #define USB_UOC_LEN 0x20
971 #define USB_OHCI_BASE 0x14020100
972 #define USB_OHCI_LEN 0x100
973 #define USB_EHCI_BASE 0x14020200
974 #define USB_EHCI_LEN 0x100
975 #define USB_UDC_BASE 0x14022000
976 #define USB_UDC_LEN 0x2000
977 #define USB_MSR_BASE 0xB4020000
978 #define USB_MSR_MCFG 4
979 #define USBMSRMCFG_OMEMEN 0
980 #define USBMSRMCFG_OBMEN 1
981 #define USBMSRMCFG_EMEMEN 2
982 #define USBMSRMCFG_EBMEN 3
983 #define USBMSRMCFG_DMEMEN 4
984 #define USBMSRMCFG_DBMEN 5
985 #define USBMSRMCFG_GMEMEN 6
986 #define USBMSRMCFG_OHCCLKEN 16
987 #define USBMSRMCFG_EHCCLKEN 17
988 #define USBMSRMCFG_UDCCLKEN 18
989 #define USBMSRMCFG_PHYPLLEN 19
990 #define USBMSRMCFG_RDCOMB 30
991 #define USBMSRMCFG_PFEN 31
993 #endif /* CONFIG_SOC_AU1200 */
995 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
996 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
997 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
998 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
1000 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
1001 #define INTX 0xFF /* not valid */
1003 /* Programmable Counters 0 and 1 */
1004 #define SYS_BASE 0xB1900000
1005 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
1006 # define SYS_CNTRL_E1S (1 << 23)
1007 # define SYS_CNTRL_T1S (1 << 20)
1008 # define SYS_CNTRL_M21 (1 << 19)
1009 # define SYS_CNTRL_M11 (1 << 18)
1010 # define SYS_CNTRL_M01 (1 << 17)
1011 # define SYS_CNTRL_C1S (1 << 16)
1012 # define SYS_CNTRL_BP (1 << 14)
1013 # define SYS_CNTRL_EN1 (1 << 13)
1014 # define SYS_CNTRL_BT1 (1 << 12)
1015 # define SYS_CNTRL_EN0 (1 << 11)
1016 # define SYS_CNTRL_BT0 (1 << 10)
1017 # define SYS_CNTRL_E0 (1 << 8)
1018 # define SYS_CNTRL_E0S (1 << 7)
1019 # define SYS_CNTRL_32S (1 << 5)
1020 # define SYS_CNTRL_T0S (1 << 4)
1021 # define SYS_CNTRL_M20 (1 << 3)
1022 # define SYS_CNTRL_M10 (1 << 2)
1023 # define SYS_CNTRL_M00 (1 << 1)
1024 # define SYS_CNTRL_C0S (1 << 0)
1026 /* Programmable Counter 0 Registers */
1027 #define SYS_TOYTRIM (SYS_BASE + 0)
1028 #define SYS_TOYWRITE (SYS_BASE + 4)
1029 #define SYS_TOYMATCH0 (SYS_BASE + 8)
1030 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
1031 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
1032 #define SYS_TOYREAD (SYS_BASE + 0x40)
1034 /* Programmable Counter 1 Registers */
1035 #define SYS_RTCTRIM (SYS_BASE + 0x44)
1036 #define SYS_RTCWRITE (SYS_BASE + 0x48)
1037 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
1038 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
1039 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
1040 #define SYS_RTCREAD (SYS_BASE + 0x58)
1042 /* I2S Controller */
1043 #define I2S_DATA 0xB1000000
1044 # define I2S_DATA_MASK 0xffffff
1045 #define I2S_CONFIG 0xB1000004
1046 # define I2S_CONFIG_XU (1 << 25)
1047 # define I2S_CONFIG_XO (1 << 24)
1048 # define I2S_CONFIG_RU (1 << 23)
1049 # define I2S_CONFIG_RO (1 << 22)
1050 # define I2S_CONFIG_TR (1 << 21)
1051 # define I2S_CONFIG_TE (1 << 20)
1052 # define I2S_CONFIG_TF (1 << 19)
1053 # define I2S_CONFIG_RR (1 << 18)
1054 # define I2S_CONFIG_RE (1 << 17)
1055 # define I2S_CONFIG_RF (1 << 16)
1056 # define I2S_CONFIG_PD (1 << 11)
1057 # define I2S_CONFIG_LB (1 << 10)
1058 # define I2S_CONFIG_IC (1 << 9)
1059 # define I2S_CONFIG_FM_BIT 7
1060 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1061 # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1062 # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1063 # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1064 # define I2S_CONFIG_TN (1 << 6)
1065 # define I2S_CONFIG_RN (1 << 5)
1066 # define I2S_CONFIG_SZ_BIT 0
1067 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1069 #define I2S_CONTROL 0xB1000008
1070 # define I2S_CONTROL_D (1 << 1)
1071 # define I2S_CONTROL_CE (1 << 0)
1073 /* USB Host Controller */
1074 #ifndef USB_OHCI_LEN
1075 #define USB_OHCI_LEN 0x00100000
1078 #ifndef CONFIG_SOC_AU1200
1080 /* USB Device Controller */
1081 #define USBD_EP0RD 0xB0200000
1082 #define USBD_EP0WR 0xB0200004
1083 #define USBD_EP2WR 0xB0200008
1084 #define USBD_EP3WR 0xB020000C
1085 #define USBD_EP4RD 0xB0200010
1086 #define USBD_EP5RD 0xB0200014
1087 #define USBD_INTEN 0xB0200018
1088 #define USBD_INTSTAT 0xB020001C
1089 # define USBDEV_INT_SOF (1 << 12)
1090 # define USBDEV_INT_HF_BIT 6
1091 # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1092 # define USBDEV_INT_CMPLT_BIT 0
1093 # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1094 #define USBD_CONFIG 0xB0200020
1095 #define USBD_EP0CS 0xB0200024
1096 #define USBD_EP2CS 0xB0200028
1097 #define USBD_EP3CS 0xB020002C
1098 #define USBD_EP4CS 0xB0200030
1099 #define USBD_EP5CS 0xB0200034
1100 # define USBDEV_CS_SU (1 << 14)
1101 # define USBDEV_CS_NAK (1 << 13)
1102 # define USBDEV_CS_ACK (1 << 12)
1103 # define USBDEV_CS_BUSY (1 << 11)
1104 # define USBDEV_CS_TSIZE_BIT 1
1105 # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1106 # define USBDEV_CS_STALL (1 << 0)
1107 #define USBD_EP0RDSTAT 0xB0200040
1108 #define USBD_EP0WRSTAT 0xB0200044
1109 #define USBD_EP2WRSTAT 0xB0200048
1110 #define USBD_EP3WRSTAT 0xB020004C
1111 #define USBD_EP4RDSTAT 0xB0200050
1112 #define USBD_EP5RDSTAT 0xB0200054
1113 # define USBDEV_FSTAT_FLUSH (1 << 6)
1114 # define USBDEV_FSTAT_UF (1 << 5)
1115 # define USBDEV_FSTAT_OF (1 << 4)
1116 # define USBDEV_FSTAT_FCNT_BIT 0
1117 # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1118 #define USBD_ENABLE 0xB0200058
1119 # define USBDEV_ENABLE (1 << 1)
1120 # define USBDEV_CE (1 << 0)
1122 #endif /* !CONFIG_SOC_AU1200 */
1124 /* Ethernet Controllers */
1126 /* 4 byte offsets from AU1000_ETH_BASE */
1127 #define MAC_CONTROL 0x0
1128 # define MAC_RX_ENABLE (1 << 2)
1129 # define MAC_TX_ENABLE (1 << 3)
1130 # define MAC_DEF_CHECK (1 << 5)
1131 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
1132 # define MAC_AUTO_PAD (1 << 8)
1133 # define MAC_DISABLE_RETRY (1 << 10)
1134 # define MAC_DISABLE_BCAST (1 << 11)
1135 # define MAC_LATE_COL (1 << 12)
1136 # define MAC_HASH_MODE (1 << 13)
1137 # define MAC_HASH_ONLY (1 << 15)
1138 # define MAC_PASS_ALL (1 << 16)
1139 # define MAC_INVERSE_FILTER (1 << 17)
1140 # define MAC_PROMISCUOUS (1 << 18)
1141 # define MAC_PASS_ALL_MULTI (1 << 19)
1142 # define MAC_FULL_DUPLEX (1 << 20)
1143 # define MAC_NORMAL_MODE 0
1144 # define MAC_INT_LOOPBACK (1 << 21)
1145 # define MAC_EXT_LOOPBACK (1 << 22)
1146 # define MAC_DISABLE_RX_OWN (1 << 23)
1147 # define MAC_BIG_ENDIAN (1 << 30)
1148 # define MAC_RX_ALL (1 << 31)
1149 #define MAC_ADDRESS_HIGH 0x4
1150 #define MAC_ADDRESS_LOW 0x8
1151 #define MAC_MCAST_HIGH 0xC
1152 #define MAC_MCAST_LOW 0x10
1153 #define MAC_MII_CNTRL 0x14
1154 # define MAC_MII_BUSY (1 << 0)
1155 # define MAC_MII_READ 0
1156 # define MAC_MII_WRITE (1 << 1)
1157 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1158 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1159 #define MAC_MII_DATA 0x18
1160 #define MAC_FLOW_CNTRL 0x1C
1161 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
1162 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1163 # define MAC_PASS_CONTROL (1 << 2)
1164 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1165 #define MAC_VLAN1_TAG 0x20
1166 #define MAC_VLAN2_TAG 0x24
1168 /* Ethernet Controller Enable */
1170 # define MAC_EN_CLOCK_ENABLE (1 << 0)
1171 # define MAC_EN_RESET0 (1 << 1)
1172 # define MAC_EN_TOSS (0 << 2)
1173 # define MAC_EN_CACHEABLE (1 << 3)
1174 # define MAC_EN_RESET1 (1 << 4)
1175 # define MAC_EN_RESET2 (1 << 5)
1176 # define MAC_DMA_RESET (1 << 6)
1178 /* Ethernet Controller DMA Channels */
1180 #define MAC0_TX_DMA_ADDR 0xB4004000
1181 #define MAC1_TX_DMA_ADDR 0xB4004200
1182 /* offsets from MAC_TX_RING_ADDR address */
1183 #define MAC_TX_BUFF0_STATUS 0x0
1184 # define TX_FRAME_ABORTED (1 << 0)
1185 # define TX_JAB_TIMEOUT (1 << 1)
1186 # define TX_NO_CARRIER (1 << 2)
1187 # define TX_LOSS_CARRIER (1 << 3)
1188 # define TX_EXC_DEF (1 << 4)
1189 # define TX_LATE_COLL_ABORT (1 << 5)
1190 # define TX_EXC_COLL (1 << 6)
1191 # define TX_UNDERRUN (1 << 7)
1192 # define TX_DEFERRED (1 << 8)
1193 # define TX_LATE_COLL (1 << 9)
1194 # define TX_COLL_CNT_MASK (0xF << 10)
1195 # define TX_PKT_RETRY (1 << 31)
1196 #define MAC_TX_BUFF0_ADDR 0x4
1197 # define TX_DMA_ENABLE (1 << 0)
1198 # define TX_T_DONE (1 << 1)
1199 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1200 #define MAC_TX_BUFF0_LEN 0x8
1201 #define MAC_TX_BUFF1_STATUS 0x10
1202 #define MAC_TX_BUFF1_ADDR 0x14
1203 #define MAC_TX_BUFF1_LEN 0x18
1204 #define MAC_TX_BUFF2_STATUS 0x20
1205 #define MAC_TX_BUFF2_ADDR 0x24
1206 #define MAC_TX_BUFF2_LEN 0x28
1207 #define MAC_TX_BUFF3_STATUS 0x30
1208 #define MAC_TX_BUFF3_ADDR 0x34
1209 #define MAC_TX_BUFF3_LEN 0x38
1211 #define MAC0_RX_DMA_ADDR 0xB4004100
1212 #define MAC1_RX_DMA_ADDR 0xB4004300
1213 /* offsets from MAC_RX_RING_ADDR */
1214 #define MAC_RX_BUFF0_STATUS 0x0
1215 # define RX_FRAME_LEN_MASK 0x3fff
1216 # define RX_WDOG_TIMER (1 << 14)
1217 # define RX_RUNT (1 << 15)
1218 # define RX_OVERLEN (1 << 16)
1219 # define RX_COLL (1 << 17)
1220 # define RX_ETHER (1 << 18)
1221 # define RX_MII_ERROR (1 << 19)
1222 # define RX_DRIBBLING (1 << 20)
1223 # define RX_CRC_ERROR (1 << 21)
1224 # define RX_VLAN1 (1 << 22)
1225 # define RX_VLAN2 (1 << 23)
1226 # define RX_LEN_ERROR (1 << 24)
1227 # define RX_CNTRL_FRAME (1 << 25)
1228 # define RX_U_CNTRL_FRAME (1 << 26)
1229 # define RX_MCAST_FRAME (1 << 27)
1230 # define RX_BCAST_FRAME (1 << 28)
1231 # define RX_FILTER_FAIL (1 << 29)
1232 # define RX_PACKET_FILTER (1 << 30)
1233 # define RX_MISSED_FRAME (1 << 31)
1235 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1236 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1237 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1238 #define MAC_RX_BUFF0_ADDR 0x4
1239 # define RX_DMA_ENABLE (1 << 0)
1240 # define RX_T_DONE (1 << 1)
1241 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1242 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1243 #define MAC_RX_BUFF1_STATUS 0x10
1244 #define MAC_RX_BUFF1_ADDR 0x14
1245 #define MAC_RX_BUFF2_STATUS 0x20
1246 #define MAC_RX_BUFF2_ADDR 0x24
1247 #define MAC_RX_BUFF3_STATUS 0x30
1248 #define MAC_RX_BUFF3_ADDR 0x34
1251 #define UART_BASE UART0_ADDR
1252 #ifdef CONFIG_SOC_AU1200
1253 #define UART_DEBUG_BASE UART1_ADDR
1255 #define UART_DEBUG_BASE UART3_ADDR
1258 #define UART_RX 0 /* Receive buffer */
1259 #define UART_TX 4 /* Transmit buffer */
1260 #define UART_IER 8 /* Interrupt Enable Register */
1261 #define UART_IIR 0xC /* Interrupt ID Register */
1262 #define UART_FCR 0x10 /* FIFO Control Register */
1263 #define UART_LCR 0x14 /* Line Control Register */
1264 #define UART_MCR 0x18 /* Modem Control Register */
1265 #define UART_LSR 0x1C /* Line Status Register */
1266 #define UART_MSR 0x20 /* Modem Status Register */
1267 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
1268 #define UART_MOD_CNTRL 0x100 /* Module Control */
1270 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1271 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1272 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1273 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1274 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1275 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1276 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1277 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1278 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1279 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1280 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1281 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1282 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1285 * These are the definitions for the Line Control Register
1287 #define UART_LCR_SBC 0x40 /* Set break control */
1288 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1289 #define UART_LCR_EPAR 0x10 /* Even parity select */
1290 #define UART_LCR_PARITY 0x08 /* Parity Enable */
1291 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1292 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1293 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1294 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1295 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1298 * These are the definitions for the Line Status Register
1300 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1301 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1302 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1303 #define UART_LSR_FE 0x08 /* Frame error indicator */
1304 #define UART_LSR_PE 0x04 /* Parity error indicator */
1305 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1306 #define UART_LSR_DR 0x01 /* Receiver data ready */
1309 * These are the definitions for the Interrupt Identification Register
1311 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1312 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1313 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1314 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1315 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1316 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1319 * These are the definitions for the Interrupt Enable Register
1321 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1322 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1323 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1324 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1327 * These are the definitions for the Modem Control Register
1329 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1330 #define UART_MCR_OUT2 0x08 /* Out2 complement */
1331 #define UART_MCR_OUT1 0x04 /* Out1 complement */
1332 #define UART_MCR_RTS 0x02 /* RTS complement */
1333 #define UART_MCR_DTR 0x01 /* DTR complement */
1336 * These are the definitions for the Modem Status Register
1338 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1339 #define UART_MSR_RI 0x40 /* Ring Indicator */
1340 #define UART_MSR_DSR 0x20 /* Data Set Ready */
1341 #define UART_MSR_CTS 0x10 /* Clear to Send */
1342 #define UART_MSR_DDCD 0x08 /* Delta DCD */
1343 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1344 #define UART_MSR_DDSR 0x02 /* Delta DSR */
1345 #define UART_MSR_DCTS 0x01 /* Delta CTS */
1346 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1349 #define SSI0_STATUS 0xB1600000
1350 # define SSI_STATUS_BF (1 << 4)
1351 # define SSI_STATUS_OF (1 << 3)
1352 # define SSI_STATUS_UF (1 << 2)
1353 # define SSI_STATUS_D (1 << 1)
1354 # define SSI_STATUS_B (1 << 0)
1355 #define SSI0_INT 0xB1600004
1356 # define SSI_INT_OI (1 << 3)
1357 # define SSI_INT_UI (1 << 2)
1358 # define SSI_INT_DI (1 << 1)
1359 #define SSI0_INT_ENABLE 0xB1600008
1360 # define SSI_INTE_OIE (1 << 3)
1361 # define SSI_INTE_UIE (1 << 2)
1362 # define SSI_INTE_DIE (1 << 1)
1363 #define SSI0_CONFIG 0xB1600020
1364 # define SSI_CONFIG_AO (1 << 24)
1365 # define SSI_CONFIG_DO (1 << 23)
1366 # define SSI_CONFIG_ALEN_BIT 20
1367 # define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1368 # define SSI_CONFIG_DLEN_BIT 16
1369 # define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1370 # define SSI_CONFIG_DD (1 << 11)
1371 # define SSI_CONFIG_AD (1 << 10)
1372 # define SSI_CONFIG_BM_BIT 8
1373 # define SSI_CONFIG_BM_MASK (0x3 << 8)
1374 # define SSI_CONFIG_CE (1 << 7)
1375 # define SSI_CONFIG_DP (1 << 6)
1376 # define SSI_CONFIG_DL (1 << 5)
1377 # define SSI_CONFIG_EP (1 << 4)
1378 #define SSI0_ADATA 0xB1600024
1379 # define SSI_AD_D (1 << 24)
1380 # define SSI_AD_ADDR_BIT 16
1381 # define SSI_AD_ADDR_MASK (0xff << 16)
1382 # define SSI_AD_DATA_BIT 0
1383 # define SSI_AD_DATA_MASK (0xfff << 0)
1384 #define SSI0_CLKDIV 0xB1600028
1385 #define SSI0_CONTROL 0xB1600100
1386 # define SSI_CONTROL_CD (1 << 1)
1387 # define SSI_CONTROL_E (1 << 0)
1390 #define SSI1_STATUS 0xB1680000
1391 #define SSI1_INT 0xB1680004
1392 #define SSI1_INT_ENABLE 0xB1680008
1393 #define SSI1_CONFIG 0xB1680020
1394 #define SSI1_ADATA 0xB1680024
1395 #define SSI1_CLKDIV 0xB1680028
1396 #define SSI1_ENABLE 0xB1680100
1399 * Register content definitions
1401 #define SSI_STATUS_BF (1 << 4)
1402 #define SSI_STATUS_OF (1 << 3)
1403 #define SSI_STATUS_UF (1 << 2)
1404 #define SSI_STATUS_D (1 << 1)
1405 #define SSI_STATUS_B (1 << 0)
1408 #define SSI_INT_OI (1 << 3)
1409 #define SSI_INT_UI (1 << 2)
1410 #define SSI_INT_DI (1 << 1)
1413 #define SSI_INTEN_OIE (1 << 3)
1414 #define SSI_INTEN_UIE (1 << 2)
1415 #define SSI_INTEN_DIE (1 << 1)
1417 #define SSI_CONFIG_AO (1 << 24)
1418 #define SSI_CONFIG_DO (1 << 23)
1419 #define SSI_CONFIG_ALEN (7 << 20)
1420 #define SSI_CONFIG_DLEN (15 << 16)
1421 #define SSI_CONFIG_DD (1 << 11)
1422 #define SSI_CONFIG_AD (1 << 10)
1423 #define SSI_CONFIG_BM (3 << 8)
1424 #define SSI_CONFIG_CE (1 << 7)
1425 #define SSI_CONFIG_DP (1 << 6)
1426 #define SSI_CONFIG_DL (1 << 5)
1427 #define SSI_CONFIG_EP (1 << 4)
1428 #define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1429 #define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1430 #define SSI_CONFIG_BM_HI (0 << 8)
1431 #define SSI_CONFIG_BM_LO (1 << 8)
1432 #define SSI_CONFIG_BM_CY (2 << 8)
1434 #define SSI_ADATA_D (1 << 24)
1435 #define SSI_ADATA_ADDR (0xFF << 16)
1436 #define SSI_ADATA_DATA 0x0FFF
1437 #define SSI_ADATA_ADDR_N(N) (N << 16)
1439 #define SSI_ENABLE_CD (1 << 1)
1440 #define SSI_ENABLE_E (1 << 0)
1442 /* IrDA Controller */
1443 #define IRDA_BASE 0xB0300000
1444 #define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1445 #define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1446 #define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1447 #define IR_RING_SIZE (IRDA_BASE + 0x0C)
1448 #define IR_RING_PROMPT (IRDA_BASE + 0x10)
1449 #define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1450 #define IR_INT_CLEAR (IRDA_BASE + 0x18)
1451 #define IR_CONFIG_1 (IRDA_BASE + 0x20)
1452 # define IR_RX_INVERT_LED (1 << 0)
1453 # define IR_TX_INVERT_LED (1 << 1)
1454 # define IR_ST (1 << 2)
1455 # define IR_SF (1 << 3)
1456 # define IR_SIR (1 << 4)
1457 # define IR_MIR (1 << 5)
1458 # define IR_FIR (1 << 6)
1459 # define IR_16CRC (1 << 7)
1460 # define IR_TD (1 << 8)
1461 # define IR_RX_ALL (1 << 9)
1462 # define IR_DMA_ENABLE (1 << 10)
1463 # define IR_RX_ENABLE (1 << 11)
1464 # define IR_TX_ENABLE (1 << 12)
1465 # define IR_LOOPBACK (1 << 14)
1466 # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1467 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1468 #define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1469 #define IR_ENABLE (IRDA_BASE + 0x28)
1470 # define IR_RX_STATUS (1 << 9)
1471 # define IR_TX_STATUS (1 << 10)
1472 #define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1473 #define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1474 #define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1475 #define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1476 #define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1477 # define IR_MODE_INV (1 << 0)
1478 # define IR_ONE_PIN (1 << 1)
1479 #define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1482 #define SYS_PINFUNC 0xB190002C
1483 # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1484 # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1485 # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1486 # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1487 # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1488 # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1489 # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1490 # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1491 # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1492 # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1493 # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1494 # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1495 # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1496 # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1497 # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1498 # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1501 # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1502 # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1503 # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1504 # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1506 /* Au1550 only. Redefines lots of pins */
1507 # define SYS_PF_PSC2_MASK (7 << 17)
1508 # define SYS_PF_PSC2_AC97 0
1509 # define SYS_PF_PSC2_SPI 0
1510 # define SYS_PF_PSC2_I2S (1 << 17)
1511 # define SYS_PF_PSC2_SMBUS (3 << 17)
1512 # define SYS_PF_PSC2_GPIO (7 << 17)
1513 # define SYS_PF_PSC3_MASK (7 << 20)
1514 # define SYS_PF_PSC3_AC97 0
1515 # define SYS_PF_PSC3_SPI 0
1516 # define SYS_PF_PSC3_I2S (1 << 20)
1517 # define SYS_PF_PSC3_SMBUS (3 << 20)
1518 # define SYS_PF_PSC3_GPIO (7 << 20)
1519 # define SYS_PF_PSC1_S1 (1 << 1)
1520 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1523 #ifdef CONFIG_SOC_AU1200
1524 #define SYS_PINFUNC_DMA (1 << 31)
1525 #define SYS_PINFUNC_S0A (1 << 30)
1526 #define SYS_PINFUNC_S1A (1 << 29)
1527 #define SYS_PINFUNC_LP0 (1 << 28)
1528 #define SYS_PINFUNC_LP1 (1 << 27)
1529 #define SYS_PINFUNC_LD16 (1 << 26)
1530 #define SYS_PINFUNC_LD8 (1 << 25)
1531 #define SYS_PINFUNC_LD1 (1 << 24)
1532 #define SYS_PINFUNC_LD0 (1 << 23)
1533 #define SYS_PINFUNC_P1A (3 << 21)
1534 #define SYS_PINFUNC_P1B (1 << 20)
1535 #define SYS_PINFUNC_FS3 (1 << 19)
1536 #define SYS_PINFUNC_P0A (3 << 17)
1537 #define SYS_PINFUNC_CS (1 << 16)
1538 #define SYS_PINFUNC_CIM (1 << 15)
1539 #define SYS_PINFUNC_P1C (1 << 14)
1540 #define SYS_PINFUNC_U1T (1 << 12)
1541 #define SYS_PINFUNC_U1R (1 << 11)
1542 #define SYS_PINFUNC_EX1 (1 << 10)
1543 #define SYS_PINFUNC_EX0 (1 << 9)
1544 #define SYS_PINFUNC_U0R (1 << 8)
1545 #define SYS_PINFUNC_MC (1 << 7)
1546 #define SYS_PINFUNC_S0B (1 << 6)
1547 #define SYS_PINFUNC_S0C (1 << 5)
1548 #define SYS_PINFUNC_P0B (1 << 4)
1549 #define SYS_PINFUNC_U0T (1 << 3)
1550 #define SYS_PINFUNC_S1B (1 << 2)
1553 #define SYS_TRIOUTRD 0xB1900100
1554 #define SYS_TRIOUTCLR 0xB1900100
1555 #define SYS_OUTPUTRD 0xB1900108
1556 #define SYS_OUTPUTSET 0xB1900108
1557 #define SYS_OUTPUTCLR 0xB190010C
1558 #define SYS_PINSTATERD 0xB1900110
1559 #define SYS_PININPUTEN 0xB1900110
1561 /* GPIO2, Au1500, Au1550 only */
1562 #define GPIO2_BASE 0xB1700000
1563 #define GPIO2_DIR (GPIO2_BASE + 0)
1564 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
1565 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1566 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1567 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1569 /* Power Management */
1570 #define SYS_SCRATCH0 0xB1900018
1571 #define SYS_SCRATCH1 0xB190001C
1572 #define SYS_WAKEMSK 0xB1900034
1573 #define SYS_ENDIAN 0xB1900038
1574 #define SYS_POWERCTRL 0xB190003C
1575 #define SYS_WAKESRC 0xB190005C
1576 #define SYS_SLPPWR 0xB1900078
1577 #define SYS_SLEEP 0xB190007C
1579 #define SYS_WAKEMSK_D2 (1 << 9)
1580 #define SYS_WAKEMSK_M2 (1 << 8)
1581 #define SYS_WAKEMSK_GPIO(x) (1 << (x))
1583 /* Clock Controller */
1584 #define SYS_FREQCTRL0 0xB1900020
1585 # define SYS_FC_FRDIV2_BIT 22
1586 # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1587 # define SYS_FC_FE2 (1 << 21)
1588 # define SYS_FC_FS2 (1 << 20)
1589 # define SYS_FC_FRDIV1_BIT 12
1590 # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1591 # define SYS_FC_FE1 (1 << 11)
1592 # define SYS_FC_FS1 (1 << 10)
1593 # define SYS_FC_FRDIV0_BIT 2
1594 # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1595 # define SYS_FC_FE0 (1 << 1)
1596 # define SYS_FC_FS0 (1 << 0)
1597 #define SYS_FREQCTRL1 0xB1900024
1598 # define SYS_FC_FRDIV5_BIT 22
1599 # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1600 # define SYS_FC_FE5 (1 << 21)
1601 # define SYS_FC_FS5 (1 << 20)
1602 # define SYS_FC_FRDIV4_BIT 12
1603 # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1604 # define SYS_FC_FE4 (1 << 11)
1605 # define SYS_FC_FS4 (1 << 10)
1606 # define SYS_FC_FRDIV3_BIT 2
1607 # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1608 # define SYS_FC_FE3 (1 << 1)
1609 # define SYS_FC_FS3 (1 << 0)
1610 #define SYS_CLKSRC 0xB1900028
1611 # define SYS_CS_ME1_BIT 27
1612 # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1613 # define SYS_CS_DE1 (1 << 26)
1614 # define SYS_CS_CE1 (1 << 25)
1615 # define SYS_CS_ME0_BIT 22
1616 # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1617 # define SYS_CS_DE0 (1 << 21)
1618 # define SYS_CS_CE0 (1 << 20)
1619 # define SYS_CS_MI2_BIT 17
1620 # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1621 # define SYS_CS_DI2 (1 << 16)
1622 # define SYS_CS_CI2 (1 << 15)
1623 #ifdef CONFIG_SOC_AU1100
1624 # define SYS_CS_ML_BIT 7
1625 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1626 # define SYS_CS_DL (1 << 6)
1627 # define SYS_CS_CL (1 << 5)
1629 # define SYS_CS_MUH_BIT 12
1630 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1631 # define SYS_CS_DUH (1 << 11)
1632 # define SYS_CS_CUH (1 << 10)
1633 # define SYS_CS_MUD_BIT 7
1634 # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1635 # define SYS_CS_DUD (1 << 6)
1636 # define SYS_CS_CUD (1 << 5)
1638 # define SYS_CS_MIR_BIT 2
1639 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1640 # define SYS_CS_DIR (1 << 1)
1641 # define SYS_CS_CIR (1 << 0)
1643 # define SYS_CS_MUX_AUX 0x1
1644 # define SYS_CS_MUX_FQ0 0x2
1645 # define SYS_CS_MUX_FQ1 0x3
1646 # define SYS_CS_MUX_FQ2 0x4
1647 # define SYS_CS_MUX_FQ3 0x5
1648 # define SYS_CS_MUX_FQ4 0x6
1649 # define SYS_CS_MUX_FQ5 0x7
1650 #define SYS_CPUPLL 0xB1900060
1651 #define SYS_AUXPLL 0xB1900064
1653 /* AC97 Controller */
1654 #define AC97C_CONFIG 0xB0000000
1655 # define AC97C_RECV_SLOTS_BIT 13
1656 # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1657 # define AC97C_XMIT_SLOTS_BIT 3
1658 # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1659 # define AC97C_SG (1 << 2)
1660 # define AC97C_SYNC (1 << 1)
1661 # define AC97C_RESET (1 << 0)
1662 #define AC97C_STATUS 0xB0000004
1663 # define AC97C_XU (1 << 11)
1664 # define AC97C_XO (1 << 10)
1665 # define AC97C_RU (1 << 9)
1666 # define AC97C_RO (1 << 8)
1667 # define AC97C_READY (1 << 7)
1668 # define AC97C_CP (1 << 6)
1669 # define AC97C_TR (1 << 5)
1670 # define AC97C_TE (1 << 4)
1671 # define AC97C_TF (1 << 3)
1672 # define AC97C_RR (1 << 2)
1673 # define AC97C_RE (1 << 1)
1674 # define AC97C_RF (1 << 0)
1675 #define AC97C_DATA 0xB0000008
1676 #define AC97C_CMD 0xB000000C
1677 # define AC97C_WD_BIT 16
1678 # define AC97C_READ (1 << 7)
1679 # define AC97C_INDEX_MASK 0x7f
1680 #define AC97C_CNTRL 0xB0000010
1681 # define AC97C_RS (1 << 1)
1682 # define AC97C_CE (1 << 0)
1684 /* Secure Digital (SD) Controller */
1685 #define SD0_XMIT_FIFO 0xB0600000
1686 #define SD0_RECV_FIFO 0xB0600004
1687 #define SD1_XMIT_FIFO 0xB0680000
1688 #define SD1_RECV_FIFO 0xB0680004
1690 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1691 /* Au1500 PCI Controller */
1692 #define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1693 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1694 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1695 # define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1696 (1 << 25) | (1 << 26) | (1 << 27))
1697 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1698 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1699 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1700 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1701 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1702 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1703 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1704 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1705 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1706 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1707 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1708 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1710 #define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1713 * All of our structures, like PCI resource, have 32-bit members.
1714 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1715 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1716 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1717 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1718 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1719 * ourselves and then adjust the device's resources.
1721 #define Au1500_EXT_CFG 0x600000000ULL
1722 #define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1723 #define Au1500_PCI_IO_START 0x500000000ULL
1724 #define Au1500_PCI_IO_END 0x5000FFFFFULL
1725 #define Au1500_PCI_MEM_START 0x440000000ULL
1726 #define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1728 #define PCI_IO_START 0x00001000
1729 #define PCI_IO_END 0x000FFFFF
1730 #define PCI_MEM_START 0x40000000
1731 #define PCI_MEM_END 0x4FFFFFFF
1733 #define PCI_FIRST_DEVFN (0 << 3)
1734 #define PCI_LAST_DEVFN (19 << 3)
1736 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1737 #define IOPORT_RESOURCE_END 0xffffffff
1738 #define IOMEM_RESOURCE_START 0x10000000
1739 #define IOMEM_RESOURCE_END 0xffffffff
1741 #else /* Au1000 and Au1100 and Au1200 */
1743 /* Don't allow any legacy ports probing */
1744 #define IOPORT_RESOURCE_START 0x10000000
1745 #define IOPORT_RESOURCE_END 0xffffffff
1746 #define IOMEM_RESOURCE_START 0x10000000
1747 #define IOMEM_RESOURCE_END 0xffffffff
1749 #define PCI_IO_START 0
1750 #define PCI_IO_END 0
1751 #define PCI_MEM_START 0
1752 #define PCI_MEM_END 0
1753 #define PCI_FIRST_DEVFN 0
1754 #define PCI_LAST_DEVFN 0
1759 * All Au1xx0 SOCs have a PCMCIA controller.
1760 * We setup our 32-bit pseudo addresses to be equal to the
1761 * 36-bit addr >> 4, to make it easier to check the address
1763 * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000.
1764 * The pseudo address we use is 0xF400 0000. Any address over
1765 * 0xF400 0000 is a PCMCIA pseudo address.
1767 #define PCMCIA_IO_PSEUDO_PHYS (PCMCIA_IO_PHYS_ADDR >> 4)
1768 #define PCMCIA_ATTR_PSEUDO_PHYS (PCMCIA_ATTR_PHYS_ADDR >> 4)
1769 #define PCMCIA_MEM_PSEUDO_PHYS (PCMCIA_MEM_PHYS_ADDR >> 4)
1770 #define PCMCIA_PSEUDO_END (0xffffffff)
1772 #ifndef _LANGUAGE_ASSEMBLY
1773 typedef volatile struct {
1774 /* 0x0000 */ u32 toytrim;
1775 /* 0x0004 */ u32 toywrite;
1776 /* 0x0008 */ u32 toymatch0;
1777 /* 0x000C */ u32 toymatch1;
1778 /* 0x0010 */ u32 toymatch2;
1779 /* 0x0014 */ u32 cntrctrl;
1780 /* 0x0018 */ u32 scratch0;
1781 /* 0x001C */ u32 scratch1;
1782 /* 0x0020 */ u32 freqctrl0;
1783 /* 0x0024 */ u32 freqctrl1;
1784 /* 0x0028 */ u32 clksrc;
1785 /* 0x002C */ u32 pinfunc;
1786 /* 0x0030 */ u32 reserved0;
1787 /* 0x0034 */ u32 wakemsk;
1788 /* 0x0038 */ u32 endian;
1789 /* 0x003C */ u32 powerctrl;
1790 /* 0x0040 */ u32 toyread;
1791 /* 0x0044 */ u32 rtctrim;
1792 /* 0x0048 */ u32 rtcwrite;
1793 /* 0x004C */ u32 rtcmatch0;
1794 /* 0x0050 */ u32 rtcmatch1;
1795 /* 0x0054 */ u32 rtcmatch2;
1796 /* 0x0058 */ u32 rtcread;
1797 /* 0x005C */ u32 wakesrc;
1798 /* 0x0060 */ u32 cpupll;
1799 /* 0x0064 */ u32 auxpll;
1800 /* 0x0068 */ u32 reserved1;
1801 /* 0x006C */ u32 reserved2;
1802 /* 0x0070 */ u32 reserved3;
1803 /* 0x0074 */ u32 reserved4;
1804 /* 0x0078 */ u32 slppwr;
1805 /* 0x007C */ u32 sleep;
1806 /* 0x0080 */ u32 reserved5[32];
1807 /* 0x0100 */ u32 trioutrd;
1808 #define trioutclr trioutrd
1809 /* 0x0104 */ u32 reserved6;
1810 /* 0x0108 */ u32 outputrd;
1811 #define outputset outputrd
1812 /* 0x010C */ u32 outputclr;
1813 /* 0x0110 */ u32 pinstaterd;
1814 #define pininputen pinstaterd
1817 static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;