3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
38 #ifndef _LANGUAGE_ASSEMBLY
40 #include <linux/delay.h>
41 #include <linux/types.h>
44 #include <linux/irq.h>
46 /* cpu pipeline flush */
47 void static inline au_sync(void)
49 __asm__ volatile ("sync");
52 void static inline au_sync_udelay(int us)
54 __asm__ volatile ("sync");
58 void static inline au_sync_delay(int ms)
60 __asm__ volatile ("sync");
64 void static inline au_writeb(u8 val, unsigned long reg)
66 *(volatile u8 *)reg = val;
69 void static inline au_writew(u16 val, unsigned long reg)
71 *(volatile u16 *)reg = val;
74 void static inline au_writel(u32 val, unsigned long reg)
76 *(volatile u32 *)reg = val;
79 static inline u8 au_readb(unsigned long reg)
81 return *(volatile u8 *)reg;
84 static inline u16 au_readw(unsigned long reg)
86 return *(volatile u16 *)reg;
89 static inline u32 au_readl(unsigned long reg)
91 return *(volatile u32 *)reg;
94 /* Early Au1000 have a write-only SYS_CPUPLL register. */
95 static inline int au1xxx_cpu_has_pll_wo(void)
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
106 /* does CPU need CONFIG[OD] set to fix tons of errata? */
107 static inline int au1xxx_cpu_needs_config_od(void)
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
133 #define ALCHEMY_CPU_UNKNOWN -1
134 #define ALCHEMY_CPU_AU1000 0
135 #define ALCHEMY_CPU_AU1500 1
136 #define ALCHEMY_CPU_AU1100 2
137 #define ALCHEMY_CPU_AU1550 3
138 #define ALCHEMY_CPU_AU1200 4
140 static inline int alchemy_get_cputype(void)
142 switch (read_c0_prid() & 0xffff0000) {
144 return ALCHEMY_CPU_AU1000;
147 return ALCHEMY_CPU_AU1500;
150 return ALCHEMY_CPU_AU1100;
153 return ALCHEMY_CPU_AU1550;
157 return ALCHEMY_CPU_AU1200;
161 return ALCHEMY_CPU_UNKNOWN;
164 static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
166 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
169 /* check LSR TX_EMPTY bit */
172 if (__raw_readl(base + 0x1c) & 0x20)
175 for (i = 10000; i; i--)
176 asm volatile ("nop");
179 __raw_writel(c, base + 0x04); /* tx */
183 /* arch/mips/au1000/common/clocks.c */
184 extern void set_au1x00_speed(unsigned int new_freq);
185 extern unsigned int get_au1x00_speed(void);
186 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
187 extern unsigned long get_au1x00_uart_baud_base(void);
188 extern unsigned long au1xxx_calc_clock(void);
190 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
191 void au1xxx_save_and_sleep(void);
193 void save_au1xxx_intctl(void);
194 void restore_au1xxx_intctl(void);
197 /* SOC Interrupt numbers */
199 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
200 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
201 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
202 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
203 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
205 enum soc_au1000_ints {
206 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
207 AU1000_UART0_INT = AU1000_FIRST_INT,
215 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
216 AU1000_TOY_MATCH0_INT,
217 AU1000_TOY_MATCH1_INT,
218 AU1000_TOY_MATCH2_INT,
220 AU1000_RTC_MATCH0_INT,
221 AU1000_RTC_MATCH1_INT,
222 AU1000_RTC_MATCH2_INT,
225 AU1000_USB_DEV_REQ_INT,
226 AU1000_USB_DEV_SUS_INT,
267 enum soc_au1100_ints {
268 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
269 AU1100_UART0_INT = AU1100_FIRST_INT,
277 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
278 AU1100_TOY_MATCH0_INT,
279 AU1100_TOY_MATCH1_INT,
280 AU1100_TOY_MATCH2_INT,
282 AU1100_RTC_MATCH0_INT,
283 AU1100_RTC_MATCH1_INT,
284 AU1100_RTC_MATCH2_INT,
287 AU1100_USB_DEV_REQ_INT,
288 AU1100_USB_DEV_SUS_INT,
292 AU1100_GPIO208_215_INT,
329 enum soc_au1500_ints {
330 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
331 AU1500_UART0_INT = AU1500_FIRST_INT,
339 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
340 AU1500_TOY_MATCH0_INT,
341 AU1500_TOY_MATCH1_INT,
342 AU1500_TOY_MATCH2_INT,
344 AU1500_RTC_MATCH0_INT,
345 AU1500_RTC_MATCH1_INT,
346 AU1500_RTC_MATCH2_INT,
349 AU1500_USB_DEV_REQ_INT,
350 AU1500_USB_DEV_SUS_INT,
355 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
387 AU1500_GPIO208_215_INT,
390 enum soc_au1550_ints {
391 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
392 AU1550_UART0_INT = AU1550_FIRST_INT,
407 AU1550_TOY_MATCH0_INT,
408 AU1550_TOY_MATCH1_INT,
409 AU1550_TOY_MATCH2_INT,
411 AU1550_RTC_MATCH0_INT,
412 AU1550_RTC_MATCH1_INT,
413 AU1550_RTC_MATCH2_INT,
415 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
416 AU1550_USB_DEV_REQ_INT,
417 AU1550_USB_DEV_SUS_INT,
421 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
438 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
452 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
455 enum soc_au1200_ints {
456 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
457 AU1200_UART0_INT = AU1200_FIRST_INT,
472 AU1200_TOY_MATCH0_INT,
473 AU1200_TOY_MATCH1_INT,
474 AU1200_TOY_MATCH2_INT,
476 AU1200_RTC_MATCH0_INT,
477 AU1200_RTC_MATCH1_INT,
478 AU1200_RTC_MATCH2_INT,
485 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
523 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
526 * SDRAM register offsets
528 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
529 defined(CONFIG_SOC_AU1100)
530 #define MEM_SDMODE0 0x0000
531 #define MEM_SDMODE1 0x0004
532 #define MEM_SDMODE2 0x0008
533 #define MEM_SDADDR0 0x000C
534 #define MEM_SDADDR1 0x0010
535 #define MEM_SDADDR2 0x0014
536 #define MEM_SDREFCFG 0x0018
537 #define MEM_SDPRECMD 0x001C
538 #define MEM_SDAUTOREF 0x0020
539 #define MEM_SDWRMD0 0x0024
540 #define MEM_SDWRMD1 0x0028
541 #define MEM_SDWRMD2 0x002C
542 #define MEM_SDSLEEP 0x0030
543 #define MEM_SDSMCKE 0x0034
546 * MEM_SDMODE register content definitions
548 #define MEM_SDMODE_F (1 << 22)
549 #define MEM_SDMODE_SR (1 << 21)
550 #define MEM_SDMODE_BS (1 << 20)
551 #define MEM_SDMODE_RS (3 << 18)
552 #define MEM_SDMODE_CS (7 << 15)
553 #define MEM_SDMODE_TRAS (15 << 11)
554 #define MEM_SDMODE_TMRD (3 << 9)
555 #define MEM_SDMODE_TWR (3 << 7)
556 #define MEM_SDMODE_TRP (3 << 5)
557 #define MEM_SDMODE_TRCD (3 << 3)
558 #define MEM_SDMODE_TCL (7 << 0)
560 #define MEM_SDMODE_BS_2Bank (0 << 20)
561 #define MEM_SDMODE_BS_4Bank (1 << 20)
562 #define MEM_SDMODE_RS_11Row (0 << 18)
563 #define MEM_SDMODE_RS_12Row (1 << 18)
564 #define MEM_SDMODE_RS_13Row (2 << 18)
565 #define MEM_SDMODE_RS_N(N) ((N) << 18)
566 #define MEM_SDMODE_CS_7Col (0 << 15)
567 #define MEM_SDMODE_CS_8Col (1 << 15)
568 #define MEM_SDMODE_CS_9Col (2 << 15)
569 #define MEM_SDMODE_CS_10Col (3 << 15)
570 #define MEM_SDMODE_CS_11Col (4 << 15)
571 #define MEM_SDMODE_CS_N(N) ((N) << 15)
572 #define MEM_SDMODE_TRAS_N(N) ((N) << 11)
573 #define MEM_SDMODE_TMRD_N(N) ((N) << 9)
574 #define MEM_SDMODE_TWR_N(N) ((N) << 7)
575 #define MEM_SDMODE_TRP_N(N) ((N) << 5)
576 #define MEM_SDMODE_TRCD_N(N) ((N) << 3)
577 #define MEM_SDMODE_TCL_N(N) ((N) << 0)
580 * MEM_SDADDR register contents definitions
582 #define MEM_SDADDR_E (1 << 20)
583 #define MEM_SDADDR_CSBA (0x03FF << 10)
584 #define MEM_SDADDR_CSMASK (0x03FF << 0)
585 #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
586 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
589 * MEM_SDREFCFG register content definitions
591 #define MEM_SDREFCFG_TRC (15 << 28)
592 #define MEM_SDREFCFG_TRPM (3 << 26)
593 #define MEM_SDREFCFG_E (1 << 25)
594 #define MEM_SDREFCFG_RE (0x1ffffff << 0)
595 #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
596 #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
597 #define MEM_SDREFCFG_REF_N(N) (N)
600 /***********************************************************************/
603 * Au1550 SDRAM Register Offsets
606 /***********************************************************************/
608 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
609 #define MEM_SDMODE0 0x0800
610 #define MEM_SDMODE1 0x0808
611 #define MEM_SDMODE2 0x0810
612 #define MEM_SDADDR0 0x0820
613 #define MEM_SDADDR1 0x0828
614 #define MEM_SDADDR2 0x0830
615 #define MEM_SDCONFIGA 0x0840
616 #define MEM_SDCONFIGB 0x0848
617 #define MEM_SDSTAT 0x0850
618 #define MEM_SDERRADDR 0x0858
619 #define MEM_SDSTRIDE0 0x0860
620 #define MEM_SDSTRIDE1 0x0868
621 #define MEM_SDSTRIDE2 0x0870
622 #define MEM_SDWRMD0 0x0880
623 #define MEM_SDWRMD1 0x0888
624 #define MEM_SDWRMD2 0x0890
625 #define MEM_SDPRECMD 0x08C0
626 #define MEM_SDAUTOREF 0x08C8
627 #define MEM_SDSREF 0x08D0
628 #define MEM_SDSLEEP MEM_SDSREF
633 * Physical base addresses for integrated peripherals
636 #ifdef CONFIG_SOC_AU1000
637 #define MEM_PHYS_ADDR 0x14000000
638 #define STATIC_MEM_PHYS_ADDR 0x14001000
639 #define DMA0_PHYS_ADDR 0x14002000
640 #define DMA1_PHYS_ADDR 0x14002100
641 #define DMA2_PHYS_ADDR 0x14002200
642 #define DMA3_PHYS_ADDR 0x14002300
643 #define DMA4_PHYS_ADDR 0x14002400
644 #define DMA5_PHYS_ADDR 0x14002500
645 #define DMA6_PHYS_ADDR 0x14002600
646 #define DMA7_PHYS_ADDR 0x14002700
647 #define IC0_PHYS_ADDR 0x10400000
648 #define IC1_PHYS_ADDR 0x11800000
649 #define AC97_PHYS_ADDR 0x10000000
650 #define USBH_PHYS_ADDR 0x10100000
651 #define USBD_PHYS_ADDR 0x10200000
652 #define IRDA_PHYS_ADDR 0x10300000
653 #define MAC0_PHYS_ADDR 0x10500000
654 #define MAC1_PHYS_ADDR 0x10510000
655 #define MACEN_PHYS_ADDR 0x10520000
656 #define MACDMA0_PHYS_ADDR 0x14004000
657 #define MACDMA1_PHYS_ADDR 0x14004200
658 #define I2S_PHYS_ADDR 0x11000000
659 #define UART0_PHYS_ADDR 0x11100000
660 #define UART1_PHYS_ADDR 0x11200000
661 #define UART2_PHYS_ADDR 0x11300000
662 #define UART3_PHYS_ADDR 0x11400000
663 #define SSI0_PHYS_ADDR 0x11600000
664 #define SSI1_PHYS_ADDR 0x11680000
665 #define SYS_PHYS_ADDR 0x11900000
666 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
667 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
668 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
671 /********************************************************************/
673 #ifdef CONFIG_SOC_AU1500
674 #define MEM_PHYS_ADDR 0x14000000
675 #define STATIC_MEM_PHYS_ADDR 0x14001000
676 #define DMA0_PHYS_ADDR 0x14002000
677 #define DMA1_PHYS_ADDR 0x14002100
678 #define DMA2_PHYS_ADDR 0x14002200
679 #define DMA3_PHYS_ADDR 0x14002300
680 #define DMA4_PHYS_ADDR 0x14002400
681 #define DMA5_PHYS_ADDR 0x14002500
682 #define DMA6_PHYS_ADDR 0x14002600
683 #define DMA7_PHYS_ADDR 0x14002700
684 #define IC0_PHYS_ADDR 0x10400000
685 #define IC1_PHYS_ADDR 0x11800000
686 #define AC97_PHYS_ADDR 0x10000000
687 #define USBH_PHYS_ADDR 0x10100000
688 #define USBD_PHYS_ADDR 0x10200000
689 #define PCI_PHYS_ADDR 0x14005000
690 #define MAC0_PHYS_ADDR 0x11500000
691 #define MAC1_PHYS_ADDR 0x11510000
692 #define MACEN_PHYS_ADDR 0x11520000
693 #define MACDMA0_PHYS_ADDR 0x14004000
694 #define MACDMA1_PHYS_ADDR 0x14004200
695 #define I2S_PHYS_ADDR 0x11000000
696 #define UART0_PHYS_ADDR 0x11100000
697 #define UART3_PHYS_ADDR 0x11400000
698 #define GPIO2_PHYS_ADDR 0x11700000
699 #define SYS_PHYS_ADDR 0x11900000
700 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
701 #define PCI_IO_PHYS_ADDR 0x500000000ULL
702 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
703 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
704 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
705 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
706 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
709 /********************************************************************/
711 #ifdef CONFIG_SOC_AU1100
712 #define MEM_PHYS_ADDR 0x14000000
713 #define STATIC_MEM_PHYS_ADDR 0x14001000
714 #define DMA0_PHYS_ADDR 0x14002000
715 #define DMA1_PHYS_ADDR 0x14002100
716 #define DMA2_PHYS_ADDR 0x14002200
717 #define DMA3_PHYS_ADDR 0x14002300
718 #define DMA4_PHYS_ADDR 0x14002400
719 #define DMA5_PHYS_ADDR 0x14002500
720 #define DMA6_PHYS_ADDR 0x14002600
721 #define DMA7_PHYS_ADDR 0x14002700
722 #define IC0_PHYS_ADDR 0x10400000
723 #define SD0_PHYS_ADDR 0x10600000
724 #define SD1_PHYS_ADDR 0x10680000
725 #define IC1_PHYS_ADDR 0x11800000
726 #define AC97_PHYS_ADDR 0x10000000
727 #define USBH_PHYS_ADDR 0x10100000
728 #define USBD_PHYS_ADDR 0x10200000
729 #define IRDA_PHYS_ADDR 0x10300000
730 #define MAC0_PHYS_ADDR 0x10500000
731 #define MACEN_PHYS_ADDR 0x10520000
732 #define MACDMA0_PHYS_ADDR 0x14004000
733 #define MACDMA1_PHYS_ADDR 0x14004200
734 #define I2S_PHYS_ADDR 0x11000000
735 #define UART0_PHYS_ADDR 0x11100000
736 #define UART1_PHYS_ADDR 0x11200000
737 #define UART3_PHYS_ADDR 0x11400000
738 #define SSI0_PHYS_ADDR 0x11600000
739 #define SSI1_PHYS_ADDR 0x11680000
740 #define GPIO2_PHYS_ADDR 0x11700000
741 #define SYS_PHYS_ADDR 0x11900000
742 #define LCD_PHYS_ADDR 0x15000000
743 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
744 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
745 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
748 /***********************************************************************/
750 #ifdef CONFIG_SOC_AU1550
751 #define MEM_PHYS_ADDR 0x14000000
752 #define STATIC_MEM_PHYS_ADDR 0x14001000
753 #define IC0_PHYS_ADDR 0x10400000
754 #define IC1_PHYS_ADDR 0x11800000
755 #define USBH_PHYS_ADDR 0x14020000
756 #define USBD_PHYS_ADDR 0x10200000
757 #define PCI_PHYS_ADDR 0x14005000
758 #define MAC0_PHYS_ADDR 0x10500000
759 #define MAC1_PHYS_ADDR 0x10510000
760 #define MACEN_PHYS_ADDR 0x10520000
761 #define MACDMA0_PHYS_ADDR 0x14004000
762 #define MACDMA1_PHYS_ADDR 0x14004200
763 #define UART0_PHYS_ADDR 0x11100000
764 #define UART1_PHYS_ADDR 0x11200000
765 #define UART3_PHYS_ADDR 0x11400000
766 #define GPIO2_PHYS_ADDR 0x11700000
767 #define SYS_PHYS_ADDR 0x11900000
768 #define DDMA_PHYS_ADDR 0x14002000
769 #define PE_PHYS_ADDR 0x14008000
770 #define PSC0_PHYS_ADDR 0x11A00000
771 #define PSC1_PHYS_ADDR 0x11B00000
772 #define PSC2_PHYS_ADDR 0x10A00000
773 #define PSC3_PHYS_ADDR 0x10B00000
774 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
775 #define PCI_IO_PHYS_ADDR 0x500000000ULL
776 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
777 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
778 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
779 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
780 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
783 /***********************************************************************/
785 #ifdef CONFIG_SOC_AU1200
786 #define MEM_PHYS_ADDR 0x14000000
787 #define STATIC_MEM_PHYS_ADDR 0x14001000
788 #define AES_PHYS_ADDR 0x10300000
789 #define CIM_PHYS_ADDR 0x14004000
790 #define IC0_PHYS_ADDR 0x10400000
791 #define IC1_PHYS_ADDR 0x11800000
792 #define USBM_PHYS_ADDR 0x14020000
793 #define USBH_PHYS_ADDR 0x14020100
794 #define UART0_PHYS_ADDR 0x11100000
795 #define UART1_PHYS_ADDR 0x11200000
796 #define GPIO2_PHYS_ADDR 0x11700000
797 #define SYS_PHYS_ADDR 0x11900000
798 #define DDMA_PHYS_ADDR 0x14002000
799 #define PSC0_PHYS_ADDR 0x11A00000
800 #define PSC1_PHYS_ADDR 0x11B00000
801 #define SD0_PHYS_ADDR 0x10600000
802 #define SD1_PHYS_ADDR 0x10680000
803 #define LCD_PHYS_ADDR 0x15000000
804 #define SWCNT_PHYS_ADDR 0x1110010C
805 #define MAEFE_PHYS_ADDR 0x14012000
806 #define MAEBE_PHYS_ADDR 0x14010000
807 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
808 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
809 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
812 /* Static Bus Controller */
813 #define MEM_STCFG0 0xB4001000
814 #define MEM_STTIME0 0xB4001004
815 #define MEM_STADDR0 0xB4001008
817 #define MEM_STCFG1 0xB4001010
818 #define MEM_STTIME1 0xB4001014
819 #define MEM_STADDR1 0xB4001018
821 #define MEM_STCFG2 0xB4001020
822 #define MEM_STTIME2 0xB4001024
823 #define MEM_STADDR2 0xB4001028
825 #define MEM_STCFG3 0xB4001030
826 #define MEM_STTIME3 0xB4001034
827 #define MEM_STADDR3 0xB4001038
829 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
830 #define MEM_STNDCTL 0xB4001100
831 #define MEM_STSTAT 0xB4001104
833 #define MEM_STNAND_CMD 0x0
834 #define MEM_STNAND_ADDR 0x4
835 #define MEM_STNAND_DATA 0x20
838 /* Interrupt Controller 0 */
839 #define IC0_CFG0RD 0xB0400040
840 #define IC0_CFG0SET 0xB0400040
841 #define IC0_CFG0CLR 0xB0400044
843 #define IC0_CFG1RD 0xB0400048
844 #define IC0_CFG1SET 0xB0400048
845 #define IC0_CFG1CLR 0xB040004C
847 #define IC0_CFG2RD 0xB0400050
848 #define IC0_CFG2SET 0xB0400050
849 #define IC0_CFG2CLR 0xB0400054
851 #define IC0_REQ0INT 0xB0400054
852 #define IC0_SRCRD 0xB0400058
853 #define IC0_SRCSET 0xB0400058
854 #define IC0_SRCCLR 0xB040005C
855 #define IC0_REQ1INT 0xB040005C
857 #define IC0_ASSIGNRD 0xB0400060
858 #define IC0_ASSIGNSET 0xB0400060
859 #define IC0_ASSIGNCLR 0xB0400064
861 #define IC0_WAKERD 0xB0400068
862 #define IC0_WAKESET 0xB0400068
863 #define IC0_WAKECLR 0xB040006C
865 #define IC0_MASKRD 0xB0400070
866 #define IC0_MASKSET 0xB0400070
867 #define IC0_MASKCLR 0xB0400074
869 #define IC0_RISINGRD 0xB0400078
870 #define IC0_RISINGCLR 0xB0400078
871 #define IC0_FALLINGRD 0xB040007C
872 #define IC0_FALLINGCLR 0xB040007C
874 #define IC0_TESTBIT 0xB0400080
876 /* Interrupt Controller 1 */
877 #define IC1_CFG0RD 0xB1800040
878 #define IC1_CFG0SET 0xB1800040
879 #define IC1_CFG0CLR 0xB1800044
881 #define IC1_CFG1RD 0xB1800048
882 #define IC1_CFG1SET 0xB1800048
883 #define IC1_CFG1CLR 0xB180004C
885 #define IC1_CFG2RD 0xB1800050
886 #define IC1_CFG2SET 0xB1800050
887 #define IC1_CFG2CLR 0xB1800054
889 #define IC1_REQ0INT 0xB1800054
890 #define IC1_SRCRD 0xB1800058
891 #define IC1_SRCSET 0xB1800058
892 #define IC1_SRCCLR 0xB180005C
893 #define IC1_REQ1INT 0xB180005C
895 #define IC1_ASSIGNRD 0xB1800060
896 #define IC1_ASSIGNSET 0xB1800060
897 #define IC1_ASSIGNCLR 0xB1800064
899 #define IC1_WAKERD 0xB1800068
900 #define IC1_WAKESET 0xB1800068
901 #define IC1_WAKECLR 0xB180006C
903 #define IC1_MASKRD 0xB1800070
904 #define IC1_MASKSET 0xB1800070
905 #define IC1_MASKCLR 0xB1800074
907 #define IC1_RISINGRD 0xB1800078
908 #define IC1_RISINGCLR 0xB1800078
909 #define IC1_FALLINGRD 0xB180007C
910 #define IC1_FALLINGCLR 0xB180007C
912 #define IC1_TESTBIT 0xB1800080
916 #ifdef CONFIG_SOC_AU1000
918 #define UART0_ADDR 0xB1100000
919 #define UART1_ADDR 0xB1200000
920 #define UART2_ADDR 0xB1300000
921 #define UART3_ADDR 0xB1400000
923 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
924 #define USB_HOST_CONFIG 0xB017FFFC
925 #define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
927 #define AU1000_ETH0_BASE 0xB0500000
928 #define AU1000_ETH1_BASE 0xB0510000
929 #define AU1000_MAC0_ENABLE 0xB0520000
930 #define AU1000_MAC1_ENABLE 0xB0520004
931 #define NUM_ETH_INTERFACES 2
932 #endif /* CONFIG_SOC_AU1000 */
935 #ifdef CONFIG_SOC_AU1500
937 #define UART0_ADDR 0xB1100000
938 #define UART3_ADDR 0xB1400000
940 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
941 #define USB_HOST_CONFIG 0xB017fffc
942 #define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
944 #define AU1500_ETH0_BASE 0xB1500000
945 #define AU1500_ETH1_BASE 0xB1510000
946 #define AU1500_MAC0_ENABLE 0xB1520000
947 #define AU1500_MAC1_ENABLE 0xB1520004
948 #define NUM_ETH_INTERFACES 2
949 #endif /* CONFIG_SOC_AU1500 */
952 #ifdef CONFIG_SOC_AU1100
954 #define UART0_ADDR 0xB1100000
955 #define UART1_ADDR 0xB1200000
956 #define UART3_ADDR 0xB1400000
958 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
959 #define USB_HOST_CONFIG 0xB017FFFC
960 #define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
962 #define AU1100_ETH0_BASE 0xB0500000
963 #define AU1100_MAC0_ENABLE 0xB0520000
964 #define NUM_ETH_INTERFACES 1
965 #endif /* CONFIG_SOC_AU1100 */
967 #ifdef CONFIG_SOC_AU1550
968 #define UART0_ADDR 0xB1100000
969 #define UART1_ADDR 0xB1200000
970 #define UART3_ADDR 0xB1400000
972 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
973 #define USB_OHCI_LEN 0x00060000
974 #define USB_HOST_CONFIG 0xB4027ffc
975 #define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
977 #define AU1550_ETH0_BASE 0xB0500000
978 #define AU1550_ETH1_BASE 0xB0510000
979 #define AU1550_MAC0_ENABLE 0xB0520000
980 #define AU1550_MAC1_ENABLE 0xB0520004
981 #define NUM_ETH_INTERFACES 2
982 #endif /* CONFIG_SOC_AU1550 */
985 #ifdef CONFIG_SOC_AU1200
987 #define UART0_ADDR 0xB1100000
988 #define UART1_ADDR 0xB1200000
990 #define USB_UOC_BASE 0x14020020
991 #define USB_UOC_LEN 0x20
992 #define USB_OHCI_BASE 0x14020100
993 #define USB_OHCI_LEN 0x100
994 #define USB_EHCI_BASE 0x14020200
995 #define USB_EHCI_LEN 0x100
996 #define USB_UDC_BASE 0x14022000
997 #define USB_UDC_LEN 0x2000
998 #define USB_MSR_BASE 0xB4020000
999 #define USB_MSR_MCFG 4
1000 #define USBMSRMCFG_OMEMEN 0
1001 #define USBMSRMCFG_OBMEN 1
1002 #define USBMSRMCFG_EMEMEN 2
1003 #define USBMSRMCFG_EBMEN 3
1004 #define USBMSRMCFG_DMEMEN 4
1005 #define USBMSRMCFG_DBMEN 5
1006 #define USBMSRMCFG_GMEMEN 6
1007 #define USBMSRMCFG_OHCCLKEN 16
1008 #define USBMSRMCFG_EHCCLKEN 17
1009 #define USBMSRMCFG_UDCCLKEN 18
1010 #define USBMSRMCFG_PHYPLLEN 19
1011 #define USBMSRMCFG_RDCOMB 30
1012 #define USBMSRMCFG_PFEN 31
1014 #define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
1016 #endif /* CONFIG_SOC_AU1200 */
1018 /* Programmable Counters 0 and 1 */
1019 #define SYS_BASE 0xB1900000
1020 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
1021 # define SYS_CNTRL_E1S (1 << 23)
1022 # define SYS_CNTRL_T1S (1 << 20)
1023 # define SYS_CNTRL_M21 (1 << 19)
1024 # define SYS_CNTRL_M11 (1 << 18)
1025 # define SYS_CNTRL_M01 (1 << 17)
1026 # define SYS_CNTRL_C1S (1 << 16)
1027 # define SYS_CNTRL_BP (1 << 14)
1028 # define SYS_CNTRL_EN1 (1 << 13)
1029 # define SYS_CNTRL_BT1 (1 << 12)
1030 # define SYS_CNTRL_EN0 (1 << 11)
1031 # define SYS_CNTRL_BT0 (1 << 10)
1032 # define SYS_CNTRL_E0 (1 << 8)
1033 # define SYS_CNTRL_E0S (1 << 7)
1034 # define SYS_CNTRL_32S (1 << 5)
1035 # define SYS_CNTRL_T0S (1 << 4)
1036 # define SYS_CNTRL_M20 (1 << 3)
1037 # define SYS_CNTRL_M10 (1 << 2)
1038 # define SYS_CNTRL_M00 (1 << 1)
1039 # define SYS_CNTRL_C0S (1 << 0)
1041 /* Programmable Counter 0 Registers */
1042 #define SYS_TOYTRIM (SYS_BASE + 0)
1043 #define SYS_TOYWRITE (SYS_BASE + 4)
1044 #define SYS_TOYMATCH0 (SYS_BASE + 8)
1045 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
1046 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
1047 #define SYS_TOYREAD (SYS_BASE + 0x40)
1049 /* Programmable Counter 1 Registers */
1050 #define SYS_RTCTRIM (SYS_BASE + 0x44)
1051 #define SYS_RTCWRITE (SYS_BASE + 0x48)
1052 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
1053 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
1054 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
1055 #define SYS_RTCREAD (SYS_BASE + 0x58)
1057 /* I2S Controller */
1058 #define I2S_DATA 0xB1000000
1059 # define I2S_DATA_MASK 0xffffff
1060 #define I2S_CONFIG 0xB1000004
1061 # define I2S_CONFIG_XU (1 << 25)
1062 # define I2S_CONFIG_XO (1 << 24)
1063 # define I2S_CONFIG_RU (1 << 23)
1064 # define I2S_CONFIG_RO (1 << 22)
1065 # define I2S_CONFIG_TR (1 << 21)
1066 # define I2S_CONFIG_TE (1 << 20)
1067 # define I2S_CONFIG_TF (1 << 19)
1068 # define I2S_CONFIG_RR (1 << 18)
1069 # define I2S_CONFIG_RE (1 << 17)
1070 # define I2S_CONFIG_RF (1 << 16)
1071 # define I2S_CONFIG_PD (1 << 11)
1072 # define I2S_CONFIG_LB (1 << 10)
1073 # define I2S_CONFIG_IC (1 << 9)
1074 # define I2S_CONFIG_FM_BIT 7
1075 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1076 # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1077 # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1078 # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1079 # define I2S_CONFIG_TN (1 << 6)
1080 # define I2S_CONFIG_RN (1 << 5)
1081 # define I2S_CONFIG_SZ_BIT 0
1082 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1084 #define I2S_CONTROL 0xB1000008
1085 # define I2S_CONTROL_D (1 << 1)
1086 # define I2S_CONTROL_CE (1 << 0)
1088 /* USB Host Controller */
1089 #ifndef USB_OHCI_LEN
1090 #define USB_OHCI_LEN 0x00100000
1093 #ifndef CONFIG_SOC_AU1200
1095 /* USB Device Controller */
1096 #define USBD_EP0RD 0xB0200000
1097 #define USBD_EP0WR 0xB0200004
1098 #define USBD_EP2WR 0xB0200008
1099 #define USBD_EP3WR 0xB020000C
1100 #define USBD_EP4RD 0xB0200010
1101 #define USBD_EP5RD 0xB0200014
1102 #define USBD_INTEN 0xB0200018
1103 #define USBD_INTSTAT 0xB020001C
1104 # define USBDEV_INT_SOF (1 << 12)
1105 # define USBDEV_INT_HF_BIT 6
1106 # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1107 # define USBDEV_INT_CMPLT_BIT 0
1108 # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1109 #define USBD_CONFIG 0xB0200020
1110 #define USBD_EP0CS 0xB0200024
1111 #define USBD_EP2CS 0xB0200028
1112 #define USBD_EP3CS 0xB020002C
1113 #define USBD_EP4CS 0xB0200030
1114 #define USBD_EP5CS 0xB0200034
1115 # define USBDEV_CS_SU (1 << 14)
1116 # define USBDEV_CS_NAK (1 << 13)
1117 # define USBDEV_CS_ACK (1 << 12)
1118 # define USBDEV_CS_BUSY (1 << 11)
1119 # define USBDEV_CS_TSIZE_BIT 1
1120 # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1121 # define USBDEV_CS_STALL (1 << 0)
1122 #define USBD_EP0RDSTAT 0xB0200040
1123 #define USBD_EP0WRSTAT 0xB0200044
1124 #define USBD_EP2WRSTAT 0xB0200048
1125 #define USBD_EP3WRSTAT 0xB020004C
1126 #define USBD_EP4RDSTAT 0xB0200050
1127 #define USBD_EP5RDSTAT 0xB0200054
1128 # define USBDEV_FSTAT_FLUSH (1 << 6)
1129 # define USBDEV_FSTAT_UF (1 << 5)
1130 # define USBDEV_FSTAT_OF (1 << 4)
1131 # define USBDEV_FSTAT_FCNT_BIT 0
1132 # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1133 #define USBD_ENABLE 0xB0200058
1134 # define USBDEV_ENABLE (1 << 1)
1135 # define USBDEV_CE (1 << 0)
1137 #endif /* !CONFIG_SOC_AU1200 */
1139 /* Ethernet Controllers */
1141 /* 4 byte offsets from AU1000_ETH_BASE */
1142 #define MAC_CONTROL 0x0
1143 # define MAC_RX_ENABLE (1 << 2)
1144 # define MAC_TX_ENABLE (1 << 3)
1145 # define MAC_DEF_CHECK (1 << 5)
1146 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
1147 # define MAC_AUTO_PAD (1 << 8)
1148 # define MAC_DISABLE_RETRY (1 << 10)
1149 # define MAC_DISABLE_BCAST (1 << 11)
1150 # define MAC_LATE_COL (1 << 12)
1151 # define MAC_HASH_MODE (1 << 13)
1152 # define MAC_HASH_ONLY (1 << 15)
1153 # define MAC_PASS_ALL (1 << 16)
1154 # define MAC_INVERSE_FILTER (1 << 17)
1155 # define MAC_PROMISCUOUS (1 << 18)
1156 # define MAC_PASS_ALL_MULTI (1 << 19)
1157 # define MAC_FULL_DUPLEX (1 << 20)
1158 # define MAC_NORMAL_MODE 0
1159 # define MAC_INT_LOOPBACK (1 << 21)
1160 # define MAC_EXT_LOOPBACK (1 << 22)
1161 # define MAC_DISABLE_RX_OWN (1 << 23)
1162 # define MAC_BIG_ENDIAN (1 << 30)
1163 # define MAC_RX_ALL (1 << 31)
1164 #define MAC_ADDRESS_HIGH 0x4
1165 #define MAC_ADDRESS_LOW 0x8
1166 #define MAC_MCAST_HIGH 0xC
1167 #define MAC_MCAST_LOW 0x10
1168 #define MAC_MII_CNTRL 0x14
1169 # define MAC_MII_BUSY (1 << 0)
1170 # define MAC_MII_READ 0
1171 # define MAC_MII_WRITE (1 << 1)
1172 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1173 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1174 #define MAC_MII_DATA 0x18
1175 #define MAC_FLOW_CNTRL 0x1C
1176 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
1177 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1178 # define MAC_PASS_CONTROL (1 << 2)
1179 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1180 #define MAC_VLAN1_TAG 0x20
1181 #define MAC_VLAN2_TAG 0x24
1183 /* Ethernet Controller Enable */
1185 # define MAC_EN_CLOCK_ENABLE (1 << 0)
1186 # define MAC_EN_RESET0 (1 << 1)
1187 # define MAC_EN_TOSS (0 << 2)
1188 # define MAC_EN_CACHEABLE (1 << 3)
1189 # define MAC_EN_RESET1 (1 << 4)
1190 # define MAC_EN_RESET2 (1 << 5)
1191 # define MAC_DMA_RESET (1 << 6)
1193 /* Ethernet Controller DMA Channels */
1195 #define MAC0_TX_DMA_ADDR 0xB4004000
1196 #define MAC1_TX_DMA_ADDR 0xB4004200
1197 /* offsets from MAC_TX_RING_ADDR address */
1198 #define MAC_TX_BUFF0_STATUS 0x0
1199 # define TX_FRAME_ABORTED (1 << 0)
1200 # define TX_JAB_TIMEOUT (1 << 1)
1201 # define TX_NO_CARRIER (1 << 2)
1202 # define TX_LOSS_CARRIER (1 << 3)
1203 # define TX_EXC_DEF (1 << 4)
1204 # define TX_LATE_COLL_ABORT (1 << 5)
1205 # define TX_EXC_COLL (1 << 6)
1206 # define TX_UNDERRUN (1 << 7)
1207 # define TX_DEFERRED (1 << 8)
1208 # define TX_LATE_COLL (1 << 9)
1209 # define TX_COLL_CNT_MASK (0xF << 10)
1210 # define TX_PKT_RETRY (1 << 31)
1211 #define MAC_TX_BUFF0_ADDR 0x4
1212 # define TX_DMA_ENABLE (1 << 0)
1213 # define TX_T_DONE (1 << 1)
1214 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1215 #define MAC_TX_BUFF0_LEN 0x8
1216 #define MAC_TX_BUFF1_STATUS 0x10
1217 #define MAC_TX_BUFF1_ADDR 0x14
1218 #define MAC_TX_BUFF1_LEN 0x18
1219 #define MAC_TX_BUFF2_STATUS 0x20
1220 #define MAC_TX_BUFF2_ADDR 0x24
1221 #define MAC_TX_BUFF2_LEN 0x28
1222 #define MAC_TX_BUFF3_STATUS 0x30
1223 #define MAC_TX_BUFF3_ADDR 0x34
1224 #define MAC_TX_BUFF3_LEN 0x38
1226 #define MAC0_RX_DMA_ADDR 0xB4004100
1227 #define MAC1_RX_DMA_ADDR 0xB4004300
1228 /* offsets from MAC_RX_RING_ADDR */
1229 #define MAC_RX_BUFF0_STATUS 0x0
1230 # define RX_FRAME_LEN_MASK 0x3fff
1231 # define RX_WDOG_TIMER (1 << 14)
1232 # define RX_RUNT (1 << 15)
1233 # define RX_OVERLEN (1 << 16)
1234 # define RX_COLL (1 << 17)
1235 # define RX_ETHER (1 << 18)
1236 # define RX_MII_ERROR (1 << 19)
1237 # define RX_DRIBBLING (1 << 20)
1238 # define RX_CRC_ERROR (1 << 21)
1239 # define RX_VLAN1 (1 << 22)
1240 # define RX_VLAN2 (1 << 23)
1241 # define RX_LEN_ERROR (1 << 24)
1242 # define RX_CNTRL_FRAME (1 << 25)
1243 # define RX_U_CNTRL_FRAME (1 << 26)
1244 # define RX_MCAST_FRAME (1 << 27)
1245 # define RX_BCAST_FRAME (1 << 28)
1246 # define RX_FILTER_FAIL (1 << 29)
1247 # define RX_PACKET_FILTER (1 << 30)
1248 # define RX_MISSED_FRAME (1 << 31)
1250 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1251 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1252 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1253 #define MAC_RX_BUFF0_ADDR 0x4
1254 # define RX_DMA_ENABLE (1 << 0)
1255 # define RX_T_DONE (1 << 1)
1256 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1257 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1258 #define MAC_RX_BUFF1_STATUS 0x10
1259 #define MAC_RX_BUFF1_ADDR 0x14
1260 #define MAC_RX_BUFF2_STATUS 0x20
1261 #define MAC_RX_BUFF2_ADDR 0x24
1262 #define MAC_RX_BUFF3_STATUS 0x30
1263 #define MAC_RX_BUFF3_ADDR 0x34
1266 #define UART_BASE UART0_ADDR
1267 #ifdef CONFIG_SOC_AU1200
1268 #define UART_DEBUG_BASE UART1_ADDR
1270 #define UART_DEBUG_BASE UART3_ADDR
1273 #define UART_RX 0 /* Receive buffer */
1274 #define UART_TX 4 /* Transmit buffer */
1275 #define UART_IER 8 /* Interrupt Enable Register */
1276 #define UART_IIR 0xC /* Interrupt ID Register */
1277 #define UART_FCR 0x10 /* FIFO Control Register */
1278 #define UART_LCR 0x14 /* Line Control Register */
1279 #define UART_MCR 0x18 /* Modem Control Register */
1280 #define UART_LSR 0x1C /* Line Status Register */
1281 #define UART_MSR 0x20 /* Modem Status Register */
1282 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
1283 #define UART_MOD_CNTRL 0x100 /* Module Control */
1285 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1286 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1287 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1288 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1289 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1290 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1291 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1292 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1293 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1294 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1295 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1296 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1297 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1300 * These are the definitions for the Line Control Register
1302 #define UART_LCR_SBC 0x40 /* Set break control */
1303 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1304 #define UART_LCR_EPAR 0x10 /* Even parity select */
1305 #define UART_LCR_PARITY 0x08 /* Parity Enable */
1306 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1307 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1308 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1309 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1310 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1313 * These are the definitions for the Line Status Register
1315 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1316 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1317 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1318 #define UART_LSR_FE 0x08 /* Frame error indicator */
1319 #define UART_LSR_PE 0x04 /* Parity error indicator */
1320 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1321 #define UART_LSR_DR 0x01 /* Receiver data ready */
1324 * These are the definitions for the Interrupt Identification Register
1326 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1327 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1328 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1329 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1330 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1331 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1334 * These are the definitions for the Interrupt Enable Register
1336 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1337 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1338 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1339 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1342 * These are the definitions for the Modem Control Register
1344 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1345 #define UART_MCR_OUT2 0x08 /* Out2 complement */
1346 #define UART_MCR_OUT1 0x04 /* Out1 complement */
1347 #define UART_MCR_RTS 0x02 /* RTS complement */
1348 #define UART_MCR_DTR 0x01 /* DTR complement */
1351 * These are the definitions for the Modem Status Register
1353 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1354 #define UART_MSR_RI 0x40 /* Ring Indicator */
1355 #define UART_MSR_DSR 0x20 /* Data Set Ready */
1356 #define UART_MSR_CTS 0x10 /* Clear to Send */
1357 #define UART_MSR_DDCD 0x08 /* Delta DCD */
1358 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1359 #define UART_MSR_DDSR 0x02 /* Delta DSR */
1360 #define UART_MSR_DCTS 0x01 /* Delta CTS */
1361 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1364 #define SSI0_STATUS 0xB1600000
1365 # define SSI_STATUS_BF (1 << 4)
1366 # define SSI_STATUS_OF (1 << 3)
1367 # define SSI_STATUS_UF (1 << 2)
1368 # define SSI_STATUS_D (1 << 1)
1369 # define SSI_STATUS_B (1 << 0)
1370 #define SSI0_INT 0xB1600004
1371 # define SSI_INT_OI (1 << 3)
1372 # define SSI_INT_UI (1 << 2)
1373 # define SSI_INT_DI (1 << 1)
1374 #define SSI0_INT_ENABLE 0xB1600008
1375 # define SSI_INTE_OIE (1 << 3)
1376 # define SSI_INTE_UIE (1 << 2)
1377 # define SSI_INTE_DIE (1 << 1)
1378 #define SSI0_CONFIG 0xB1600020
1379 # define SSI_CONFIG_AO (1 << 24)
1380 # define SSI_CONFIG_DO (1 << 23)
1381 # define SSI_CONFIG_ALEN_BIT 20
1382 # define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1383 # define SSI_CONFIG_DLEN_BIT 16
1384 # define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1385 # define SSI_CONFIG_DD (1 << 11)
1386 # define SSI_CONFIG_AD (1 << 10)
1387 # define SSI_CONFIG_BM_BIT 8
1388 # define SSI_CONFIG_BM_MASK (0x3 << 8)
1389 # define SSI_CONFIG_CE (1 << 7)
1390 # define SSI_CONFIG_DP (1 << 6)
1391 # define SSI_CONFIG_DL (1 << 5)
1392 # define SSI_CONFIG_EP (1 << 4)
1393 #define SSI0_ADATA 0xB1600024
1394 # define SSI_AD_D (1 << 24)
1395 # define SSI_AD_ADDR_BIT 16
1396 # define SSI_AD_ADDR_MASK (0xff << 16)
1397 # define SSI_AD_DATA_BIT 0
1398 # define SSI_AD_DATA_MASK (0xfff << 0)
1399 #define SSI0_CLKDIV 0xB1600028
1400 #define SSI0_CONTROL 0xB1600100
1401 # define SSI_CONTROL_CD (1 << 1)
1402 # define SSI_CONTROL_E (1 << 0)
1405 #define SSI1_STATUS 0xB1680000
1406 #define SSI1_INT 0xB1680004
1407 #define SSI1_INT_ENABLE 0xB1680008
1408 #define SSI1_CONFIG 0xB1680020
1409 #define SSI1_ADATA 0xB1680024
1410 #define SSI1_CLKDIV 0xB1680028
1411 #define SSI1_ENABLE 0xB1680100
1414 * Register content definitions
1416 #define SSI_STATUS_BF (1 << 4)
1417 #define SSI_STATUS_OF (1 << 3)
1418 #define SSI_STATUS_UF (1 << 2)
1419 #define SSI_STATUS_D (1 << 1)
1420 #define SSI_STATUS_B (1 << 0)
1423 #define SSI_INT_OI (1 << 3)
1424 #define SSI_INT_UI (1 << 2)
1425 #define SSI_INT_DI (1 << 1)
1428 #define SSI_INTEN_OIE (1 << 3)
1429 #define SSI_INTEN_UIE (1 << 2)
1430 #define SSI_INTEN_DIE (1 << 1)
1432 #define SSI_CONFIG_AO (1 << 24)
1433 #define SSI_CONFIG_DO (1 << 23)
1434 #define SSI_CONFIG_ALEN (7 << 20)
1435 #define SSI_CONFIG_DLEN (15 << 16)
1436 #define SSI_CONFIG_DD (1 << 11)
1437 #define SSI_CONFIG_AD (1 << 10)
1438 #define SSI_CONFIG_BM (3 << 8)
1439 #define SSI_CONFIG_CE (1 << 7)
1440 #define SSI_CONFIG_DP (1 << 6)
1441 #define SSI_CONFIG_DL (1 << 5)
1442 #define SSI_CONFIG_EP (1 << 4)
1443 #define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1444 #define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1445 #define SSI_CONFIG_BM_HI (0 << 8)
1446 #define SSI_CONFIG_BM_LO (1 << 8)
1447 #define SSI_CONFIG_BM_CY (2 << 8)
1449 #define SSI_ADATA_D (1 << 24)
1450 #define SSI_ADATA_ADDR (0xFF << 16)
1451 #define SSI_ADATA_DATA 0x0FFF
1452 #define SSI_ADATA_ADDR_N(N) (N << 16)
1454 #define SSI_ENABLE_CD (1 << 1)
1455 #define SSI_ENABLE_E (1 << 0)
1457 /* IrDA Controller */
1458 #define IRDA_BASE 0xB0300000
1459 #define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1460 #define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1461 #define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1462 #define IR_RING_SIZE (IRDA_BASE + 0x0C)
1463 #define IR_RING_PROMPT (IRDA_BASE + 0x10)
1464 #define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1465 #define IR_INT_CLEAR (IRDA_BASE + 0x18)
1466 #define IR_CONFIG_1 (IRDA_BASE + 0x20)
1467 # define IR_RX_INVERT_LED (1 << 0)
1468 # define IR_TX_INVERT_LED (1 << 1)
1469 # define IR_ST (1 << 2)
1470 # define IR_SF (1 << 3)
1471 # define IR_SIR (1 << 4)
1472 # define IR_MIR (1 << 5)
1473 # define IR_FIR (1 << 6)
1474 # define IR_16CRC (1 << 7)
1475 # define IR_TD (1 << 8)
1476 # define IR_RX_ALL (1 << 9)
1477 # define IR_DMA_ENABLE (1 << 10)
1478 # define IR_RX_ENABLE (1 << 11)
1479 # define IR_TX_ENABLE (1 << 12)
1480 # define IR_LOOPBACK (1 << 14)
1481 # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1482 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1483 #define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1484 #define IR_ENABLE (IRDA_BASE + 0x28)
1485 # define IR_RX_STATUS (1 << 9)
1486 # define IR_TX_STATUS (1 << 10)
1487 #define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1488 #define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1489 #define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1490 #define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1491 #define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1492 # define IR_MODE_INV (1 << 0)
1493 # define IR_ONE_PIN (1 << 1)
1494 #define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1497 #define SYS_PINFUNC 0xB190002C
1498 # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1499 # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1500 # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1501 # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1502 # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1503 # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1504 # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1505 # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1506 # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1507 # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1508 # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1509 # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1510 # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1511 # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1512 # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1513 # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1516 # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1517 # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1518 # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1519 # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1521 /* Au1550 only. Redefines lots of pins */
1522 # define SYS_PF_PSC2_MASK (7 << 17)
1523 # define SYS_PF_PSC2_AC97 0
1524 # define SYS_PF_PSC2_SPI 0
1525 # define SYS_PF_PSC2_I2S (1 << 17)
1526 # define SYS_PF_PSC2_SMBUS (3 << 17)
1527 # define SYS_PF_PSC2_GPIO (7 << 17)
1528 # define SYS_PF_PSC3_MASK (7 << 20)
1529 # define SYS_PF_PSC3_AC97 0
1530 # define SYS_PF_PSC3_SPI 0
1531 # define SYS_PF_PSC3_I2S (1 << 20)
1532 # define SYS_PF_PSC3_SMBUS (3 << 20)
1533 # define SYS_PF_PSC3_GPIO (7 << 20)
1534 # define SYS_PF_PSC1_S1 (1 << 1)
1535 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1538 #ifdef CONFIG_SOC_AU1200
1539 #define SYS_PINFUNC_DMA (1 << 31)
1540 #define SYS_PINFUNC_S0A (1 << 30)
1541 #define SYS_PINFUNC_S1A (1 << 29)
1542 #define SYS_PINFUNC_LP0 (1 << 28)
1543 #define SYS_PINFUNC_LP1 (1 << 27)
1544 #define SYS_PINFUNC_LD16 (1 << 26)
1545 #define SYS_PINFUNC_LD8 (1 << 25)
1546 #define SYS_PINFUNC_LD1 (1 << 24)
1547 #define SYS_PINFUNC_LD0 (1 << 23)
1548 #define SYS_PINFUNC_P1A (3 << 21)
1549 #define SYS_PINFUNC_P1B (1 << 20)
1550 #define SYS_PINFUNC_FS3 (1 << 19)
1551 #define SYS_PINFUNC_P0A (3 << 17)
1552 #define SYS_PINFUNC_CS (1 << 16)
1553 #define SYS_PINFUNC_CIM (1 << 15)
1554 #define SYS_PINFUNC_P1C (1 << 14)
1555 #define SYS_PINFUNC_U1T (1 << 12)
1556 #define SYS_PINFUNC_U1R (1 << 11)
1557 #define SYS_PINFUNC_EX1 (1 << 10)
1558 #define SYS_PINFUNC_EX0 (1 << 9)
1559 #define SYS_PINFUNC_U0R (1 << 8)
1560 #define SYS_PINFUNC_MC (1 << 7)
1561 #define SYS_PINFUNC_S0B (1 << 6)
1562 #define SYS_PINFUNC_S0C (1 << 5)
1563 #define SYS_PINFUNC_P0B (1 << 4)
1564 #define SYS_PINFUNC_U0T (1 << 3)
1565 #define SYS_PINFUNC_S1B (1 << 2)
1568 #define SYS_TRIOUTRD 0xB1900100
1569 #define SYS_TRIOUTCLR 0xB1900100
1570 #define SYS_OUTPUTRD 0xB1900108
1571 #define SYS_OUTPUTSET 0xB1900108
1572 #define SYS_OUTPUTCLR 0xB190010C
1573 #define SYS_PINSTATERD 0xB1900110
1574 #define SYS_PININPUTEN 0xB1900110
1576 /* GPIO2, Au1500, Au1550 only */
1577 #define GPIO2_BASE 0xB1700000
1578 #define GPIO2_DIR (GPIO2_BASE + 0)
1579 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
1580 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1581 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1582 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1584 /* Power Management */
1585 #define SYS_SCRATCH0 0xB1900018
1586 #define SYS_SCRATCH1 0xB190001C
1587 #define SYS_WAKEMSK 0xB1900034
1588 #define SYS_ENDIAN 0xB1900038
1589 #define SYS_POWERCTRL 0xB190003C
1590 #define SYS_WAKESRC 0xB190005C
1591 #define SYS_SLPPWR 0xB1900078
1592 #define SYS_SLEEP 0xB190007C
1594 #define SYS_WAKEMSK_D2 (1 << 9)
1595 #define SYS_WAKEMSK_M2 (1 << 8)
1596 #define SYS_WAKEMSK_GPIO(x) (1 << (x))
1598 /* Clock Controller */
1599 #define SYS_FREQCTRL0 0xB1900020
1600 # define SYS_FC_FRDIV2_BIT 22
1601 # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1602 # define SYS_FC_FE2 (1 << 21)
1603 # define SYS_FC_FS2 (1 << 20)
1604 # define SYS_FC_FRDIV1_BIT 12
1605 # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1606 # define SYS_FC_FE1 (1 << 11)
1607 # define SYS_FC_FS1 (1 << 10)
1608 # define SYS_FC_FRDIV0_BIT 2
1609 # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1610 # define SYS_FC_FE0 (1 << 1)
1611 # define SYS_FC_FS0 (1 << 0)
1612 #define SYS_FREQCTRL1 0xB1900024
1613 # define SYS_FC_FRDIV5_BIT 22
1614 # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1615 # define SYS_FC_FE5 (1 << 21)
1616 # define SYS_FC_FS5 (1 << 20)
1617 # define SYS_FC_FRDIV4_BIT 12
1618 # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1619 # define SYS_FC_FE4 (1 << 11)
1620 # define SYS_FC_FS4 (1 << 10)
1621 # define SYS_FC_FRDIV3_BIT 2
1622 # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1623 # define SYS_FC_FE3 (1 << 1)
1624 # define SYS_FC_FS3 (1 << 0)
1625 #define SYS_CLKSRC 0xB1900028
1626 # define SYS_CS_ME1_BIT 27
1627 # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1628 # define SYS_CS_DE1 (1 << 26)
1629 # define SYS_CS_CE1 (1 << 25)
1630 # define SYS_CS_ME0_BIT 22
1631 # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1632 # define SYS_CS_DE0 (1 << 21)
1633 # define SYS_CS_CE0 (1 << 20)
1634 # define SYS_CS_MI2_BIT 17
1635 # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1636 # define SYS_CS_DI2 (1 << 16)
1637 # define SYS_CS_CI2 (1 << 15)
1638 #ifdef CONFIG_SOC_AU1100
1639 # define SYS_CS_ML_BIT 7
1640 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1641 # define SYS_CS_DL (1 << 6)
1642 # define SYS_CS_CL (1 << 5)
1644 # define SYS_CS_MUH_BIT 12
1645 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1646 # define SYS_CS_DUH (1 << 11)
1647 # define SYS_CS_CUH (1 << 10)
1648 # define SYS_CS_MUD_BIT 7
1649 # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1650 # define SYS_CS_DUD (1 << 6)
1651 # define SYS_CS_CUD (1 << 5)
1653 # define SYS_CS_MIR_BIT 2
1654 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1655 # define SYS_CS_DIR (1 << 1)
1656 # define SYS_CS_CIR (1 << 0)
1658 # define SYS_CS_MUX_AUX 0x1
1659 # define SYS_CS_MUX_FQ0 0x2
1660 # define SYS_CS_MUX_FQ1 0x3
1661 # define SYS_CS_MUX_FQ2 0x4
1662 # define SYS_CS_MUX_FQ3 0x5
1663 # define SYS_CS_MUX_FQ4 0x6
1664 # define SYS_CS_MUX_FQ5 0x7
1665 #define SYS_CPUPLL 0xB1900060
1666 #define SYS_AUXPLL 0xB1900064
1668 /* AC97 Controller */
1669 #define AC97C_CONFIG 0xB0000000
1670 # define AC97C_RECV_SLOTS_BIT 13
1671 # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1672 # define AC97C_XMIT_SLOTS_BIT 3
1673 # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1674 # define AC97C_SG (1 << 2)
1675 # define AC97C_SYNC (1 << 1)
1676 # define AC97C_RESET (1 << 0)
1677 #define AC97C_STATUS 0xB0000004
1678 # define AC97C_XU (1 << 11)
1679 # define AC97C_XO (1 << 10)
1680 # define AC97C_RU (1 << 9)
1681 # define AC97C_RO (1 << 8)
1682 # define AC97C_READY (1 << 7)
1683 # define AC97C_CP (1 << 6)
1684 # define AC97C_TR (1 << 5)
1685 # define AC97C_TE (1 << 4)
1686 # define AC97C_TF (1 << 3)
1687 # define AC97C_RR (1 << 2)
1688 # define AC97C_RE (1 << 1)
1689 # define AC97C_RF (1 << 0)
1690 #define AC97C_DATA 0xB0000008
1691 #define AC97C_CMD 0xB000000C
1692 # define AC97C_WD_BIT 16
1693 # define AC97C_READ (1 << 7)
1694 # define AC97C_INDEX_MASK 0x7f
1695 #define AC97C_CNTRL 0xB0000010
1696 # define AC97C_RS (1 << 1)
1697 # define AC97C_CE (1 << 0)
1699 /* Secure Digital (SD) Controller */
1700 #define SD0_XMIT_FIFO 0xB0600000
1701 #define SD0_RECV_FIFO 0xB0600004
1702 #define SD1_XMIT_FIFO 0xB0680000
1703 #define SD1_RECV_FIFO 0xB0680004
1705 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1706 /* Au1500 PCI Controller */
1707 #define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1708 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1709 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1710 # define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1711 (1 << 25) | (1 << 26) | (1 << 27))
1712 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1713 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1714 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1715 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1716 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1717 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1718 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1719 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1720 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1721 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1722 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1723 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1725 #define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1728 * All of our structures, like PCI resource, have 32-bit members.
1729 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1730 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1731 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1732 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1733 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1734 * ourselves and then adjust the device's resources.
1736 #define Au1500_EXT_CFG 0x600000000ULL
1737 #define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1738 #define Au1500_PCI_IO_START 0x500000000ULL
1739 #define Au1500_PCI_IO_END 0x5000FFFFFULL
1740 #define Au1500_PCI_MEM_START 0x440000000ULL
1741 #define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1743 #define PCI_IO_START 0x00001000
1744 #define PCI_IO_END 0x000FFFFF
1745 #define PCI_MEM_START 0x40000000
1746 #define PCI_MEM_END 0x4FFFFFFF
1748 #define PCI_FIRST_DEVFN (0 << 3)
1749 #define PCI_LAST_DEVFN (19 << 3)
1751 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1752 #define IOPORT_RESOURCE_END 0xffffffff
1753 #define IOMEM_RESOURCE_START 0x10000000
1754 #define IOMEM_RESOURCE_END 0xffffffff
1756 #else /* Au1000 and Au1100 and Au1200 */
1758 /* Don't allow any legacy ports probing */
1759 #define IOPORT_RESOURCE_START 0x10000000
1760 #define IOPORT_RESOURCE_END 0xffffffff
1761 #define IOMEM_RESOURCE_START 0x10000000
1762 #define IOMEM_RESOURCE_END 0xffffffff
1764 #define PCI_IO_START 0
1765 #define PCI_IO_END 0
1766 #define PCI_MEM_START 0
1767 #define PCI_MEM_END 0
1768 #define PCI_FIRST_DEVFN 0
1769 #define PCI_LAST_DEVFN 0
1774 * All Au1xx0 SOCs have a PCMCIA controller.
1775 * We setup our 32-bit pseudo addresses to be equal to the
1776 * 36-bit addr >> 4, to make it easier to check the address
1778 * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000.
1779 * The pseudo address we use is 0xF400 0000. Any address over
1780 * 0xF400 0000 is a PCMCIA pseudo address.
1782 #define PCMCIA_IO_PSEUDO_PHYS (PCMCIA_IO_PHYS_ADDR >> 4)
1783 #define PCMCIA_ATTR_PSEUDO_PHYS (PCMCIA_ATTR_PHYS_ADDR >> 4)
1784 #define PCMCIA_MEM_PSEUDO_PHYS (PCMCIA_MEM_PHYS_ADDR >> 4)
1785 #define PCMCIA_PSEUDO_END (0xffffffff)
1787 #ifndef _LANGUAGE_ASSEMBLY
1788 typedef volatile struct {
1789 /* 0x0000 */ u32 toytrim;
1790 /* 0x0004 */ u32 toywrite;
1791 /* 0x0008 */ u32 toymatch0;
1792 /* 0x000C */ u32 toymatch1;
1793 /* 0x0010 */ u32 toymatch2;
1794 /* 0x0014 */ u32 cntrctrl;
1795 /* 0x0018 */ u32 scratch0;
1796 /* 0x001C */ u32 scratch1;
1797 /* 0x0020 */ u32 freqctrl0;
1798 /* 0x0024 */ u32 freqctrl1;
1799 /* 0x0028 */ u32 clksrc;
1800 /* 0x002C */ u32 pinfunc;
1801 /* 0x0030 */ u32 reserved0;
1802 /* 0x0034 */ u32 wakemsk;
1803 /* 0x0038 */ u32 endian;
1804 /* 0x003C */ u32 powerctrl;
1805 /* 0x0040 */ u32 toyread;
1806 /* 0x0044 */ u32 rtctrim;
1807 /* 0x0048 */ u32 rtcwrite;
1808 /* 0x004C */ u32 rtcmatch0;
1809 /* 0x0050 */ u32 rtcmatch1;
1810 /* 0x0054 */ u32 rtcmatch2;
1811 /* 0x0058 */ u32 rtcread;
1812 /* 0x005C */ u32 wakesrc;
1813 /* 0x0060 */ u32 cpupll;
1814 /* 0x0064 */ u32 auxpll;
1815 /* 0x0068 */ u32 reserved1;
1816 /* 0x006C */ u32 reserved2;
1817 /* 0x0070 */ u32 reserved3;
1818 /* 0x0074 */ u32 reserved4;
1819 /* 0x0078 */ u32 slppwr;
1820 /* 0x007C */ u32 sleep;
1821 /* 0x0080 */ u32 reserved5[32];
1822 /* 0x0100 */ u32 trioutrd;
1823 #define trioutclr trioutrd
1824 /* 0x0104 */ u32 reserved6;
1825 /* 0x0108 */ u32 outputrd;
1826 #define outputset outputrd
1827 /* 0x010C */ u32 outputclr;
1828 /* 0x0110 */ u32 pinstaterd;
1829 #define pininputen pinstaterd
1832 static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;