3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
38 #ifndef _LANGUAGE_ASSEMBLY
40 #include <linux/delay.h>
41 #include <linux/types.h>
44 #include <linux/irq.h>
46 /* cpu pipeline flush */
47 void static inline au_sync(void)
49 __asm__ volatile ("sync");
52 void static inline au_sync_udelay(int us)
54 __asm__ volatile ("sync");
58 void static inline au_sync_delay(int ms)
60 __asm__ volatile ("sync");
64 void static inline au_writeb(u8 val, unsigned long reg)
66 *(volatile u8 *)reg = val;
69 void static inline au_writew(u16 val, unsigned long reg)
71 *(volatile u16 *)reg = val;
74 void static inline au_writel(u32 val, unsigned long reg)
76 *(volatile u32 *)reg = val;
79 static inline u8 au_readb(unsigned long reg)
81 return *(volatile u8 *)reg;
84 static inline u16 au_readw(unsigned long reg)
86 return *(volatile u16 *)reg;
89 static inline u32 au_readl(unsigned long reg)
91 return *(volatile u32 *)reg;
94 /* Early Au1000 have a write-only SYS_CPUPLL register. */
95 static inline int au1xxx_cpu_has_pll_wo(void)
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
106 /* does CPU need CONFIG[OD] set to fix tons of errata? */
107 static inline int au1xxx_cpu_needs_config_od(void)
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
133 #define ALCHEMY_CPU_UNKNOWN -1
134 #define ALCHEMY_CPU_AU1000 0
135 #define ALCHEMY_CPU_AU1500 1
136 #define ALCHEMY_CPU_AU1100 2
137 #define ALCHEMY_CPU_AU1550 3
138 #define ALCHEMY_CPU_AU1200 4
140 static inline int alchemy_get_cputype(void)
142 switch (read_c0_prid() & 0xffff0000) {
144 return ALCHEMY_CPU_AU1000;
147 return ALCHEMY_CPU_AU1500;
150 return ALCHEMY_CPU_AU1100;
153 return ALCHEMY_CPU_AU1550;
157 return ALCHEMY_CPU_AU1200;
161 return ALCHEMY_CPU_UNKNOWN;
164 static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
166 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
169 /* check LSR TX_EMPTY bit */
172 if (__raw_readl(base + 0x1c) & 0x20)
175 for (i = 10000; i; i--)
176 asm volatile ("nop");
179 __raw_writel(c, base + 0x04); /* tx */
183 /* arch/mips/au1000/common/clocks.c */
184 extern void set_au1x00_speed(unsigned int new_freq);
185 extern unsigned int get_au1x00_speed(void);
186 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
187 extern unsigned long get_au1x00_uart_baud_base(void);
188 extern unsigned long au1xxx_calc_clock(void);
190 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
191 void au1xxx_save_and_sleep(void);
195 /* SOC Interrupt numbers */
197 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
198 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
199 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
200 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
201 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
203 enum soc_au1000_ints {
204 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
205 AU1000_UART0_INT = AU1000_FIRST_INT,
213 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
214 AU1000_TOY_MATCH0_INT,
215 AU1000_TOY_MATCH1_INT,
216 AU1000_TOY_MATCH2_INT,
218 AU1000_RTC_MATCH0_INT,
219 AU1000_RTC_MATCH1_INT,
220 AU1000_RTC_MATCH2_INT,
223 AU1000_USB_DEV_REQ_INT,
224 AU1000_USB_DEV_SUS_INT,
265 enum soc_au1100_ints {
266 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
267 AU1100_UART0_INT = AU1100_FIRST_INT,
275 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
276 AU1100_TOY_MATCH0_INT,
277 AU1100_TOY_MATCH1_INT,
278 AU1100_TOY_MATCH2_INT,
280 AU1100_RTC_MATCH0_INT,
281 AU1100_RTC_MATCH1_INT,
282 AU1100_RTC_MATCH2_INT,
285 AU1100_USB_DEV_REQ_INT,
286 AU1100_USB_DEV_SUS_INT,
290 AU1100_GPIO208_215_INT,
327 enum soc_au1500_ints {
328 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
329 AU1500_UART0_INT = AU1500_FIRST_INT,
337 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
338 AU1500_TOY_MATCH0_INT,
339 AU1500_TOY_MATCH1_INT,
340 AU1500_TOY_MATCH2_INT,
342 AU1500_RTC_MATCH0_INT,
343 AU1500_RTC_MATCH1_INT,
344 AU1500_RTC_MATCH2_INT,
347 AU1500_USB_DEV_REQ_INT,
348 AU1500_USB_DEV_SUS_INT,
353 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
385 AU1500_GPIO208_215_INT,
388 enum soc_au1550_ints {
389 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
390 AU1550_UART0_INT = AU1550_FIRST_INT,
405 AU1550_TOY_MATCH0_INT,
406 AU1550_TOY_MATCH1_INT,
407 AU1550_TOY_MATCH2_INT,
409 AU1550_RTC_MATCH0_INT,
410 AU1550_RTC_MATCH1_INT,
411 AU1550_RTC_MATCH2_INT,
413 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
414 AU1550_USB_DEV_REQ_INT,
415 AU1550_USB_DEV_SUS_INT,
419 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
436 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
450 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
453 enum soc_au1200_ints {
454 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
455 AU1200_UART0_INT = AU1200_FIRST_INT,
470 AU1200_TOY_MATCH0_INT,
471 AU1200_TOY_MATCH1_INT,
472 AU1200_TOY_MATCH2_INT,
474 AU1200_RTC_MATCH0_INT,
475 AU1200_RTC_MATCH1_INT,
476 AU1200_RTC_MATCH2_INT,
483 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
521 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
524 * SDRAM register offsets
526 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
527 defined(CONFIG_SOC_AU1100)
528 #define MEM_SDMODE0 0x0000
529 #define MEM_SDMODE1 0x0004
530 #define MEM_SDMODE2 0x0008
531 #define MEM_SDADDR0 0x000C
532 #define MEM_SDADDR1 0x0010
533 #define MEM_SDADDR2 0x0014
534 #define MEM_SDREFCFG 0x0018
535 #define MEM_SDPRECMD 0x001C
536 #define MEM_SDAUTOREF 0x0020
537 #define MEM_SDWRMD0 0x0024
538 #define MEM_SDWRMD1 0x0028
539 #define MEM_SDWRMD2 0x002C
540 #define MEM_SDSLEEP 0x0030
541 #define MEM_SDSMCKE 0x0034
544 * MEM_SDMODE register content definitions
546 #define MEM_SDMODE_F (1 << 22)
547 #define MEM_SDMODE_SR (1 << 21)
548 #define MEM_SDMODE_BS (1 << 20)
549 #define MEM_SDMODE_RS (3 << 18)
550 #define MEM_SDMODE_CS (7 << 15)
551 #define MEM_SDMODE_TRAS (15 << 11)
552 #define MEM_SDMODE_TMRD (3 << 9)
553 #define MEM_SDMODE_TWR (3 << 7)
554 #define MEM_SDMODE_TRP (3 << 5)
555 #define MEM_SDMODE_TRCD (3 << 3)
556 #define MEM_SDMODE_TCL (7 << 0)
558 #define MEM_SDMODE_BS_2Bank (0 << 20)
559 #define MEM_SDMODE_BS_4Bank (1 << 20)
560 #define MEM_SDMODE_RS_11Row (0 << 18)
561 #define MEM_SDMODE_RS_12Row (1 << 18)
562 #define MEM_SDMODE_RS_13Row (2 << 18)
563 #define MEM_SDMODE_RS_N(N) ((N) << 18)
564 #define MEM_SDMODE_CS_7Col (0 << 15)
565 #define MEM_SDMODE_CS_8Col (1 << 15)
566 #define MEM_SDMODE_CS_9Col (2 << 15)
567 #define MEM_SDMODE_CS_10Col (3 << 15)
568 #define MEM_SDMODE_CS_11Col (4 << 15)
569 #define MEM_SDMODE_CS_N(N) ((N) << 15)
570 #define MEM_SDMODE_TRAS_N(N) ((N) << 11)
571 #define MEM_SDMODE_TMRD_N(N) ((N) << 9)
572 #define MEM_SDMODE_TWR_N(N) ((N) << 7)
573 #define MEM_SDMODE_TRP_N(N) ((N) << 5)
574 #define MEM_SDMODE_TRCD_N(N) ((N) << 3)
575 #define MEM_SDMODE_TCL_N(N) ((N) << 0)
578 * MEM_SDADDR register contents definitions
580 #define MEM_SDADDR_E (1 << 20)
581 #define MEM_SDADDR_CSBA (0x03FF << 10)
582 #define MEM_SDADDR_CSMASK (0x03FF << 0)
583 #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
584 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
587 * MEM_SDREFCFG register content definitions
589 #define MEM_SDREFCFG_TRC (15 << 28)
590 #define MEM_SDREFCFG_TRPM (3 << 26)
591 #define MEM_SDREFCFG_E (1 << 25)
592 #define MEM_SDREFCFG_RE (0x1ffffff << 0)
593 #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
594 #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
595 #define MEM_SDREFCFG_REF_N(N) (N)
598 /***********************************************************************/
601 * Au1550 SDRAM Register Offsets
604 /***********************************************************************/
606 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
607 #define MEM_SDMODE0 0x0800
608 #define MEM_SDMODE1 0x0808
609 #define MEM_SDMODE2 0x0810
610 #define MEM_SDADDR0 0x0820
611 #define MEM_SDADDR1 0x0828
612 #define MEM_SDADDR2 0x0830
613 #define MEM_SDCONFIGA 0x0840
614 #define MEM_SDCONFIGB 0x0848
615 #define MEM_SDSTAT 0x0850
616 #define MEM_SDERRADDR 0x0858
617 #define MEM_SDSTRIDE0 0x0860
618 #define MEM_SDSTRIDE1 0x0868
619 #define MEM_SDSTRIDE2 0x0870
620 #define MEM_SDWRMD0 0x0880
621 #define MEM_SDWRMD1 0x0888
622 #define MEM_SDWRMD2 0x0890
623 #define MEM_SDPRECMD 0x08C0
624 #define MEM_SDAUTOREF 0x08C8
625 #define MEM_SDSREF 0x08D0
626 #define MEM_SDSLEEP MEM_SDSREF
631 * Physical base addresses for integrated peripherals
634 #ifdef CONFIG_SOC_AU1000
635 #define MEM_PHYS_ADDR 0x14000000
636 #define STATIC_MEM_PHYS_ADDR 0x14001000
637 #define DMA0_PHYS_ADDR 0x14002000
638 #define DMA1_PHYS_ADDR 0x14002100
639 #define DMA2_PHYS_ADDR 0x14002200
640 #define DMA3_PHYS_ADDR 0x14002300
641 #define DMA4_PHYS_ADDR 0x14002400
642 #define DMA5_PHYS_ADDR 0x14002500
643 #define DMA6_PHYS_ADDR 0x14002600
644 #define DMA7_PHYS_ADDR 0x14002700
645 #define IC0_PHYS_ADDR 0x10400000
646 #define IC1_PHYS_ADDR 0x11800000
647 #define AC97_PHYS_ADDR 0x10000000
648 #define USBH_PHYS_ADDR 0x10100000
649 #define USBD_PHYS_ADDR 0x10200000
650 #define IRDA_PHYS_ADDR 0x10300000
651 #define MAC0_PHYS_ADDR 0x10500000
652 #define MAC1_PHYS_ADDR 0x10510000
653 #define MACEN_PHYS_ADDR 0x10520000
654 #define MACDMA0_PHYS_ADDR 0x14004000
655 #define MACDMA1_PHYS_ADDR 0x14004200
656 #define I2S_PHYS_ADDR 0x11000000
657 #define UART0_PHYS_ADDR 0x11100000
658 #define UART1_PHYS_ADDR 0x11200000
659 #define UART2_PHYS_ADDR 0x11300000
660 #define UART3_PHYS_ADDR 0x11400000
661 #define SSI0_PHYS_ADDR 0x11600000
662 #define SSI1_PHYS_ADDR 0x11680000
663 #define SYS_PHYS_ADDR 0x11900000
664 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
665 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
666 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
669 /********************************************************************/
671 #ifdef CONFIG_SOC_AU1500
672 #define MEM_PHYS_ADDR 0x14000000
673 #define STATIC_MEM_PHYS_ADDR 0x14001000
674 #define DMA0_PHYS_ADDR 0x14002000
675 #define DMA1_PHYS_ADDR 0x14002100
676 #define DMA2_PHYS_ADDR 0x14002200
677 #define DMA3_PHYS_ADDR 0x14002300
678 #define DMA4_PHYS_ADDR 0x14002400
679 #define DMA5_PHYS_ADDR 0x14002500
680 #define DMA6_PHYS_ADDR 0x14002600
681 #define DMA7_PHYS_ADDR 0x14002700
682 #define IC0_PHYS_ADDR 0x10400000
683 #define IC1_PHYS_ADDR 0x11800000
684 #define AC97_PHYS_ADDR 0x10000000
685 #define USBH_PHYS_ADDR 0x10100000
686 #define USBD_PHYS_ADDR 0x10200000
687 #define PCI_PHYS_ADDR 0x14005000
688 #define MAC0_PHYS_ADDR 0x11500000
689 #define MAC1_PHYS_ADDR 0x11510000
690 #define MACEN_PHYS_ADDR 0x11520000
691 #define MACDMA0_PHYS_ADDR 0x14004000
692 #define MACDMA1_PHYS_ADDR 0x14004200
693 #define I2S_PHYS_ADDR 0x11000000
694 #define UART0_PHYS_ADDR 0x11100000
695 #define UART3_PHYS_ADDR 0x11400000
696 #define GPIO2_PHYS_ADDR 0x11700000
697 #define SYS_PHYS_ADDR 0x11900000
698 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
699 #define PCI_IO_PHYS_ADDR 0x500000000ULL
700 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
701 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
702 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
703 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
704 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
707 /********************************************************************/
709 #ifdef CONFIG_SOC_AU1100
710 #define MEM_PHYS_ADDR 0x14000000
711 #define STATIC_MEM_PHYS_ADDR 0x14001000
712 #define DMA0_PHYS_ADDR 0x14002000
713 #define DMA1_PHYS_ADDR 0x14002100
714 #define DMA2_PHYS_ADDR 0x14002200
715 #define DMA3_PHYS_ADDR 0x14002300
716 #define DMA4_PHYS_ADDR 0x14002400
717 #define DMA5_PHYS_ADDR 0x14002500
718 #define DMA6_PHYS_ADDR 0x14002600
719 #define DMA7_PHYS_ADDR 0x14002700
720 #define IC0_PHYS_ADDR 0x10400000
721 #define SD0_PHYS_ADDR 0x10600000
722 #define SD1_PHYS_ADDR 0x10680000
723 #define IC1_PHYS_ADDR 0x11800000
724 #define AC97_PHYS_ADDR 0x10000000
725 #define USBH_PHYS_ADDR 0x10100000
726 #define USBD_PHYS_ADDR 0x10200000
727 #define IRDA_PHYS_ADDR 0x10300000
728 #define MAC0_PHYS_ADDR 0x10500000
729 #define MACEN_PHYS_ADDR 0x10520000
730 #define MACDMA0_PHYS_ADDR 0x14004000
731 #define MACDMA1_PHYS_ADDR 0x14004200
732 #define I2S_PHYS_ADDR 0x11000000
733 #define UART0_PHYS_ADDR 0x11100000
734 #define UART1_PHYS_ADDR 0x11200000
735 #define UART3_PHYS_ADDR 0x11400000
736 #define SSI0_PHYS_ADDR 0x11600000
737 #define SSI1_PHYS_ADDR 0x11680000
738 #define GPIO2_PHYS_ADDR 0x11700000
739 #define SYS_PHYS_ADDR 0x11900000
740 #define LCD_PHYS_ADDR 0x15000000
741 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
742 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
743 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
746 /***********************************************************************/
748 #ifdef CONFIG_SOC_AU1550
749 #define MEM_PHYS_ADDR 0x14000000
750 #define STATIC_MEM_PHYS_ADDR 0x14001000
751 #define IC0_PHYS_ADDR 0x10400000
752 #define IC1_PHYS_ADDR 0x11800000
753 #define USBH_PHYS_ADDR 0x14020000
754 #define USBD_PHYS_ADDR 0x10200000
755 #define PCI_PHYS_ADDR 0x14005000
756 #define MAC0_PHYS_ADDR 0x10500000
757 #define MAC1_PHYS_ADDR 0x10510000
758 #define MACEN_PHYS_ADDR 0x10520000
759 #define MACDMA0_PHYS_ADDR 0x14004000
760 #define MACDMA1_PHYS_ADDR 0x14004200
761 #define UART0_PHYS_ADDR 0x11100000
762 #define UART1_PHYS_ADDR 0x11200000
763 #define UART3_PHYS_ADDR 0x11400000
764 #define GPIO2_PHYS_ADDR 0x11700000
765 #define SYS_PHYS_ADDR 0x11900000
766 #define DDMA_PHYS_ADDR 0x14002000
767 #define PE_PHYS_ADDR 0x14008000
768 #define PSC0_PHYS_ADDR 0x11A00000
769 #define PSC1_PHYS_ADDR 0x11B00000
770 #define PSC2_PHYS_ADDR 0x10A00000
771 #define PSC3_PHYS_ADDR 0x10B00000
772 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
773 #define PCI_IO_PHYS_ADDR 0x500000000ULL
774 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
775 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
776 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
777 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
778 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
781 /***********************************************************************/
783 #ifdef CONFIG_SOC_AU1200
784 #define MEM_PHYS_ADDR 0x14000000
785 #define STATIC_MEM_PHYS_ADDR 0x14001000
786 #define AES_PHYS_ADDR 0x10300000
787 #define CIM_PHYS_ADDR 0x14004000
788 #define IC0_PHYS_ADDR 0x10400000
789 #define IC1_PHYS_ADDR 0x11800000
790 #define USBM_PHYS_ADDR 0x14020000
791 #define USBH_PHYS_ADDR 0x14020100
792 #define UART0_PHYS_ADDR 0x11100000
793 #define UART1_PHYS_ADDR 0x11200000
794 #define GPIO2_PHYS_ADDR 0x11700000
795 #define SYS_PHYS_ADDR 0x11900000
796 #define DDMA_PHYS_ADDR 0x14002000
797 #define PSC0_PHYS_ADDR 0x11A00000
798 #define PSC1_PHYS_ADDR 0x11B00000
799 #define SD0_PHYS_ADDR 0x10600000
800 #define SD1_PHYS_ADDR 0x10680000
801 #define LCD_PHYS_ADDR 0x15000000
802 #define SWCNT_PHYS_ADDR 0x1110010C
803 #define MAEFE_PHYS_ADDR 0x14012000
804 #define MAEBE_PHYS_ADDR 0x14010000
805 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
806 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
807 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
810 /* Static Bus Controller */
811 #define MEM_STCFG0 0xB4001000
812 #define MEM_STTIME0 0xB4001004
813 #define MEM_STADDR0 0xB4001008
815 #define MEM_STCFG1 0xB4001010
816 #define MEM_STTIME1 0xB4001014
817 #define MEM_STADDR1 0xB4001018
819 #define MEM_STCFG2 0xB4001020
820 #define MEM_STTIME2 0xB4001024
821 #define MEM_STADDR2 0xB4001028
823 #define MEM_STCFG3 0xB4001030
824 #define MEM_STTIME3 0xB4001034
825 #define MEM_STADDR3 0xB4001038
827 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
828 #define MEM_STNDCTL 0xB4001100
829 #define MEM_STSTAT 0xB4001104
831 #define MEM_STNAND_CMD 0x0
832 #define MEM_STNAND_ADDR 0x4
833 #define MEM_STNAND_DATA 0x20
837 /* Interrupt Controller register offsets */
838 #define IC_CFG0RD 0x40
839 #define IC_CFG0SET 0x40
840 #define IC_CFG0CLR 0x44
841 #define IC_CFG1RD 0x48
842 #define IC_CFG1SET 0x48
843 #define IC_CFG1CLR 0x4C
844 #define IC_CFG2RD 0x50
845 #define IC_CFG2SET 0x50
846 #define IC_CFG2CLR 0x54
847 #define IC_REQ0INT 0x54
848 #define IC_SRCRD 0x58
849 #define IC_SRCSET 0x58
850 #define IC_SRCCLR 0x5C
851 #define IC_REQ1INT 0x5C
852 #define IC_ASSIGNRD 0x60
853 #define IC_ASSIGNSET 0x60
854 #define IC_ASSIGNCLR 0x64
855 #define IC_WAKERD 0x68
856 #define IC_WAKESET 0x68
857 #define IC_WAKECLR 0x6C
858 #define IC_MASKRD 0x70
859 #define IC_MASKSET 0x70
860 #define IC_MASKCLR 0x74
861 #define IC_RISINGRD 0x78
862 #define IC_RISINGCLR 0x78
863 #define IC_FALLINGRD 0x7C
864 #define IC_FALLINGCLR 0x7C
865 #define IC_TESTBIT 0x80
868 /* Interrupt Controller 0 */
869 #define IC0_CFG0RD 0xB0400040
870 #define IC0_CFG0SET 0xB0400040
871 #define IC0_CFG0CLR 0xB0400044
873 #define IC0_CFG1RD 0xB0400048
874 #define IC0_CFG1SET 0xB0400048
875 #define IC0_CFG1CLR 0xB040004C
877 #define IC0_CFG2RD 0xB0400050
878 #define IC0_CFG2SET 0xB0400050
879 #define IC0_CFG2CLR 0xB0400054
881 #define IC0_REQ0INT 0xB0400054
882 #define IC0_SRCRD 0xB0400058
883 #define IC0_SRCSET 0xB0400058
884 #define IC0_SRCCLR 0xB040005C
885 #define IC0_REQ1INT 0xB040005C
887 #define IC0_ASSIGNRD 0xB0400060
888 #define IC0_ASSIGNSET 0xB0400060
889 #define IC0_ASSIGNCLR 0xB0400064
891 #define IC0_WAKERD 0xB0400068
892 #define IC0_WAKESET 0xB0400068
893 #define IC0_WAKECLR 0xB040006C
895 #define IC0_MASKRD 0xB0400070
896 #define IC0_MASKSET 0xB0400070
897 #define IC0_MASKCLR 0xB0400074
899 #define IC0_RISINGRD 0xB0400078
900 #define IC0_RISINGCLR 0xB0400078
901 #define IC0_FALLINGRD 0xB040007C
902 #define IC0_FALLINGCLR 0xB040007C
904 #define IC0_TESTBIT 0xB0400080
906 /* Interrupt Controller 1 */
907 #define IC1_CFG0RD 0xB1800040
908 #define IC1_CFG0SET 0xB1800040
909 #define IC1_CFG0CLR 0xB1800044
911 #define IC1_CFG1RD 0xB1800048
912 #define IC1_CFG1SET 0xB1800048
913 #define IC1_CFG1CLR 0xB180004C
915 #define IC1_CFG2RD 0xB1800050
916 #define IC1_CFG2SET 0xB1800050
917 #define IC1_CFG2CLR 0xB1800054
919 #define IC1_REQ0INT 0xB1800054
920 #define IC1_SRCRD 0xB1800058
921 #define IC1_SRCSET 0xB1800058
922 #define IC1_SRCCLR 0xB180005C
923 #define IC1_REQ1INT 0xB180005C
925 #define IC1_ASSIGNRD 0xB1800060
926 #define IC1_ASSIGNSET 0xB1800060
927 #define IC1_ASSIGNCLR 0xB1800064
929 #define IC1_WAKERD 0xB1800068
930 #define IC1_WAKESET 0xB1800068
931 #define IC1_WAKECLR 0xB180006C
933 #define IC1_MASKRD 0xB1800070
934 #define IC1_MASKSET 0xB1800070
935 #define IC1_MASKCLR 0xB1800074
937 #define IC1_RISINGRD 0xB1800078
938 #define IC1_RISINGCLR 0xB1800078
939 #define IC1_FALLINGRD 0xB180007C
940 #define IC1_FALLINGCLR 0xB180007C
942 #define IC1_TESTBIT 0xB1800080
946 #ifdef CONFIG_SOC_AU1000
948 #define UART0_ADDR 0xB1100000
949 #define UART3_ADDR 0xB1400000
951 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
952 #define USB_HOST_CONFIG 0xB017FFFC
953 #define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
955 #define AU1000_ETH0_BASE 0xB0500000
956 #define AU1000_ETH1_BASE 0xB0510000
957 #define AU1000_MAC0_ENABLE 0xB0520000
958 #define AU1000_MAC1_ENABLE 0xB0520004
959 #define NUM_ETH_INTERFACES 2
960 #endif /* CONFIG_SOC_AU1000 */
963 #ifdef CONFIG_SOC_AU1500
965 #define UART0_ADDR 0xB1100000
966 #define UART3_ADDR 0xB1400000
968 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
969 #define USB_HOST_CONFIG 0xB017fffc
970 #define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
972 #define AU1500_ETH0_BASE 0xB1500000
973 #define AU1500_ETH1_BASE 0xB1510000
974 #define AU1500_MAC0_ENABLE 0xB1520000
975 #define AU1500_MAC1_ENABLE 0xB1520004
976 #define NUM_ETH_INTERFACES 2
977 #endif /* CONFIG_SOC_AU1500 */
980 #ifdef CONFIG_SOC_AU1100
982 #define UART0_ADDR 0xB1100000
983 #define UART3_ADDR 0xB1400000
985 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
986 #define USB_HOST_CONFIG 0xB017FFFC
987 #define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
989 #define AU1100_ETH0_BASE 0xB0500000
990 #define AU1100_MAC0_ENABLE 0xB0520000
991 #define NUM_ETH_INTERFACES 1
992 #endif /* CONFIG_SOC_AU1100 */
994 #ifdef CONFIG_SOC_AU1550
995 #define UART0_ADDR 0xB1100000
997 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
998 #define USB_OHCI_LEN 0x00060000
999 #define USB_HOST_CONFIG 0xB4027ffc
1000 #define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
1002 #define AU1550_ETH0_BASE 0xB0500000
1003 #define AU1550_ETH1_BASE 0xB0510000
1004 #define AU1550_MAC0_ENABLE 0xB0520000
1005 #define AU1550_MAC1_ENABLE 0xB0520004
1006 #define NUM_ETH_INTERFACES 2
1007 #endif /* CONFIG_SOC_AU1550 */
1010 #ifdef CONFIG_SOC_AU1200
1012 #define UART0_ADDR 0xB1100000
1014 #define USB_UOC_BASE 0x14020020
1015 #define USB_UOC_LEN 0x20
1016 #define USB_OHCI_BASE 0x14020100
1017 #define USB_OHCI_LEN 0x100
1018 #define USB_EHCI_BASE 0x14020200
1019 #define USB_EHCI_LEN 0x100
1020 #define USB_UDC_BASE 0x14022000
1021 #define USB_UDC_LEN 0x2000
1022 #define USB_MSR_BASE 0xB4020000
1023 #define USB_MSR_MCFG 4
1024 #define USBMSRMCFG_OMEMEN 0
1025 #define USBMSRMCFG_OBMEN 1
1026 #define USBMSRMCFG_EMEMEN 2
1027 #define USBMSRMCFG_EBMEN 3
1028 #define USBMSRMCFG_DMEMEN 4
1029 #define USBMSRMCFG_DBMEN 5
1030 #define USBMSRMCFG_GMEMEN 6
1031 #define USBMSRMCFG_OHCCLKEN 16
1032 #define USBMSRMCFG_EHCCLKEN 17
1033 #define USBMSRMCFG_UDCCLKEN 18
1034 #define USBMSRMCFG_PHYPLLEN 19
1035 #define USBMSRMCFG_RDCOMB 30
1036 #define USBMSRMCFG_PFEN 31
1038 #define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
1040 #endif /* CONFIG_SOC_AU1200 */
1042 /* Programmable Counters 0 and 1 */
1043 #define SYS_BASE 0xB1900000
1044 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
1045 # define SYS_CNTRL_E1S (1 << 23)
1046 # define SYS_CNTRL_T1S (1 << 20)
1047 # define SYS_CNTRL_M21 (1 << 19)
1048 # define SYS_CNTRL_M11 (1 << 18)
1049 # define SYS_CNTRL_M01 (1 << 17)
1050 # define SYS_CNTRL_C1S (1 << 16)
1051 # define SYS_CNTRL_BP (1 << 14)
1052 # define SYS_CNTRL_EN1 (1 << 13)
1053 # define SYS_CNTRL_BT1 (1 << 12)
1054 # define SYS_CNTRL_EN0 (1 << 11)
1055 # define SYS_CNTRL_BT0 (1 << 10)
1056 # define SYS_CNTRL_E0 (1 << 8)
1057 # define SYS_CNTRL_E0S (1 << 7)
1058 # define SYS_CNTRL_32S (1 << 5)
1059 # define SYS_CNTRL_T0S (1 << 4)
1060 # define SYS_CNTRL_M20 (1 << 3)
1061 # define SYS_CNTRL_M10 (1 << 2)
1062 # define SYS_CNTRL_M00 (1 << 1)
1063 # define SYS_CNTRL_C0S (1 << 0)
1065 /* Programmable Counter 0 Registers */
1066 #define SYS_TOYTRIM (SYS_BASE + 0)
1067 #define SYS_TOYWRITE (SYS_BASE + 4)
1068 #define SYS_TOYMATCH0 (SYS_BASE + 8)
1069 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
1070 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
1071 #define SYS_TOYREAD (SYS_BASE + 0x40)
1073 /* Programmable Counter 1 Registers */
1074 #define SYS_RTCTRIM (SYS_BASE + 0x44)
1075 #define SYS_RTCWRITE (SYS_BASE + 0x48)
1076 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
1077 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
1078 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
1079 #define SYS_RTCREAD (SYS_BASE + 0x58)
1081 /* I2S Controller */
1082 #define I2S_DATA 0xB1000000
1083 # define I2S_DATA_MASK 0xffffff
1084 #define I2S_CONFIG 0xB1000004
1085 # define I2S_CONFIG_XU (1 << 25)
1086 # define I2S_CONFIG_XO (1 << 24)
1087 # define I2S_CONFIG_RU (1 << 23)
1088 # define I2S_CONFIG_RO (1 << 22)
1089 # define I2S_CONFIG_TR (1 << 21)
1090 # define I2S_CONFIG_TE (1 << 20)
1091 # define I2S_CONFIG_TF (1 << 19)
1092 # define I2S_CONFIG_RR (1 << 18)
1093 # define I2S_CONFIG_RE (1 << 17)
1094 # define I2S_CONFIG_RF (1 << 16)
1095 # define I2S_CONFIG_PD (1 << 11)
1096 # define I2S_CONFIG_LB (1 << 10)
1097 # define I2S_CONFIG_IC (1 << 9)
1098 # define I2S_CONFIG_FM_BIT 7
1099 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1100 # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1101 # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1102 # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1103 # define I2S_CONFIG_TN (1 << 6)
1104 # define I2S_CONFIG_RN (1 << 5)
1105 # define I2S_CONFIG_SZ_BIT 0
1106 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1108 #define I2S_CONTROL 0xB1000008
1109 # define I2S_CONTROL_D (1 << 1)
1110 # define I2S_CONTROL_CE (1 << 0)
1112 /* USB Host Controller */
1113 #ifndef USB_OHCI_LEN
1114 #define USB_OHCI_LEN 0x00100000
1117 #ifndef CONFIG_SOC_AU1200
1119 /* USB Device Controller */
1120 #define USBD_EP0RD 0xB0200000
1121 #define USBD_EP0WR 0xB0200004
1122 #define USBD_EP2WR 0xB0200008
1123 #define USBD_EP3WR 0xB020000C
1124 #define USBD_EP4RD 0xB0200010
1125 #define USBD_EP5RD 0xB0200014
1126 #define USBD_INTEN 0xB0200018
1127 #define USBD_INTSTAT 0xB020001C
1128 # define USBDEV_INT_SOF (1 << 12)
1129 # define USBDEV_INT_HF_BIT 6
1130 # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1131 # define USBDEV_INT_CMPLT_BIT 0
1132 # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1133 #define USBD_CONFIG 0xB0200020
1134 #define USBD_EP0CS 0xB0200024
1135 #define USBD_EP2CS 0xB0200028
1136 #define USBD_EP3CS 0xB020002C
1137 #define USBD_EP4CS 0xB0200030
1138 #define USBD_EP5CS 0xB0200034
1139 # define USBDEV_CS_SU (1 << 14)
1140 # define USBDEV_CS_NAK (1 << 13)
1141 # define USBDEV_CS_ACK (1 << 12)
1142 # define USBDEV_CS_BUSY (1 << 11)
1143 # define USBDEV_CS_TSIZE_BIT 1
1144 # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1145 # define USBDEV_CS_STALL (1 << 0)
1146 #define USBD_EP0RDSTAT 0xB0200040
1147 #define USBD_EP0WRSTAT 0xB0200044
1148 #define USBD_EP2WRSTAT 0xB0200048
1149 #define USBD_EP3WRSTAT 0xB020004C
1150 #define USBD_EP4RDSTAT 0xB0200050
1151 #define USBD_EP5RDSTAT 0xB0200054
1152 # define USBDEV_FSTAT_FLUSH (1 << 6)
1153 # define USBDEV_FSTAT_UF (1 << 5)
1154 # define USBDEV_FSTAT_OF (1 << 4)
1155 # define USBDEV_FSTAT_FCNT_BIT 0
1156 # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1157 #define USBD_ENABLE 0xB0200058
1158 # define USBDEV_ENABLE (1 << 1)
1159 # define USBDEV_CE (1 << 0)
1161 #endif /* !CONFIG_SOC_AU1200 */
1163 /* Ethernet Controllers */
1165 /* 4 byte offsets from AU1000_ETH_BASE */
1166 #define MAC_CONTROL 0x0
1167 # define MAC_RX_ENABLE (1 << 2)
1168 # define MAC_TX_ENABLE (1 << 3)
1169 # define MAC_DEF_CHECK (1 << 5)
1170 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
1171 # define MAC_AUTO_PAD (1 << 8)
1172 # define MAC_DISABLE_RETRY (1 << 10)
1173 # define MAC_DISABLE_BCAST (1 << 11)
1174 # define MAC_LATE_COL (1 << 12)
1175 # define MAC_HASH_MODE (1 << 13)
1176 # define MAC_HASH_ONLY (1 << 15)
1177 # define MAC_PASS_ALL (1 << 16)
1178 # define MAC_INVERSE_FILTER (1 << 17)
1179 # define MAC_PROMISCUOUS (1 << 18)
1180 # define MAC_PASS_ALL_MULTI (1 << 19)
1181 # define MAC_FULL_DUPLEX (1 << 20)
1182 # define MAC_NORMAL_MODE 0
1183 # define MAC_INT_LOOPBACK (1 << 21)
1184 # define MAC_EXT_LOOPBACK (1 << 22)
1185 # define MAC_DISABLE_RX_OWN (1 << 23)
1186 # define MAC_BIG_ENDIAN (1 << 30)
1187 # define MAC_RX_ALL (1 << 31)
1188 #define MAC_ADDRESS_HIGH 0x4
1189 #define MAC_ADDRESS_LOW 0x8
1190 #define MAC_MCAST_HIGH 0xC
1191 #define MAC_MCAST_LOW 0x10
1192 #define MAC_MII_CNTRL 0x14
1193 # define MAC_MII_BUSY (1 << 0)
1194 # define MAC_MII_READ 0
1195 # define MAC_MII_WRITE (1 << 1)
1196 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1197 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1198 #define MAC_MII_DATA 0x18
1199 #define MAC_FLOW_CNTRL 0x1C
1200 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
1201 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1202 # define MAC_PASS_CONTROL (1 << 2)
1203 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1204 #define MAC_VLAN1_TAG 0x20
1205 #define MAC_VLAN2_TAG 0x24
1207 /* Ethernet Controller Enable */
1209 # define MAC_EN_CLOCK_ENABLE (1 << 0)
1210 # define MAC_EN_RESET0 (1 << 1)
1211 # define MAC_EN_TOSS (0 << 2)
1212 # define MAC_EN_CACHEABLE (1 << 3)
1213 # define MAC_EN_RESET1 (1 << 4)
1214 # define MAC_EN_RESET2 (1 << 5)
1215 # define MAC_DMA_RESET (1 << 6)
1217 /* Ethernet Controller DMA Channels */
1219 #define MAC0_TX_DMA_ADDR 0xB4004000
1220 #define MAC1_TX_DMA_ADDR 0xB4004200
1221 /* offsets from MAC_TX_RING_ADDR address */
1222 #define MAC_TX_BUFF0_STATUS 0x0
1223 # define TX_FRAME_ABORTED (1 << 0)
1224 # define TX_JAB_TIMEOUT (1 << 1)
1225 # define TX_NO_CARRIER (1 << 2)
1226 # define TX_LOSS_CARRIER (1 << 3)
1227 # define TX_EXC_DEF (1 << 4)
1228 # define TX_LATE_COLL_ABORT (1 << 5)
1229 # define TX_EXC_COLL (1 << 6)
1230 # define TX_UNDERRUN (1 << 7)
1231 # define TX_DEFERRED (1 << 8)
1232 # define TX_LATE_COLL (1 << 9)
1233 # define TX_COLL_CNT_MASK (0xF << 10)
1234 # define TX_PKT_RETRY (1 << 31)
1235 #define MAC_TX_BUFF0_ADDR 0x4
1236 # define TX_DMA_ENABLE (1 << 0)
1237 # define TX_T_DONE (1 << 1)
1238 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1239 #define MAC_TX_BUFF0_LEN 0x8
1240 #define MAC_TX_BUFF1_STATUS 0x10
1241 #define MAC_TX_BUFF1_ADDR 0x14
1242 #define MAC_TX_BUFF1_LEN 0x18
1243 #define MAC_TX_BUFF2_STATUS 0x20
1244 #define MAC_TX_BUFF2_ADDR 0x24
1245 #define MAC_TX_BUFF2_LEN 0x28
1246 #define MAC_TX_BUFF3_STATUS 0x30
1247 #define MAC_TX_BUFF3_ADDR 0x34
1248 #define MAC_TX_BUFF3_LEN 0x38
1250 #define MAC0_RX_DMA_ADDR 0xB4004100
1251 #define MAC1_RX_DMA_ADDR 0xB4004300
1252 /* offsets from MAC_RX_RING_ADDR */
1253 #define MAC_RX_BUFF0_STATUS 0x0
1254 # define RX_FRAME_LEN_MASK 0x3fff
1255 # define RX_WDOG_TIMER (1 << 14)
1256 # define RX_RUNT (1 << 15)
1257 # define RX_OVERLEN (1 << 16)
1258 # define RX_COLL (1 << 17)
1259 # define RX_ETHER (1 << 18)
1260 # define RX_MII_ERROR (1 << 19)
1261 # define RX_DRIBBLING (1 << 20)
1262 # define RX_CRC_ERROR (1 << 21)
1263 # define RX_VLAN1 (1 << 22)
1264 # define RX_VLAN2 (1 << 23)
1265 # define RX_LEN_ERROR (1 << 24)
1266 # define RX_CNTRL_FRAME (1 << 25)
1267 # define RX_U_CNTRL_FRAME (1 << 26)
1268 # define RX_MCAST_FRAME (1 << 27)
1269 # define RX_BCAST_FRAME (1 << 28)
1270 # define RX_FILTER_FAIL (1 << 29)
1271 # define RX_PACKET_FILTER (1 << 30)
1272 # define RX_MISSED_FRAME (1 << 31)
1274 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1275 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1276 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1277 #define MAC_RX_BUFF0_ADDR 0x4
1278 # define RX_DMA_ENABLE (1 << 0)
1279 # define RX_T_DONE (1 << 1)
1280 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1281 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1282 #define MAC_RX_BUFF1_STATUS 0x10
1283 #define MAC_RX_BUFF1_ADDR 0x14
1284 #define MAC_RX_BUFF2_STATUS 0x20
1285 #define MAC_RX_BUFF2_ADDR 0x24
1286 #define MAC_RX_BUFF3_STATUS 0x30
1287 #define MAC_RX_BUFF3_ADDR 0x34
1289 #define UART_RX 0 /* Receive buffer */
1290 #define UART_TX 4 /* Transmit buffer */
1291 #define UART_IER 8 /* Interrupt Enable Register */
1292 #define UART_IIR 0xC /* Interrupt ID Register */
1293 #define UART_FCR 0x10 /* FIFO Control Register */
1294 #define UART_LCR 0x14 /* Line Control Register */
1295 #define UART_MCR 0x18 /* Modem Control Register */
1296 #define UART_LSR 0x1C /* Line Status Register */
1297 #define UART_MSR 0x20 /* Modem Status Register */
1298 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
1299 #define UART_MOD_CNTRL 0x100 /* Module Control */
1302 #define SSI0_STATUS 0xB1600000
1303 # define SSI_STATUS_BF (1 << 4)
1304 # define SSI_STATUS_OF (1 << 3)
1305 # define SSI_STATUS_UF (1 << 2)
1306 # define SSI_STATUS_D (1 << 1)
1307 # define SSI_STATUS_B (1 << 0)
1308 #define SSI0_INT 0xB1600004
1309 # define SSI_INT_OI (1 << 3)
1310 # define SSI_INT_UI (1 << 2)
1311 # define SSI_INT_DI (1 << 1)
1312 #define SSI0_INT_ENABLE 0xB1600008
1313 # define SSI_INTE_OIE (1 << 3)
1314 # define SSI_INTE_UIE (1 << 2)
1315 # define SSI_INTE_DIE (1 << 1)
1316 #define SSI0_CONFIG 0xB1600020
1317 # define SSI_CONFIG_AO (1 << 24)
1318 # define SSI_CONFIG_DO (1 << 23)
1319 # define SSI_CONFIG_ALEN_BIT 20
1320 # define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1321 # define SSI_CONFIG_DLEN_BIT 16
1322 # define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1323 # define SSI_CONFIG_DD (1 << 11)
1324 # define SSI_CONFIG_AD (1 << 10)
1325 # define SSI_CONFIG_BM_BIT 8
1326 # define SSI_CONFIG_BM_MASK (0x3 << 8)
1327 # define SSI_CONFIG_CE (1 << 7)
1328 # define SSI_CONFIG_DP (1 << 6)
1329 # define SSI_CONFIG_DL (1 << 5)
1330 # define SSI_CONFIG_EP (1 << 4)
1331 #define SSI0_ADATA 0xB1600024
1332 # define SSI_AD_D (1 << 24)
1333 # define SSI_AD_ADDR_BIT 16
1334 # define SSI_AD_ADDR_MASK (0xff << 16)
1335 # define SSI_AD_DATA_BIT 0
1336 # define SSI_AD_DATA_MASK (0xfff << 0)
1337 #define SSI0_CLKDIV 0xB1600028
1338 #define SSI0_CONTROL 0xB1600100
1339 # define SSI_CONTROL_CD (1 << 1)
1340 # define SSI_CONTROL_E (1 << 0)
1343 #define SSI1_STATUS 0xB1680000
1344 #define SSI1_INT 0xB1680004
1345 #define SSI1_INT_ENABLE 0xB1680008
1346 #define SSI1_CONFIG 0xB1680020
1347 #define SSI1_ADATA 0xB1680024
1348 #define SSI1_CLKDIV 0xB1680028
1349 #define SSI1_ENABLE 0xB1680100
1352 * Register content definitions
1354 #define SSI_STATUS_BF (1 << 4)
1355 #define SSI_STATUS_OF (1 << 3)
1356 #define SSI_STATUS_UF (1 << 2)
1357 #define SSI_STATUS_D (1 << 1)
1358 #define SSI_STATUS_B (1 << 0)
1361 #define SSI_INT_OI (1 << 3)
1362 #define SSI_INT_UI (1 << 2)
1363 #define SSI_INT_DI (1 << 1)
1366 #define SSI_INTEN_OIE (1 << 3)
1367 #define SSI_INTEN_UIE (1 << 2)
1368 #define SSI_INTEN_DIE (1 << 1)
1370 #define SSI_CONFIG_AO (1 << 24)
1371 #define SSI_CONFIG_DO (1 << 23)
1372 #define SSI_CONFIG_ALEN (7 << 20)
1373 #define SSI_CONFIG_DLEN (15 << 16)
1374 #define SSI_CONFIG_DD (1 << 11)
1375 #define SSI_CONFIG_AD (1 << 10)
1376 #define SSI_CONFIG_BM (3 << 8)
1377 #define SSI_CONFIG_CE (1 << 7)
1378 #define SSI_CONFIG_DP (1 << 6)
1379 #define SSI_CONFIG_DL (1 << 5)
1380 #define SSI_CONFIG_EP (1 << 4)
1381 #define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1382 #define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1383 #define SSI_CONFIG_BM_HI (0 << 8)
1384 #define SSI_CONFIG_BM_LO (1 << 8)
1385 #define SSI_CONFIG_BM_CY (2 << 8)
1387 #define SSI_ADATA_D (1 << 24)
1388 #define SSI_ADATA_ADDR (0xFF << 16)
1389 #define SSI_ADATA_DATA 0x0FFF
1390 #define SSI_ADATA_ADDR_N(N) (N << 16)
1392 #define SSI_ENABLE_CD (1 << 1)
1393 #define SSI_ENABLE_E (1 << 0)
1395 /* IrDA Controller */
1396 #define IRDA_BASE 0xB0300000
1397 #define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1398 #define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1399 #define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1400 #define IR_RING_SIZE (IRDA_BASE + 0x0C)
1401 #define IR_RING_PROMPT (IRDA_BASE + 0x10)
1402 #define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1403 #define IR_INT_CLEAR (IRDA_BASE + 0x18)
1404 #define IR_CONFIG_1 (IRDA_BASE + 0x20)
1405 # define IR_RX_INVERT_LED (1 << 0)
1406 # define IR_TX_INVERT_LED (1 << 1)
1407 # define IR_ST (1 << 2)
1408 # define IR_SF (1 << 3)
1409 # define IR_SIR (1 << 4)
1410 # define IR_MIR (1 << 5)
1411 # define IR_FIR (1 << 6)
1412 # define IR_16CRC (1 << 7)
1413 # define IR_TD (1 << 8)
1414 # define IR_RX_ALL (1 << 9)
1415 # define IR_DMA_ENABLE (1 << 10)
1416 # define IR_RX_ENABLE (1 << 11)
1417 # define IR_TX_ENABLE (1 << 12)
1418 # define IR_LOOPBACK (1 << 14)
1419 # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1420 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1421 #define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1422 #define IR_ENABLE (IRDA_BASE + 0x28)
1423 # define IR_RX_STATUS (1 << 9)
1424 # define IR_TX_STATUS (1 << 10)
1425 #define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1426 #define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1427 #define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1428 #define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1429 #define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1430 # define IR_MODE_INV (1 << 0)
1431 # define IR_ONE_PIN (1 << 1)
1432 #define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1435 #define SYS_PINFUNC 0xB190002C
1436 # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1437 # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1438 # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1439 # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1440 # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1441 # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1442 # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1443 # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1444 # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1445 # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1446 # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1447 # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1448 # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1449 # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1450 # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1451 # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1454 # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1455 # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1456 # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1457 # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1459 /* Au1550 only. Redefines lots of pins */
1460 # define SYS_PF_PSC2_MASK (7 << 17)
1461 # define SYS_PF_PSC2_AC97 0
1462 # define SYS_PF_PSC2_SPI 0
1463 # define SYS_PF_PSC2_I2S (1 << 17)
1464 # define SYS_PF_PSC2_SMBUS (3 << 17)
1465 # define SYS_PF_PSC2_GPIO (7 << 17)
1466 # define SYS_PF_PSC3_MASK (7 << 20)
1467 # define SYS_PF_PSC3_AC97 0
1468 # define SYS_PF_PSC3_SPI 0
1469 # define SYS_PF_PSC3_I2S (1 << 20)
1470 # define SYS_PF_PSC3_SMBUS (3 << 20)
1471 # define SYS_PF_PSC3_GPIO (7 << 20)
1472 # define SYS_PF_PSC1_S1 (1 << 1)
1473 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1476 #ifdef CONFIG_SOC_AU1200
1477 #define SYS_PINFUNC_DMA (1 << 31)
1478 #define SYS_PINFUNC_S0A (1 << 30)
1479 #define SYS_PINFUNC_S1A (1 << 29)
1480 #define SYS_PINFUNC_LP0 (1 << 28)
1481 #define SYS_PINFUNC_LP1 (1 << 27)
1482 #define SYS_PINFUNC_LD16 (1 << 26)
1483 #define SYS_PINFUNC_LD8 (1 << 25)
1484 #define SYS_PINFUNC_LD1 (1 << 24)
1485 #define SYS_PINFUNC_LD0 (1 << 23)
1486 #define SYS_PINFUNC_P1A (3 << 21)
1487 #define SYS_PINFUNC_P1B (1 << 20)
1488 #define SYS_PINFUNC_FS3 (1 << 19)
1489 #define SYS_PINFUNC_P0A (3 << 17)
1490 #define SYS_PINFUNC_CS (1 << 16)
1491 #define SYS_PINFUNC_CIM (1 << 15)
1492 #define SYS_PINFUNC_P1C (1 << 14)
1493 #define SYS_PINFUNC_U1T (1 << 12)
1494 #define SYS_PINFUNC_U1R (1 << 11)
1495 #define SYS_PINFUNC_EX1 (1 << 10)
1496 #define SYS_PINFUNC_EX0 (1 << 9)
1497 #define SYS_PINFUNC_U0R (1 << 8)
1498 #define SYS_PINFUNC_MC (1 << 7)
1499 #define SYS_PINFUNC_S0B (1 << 6)
1500 #define SYS_PINFUNC_S0C (1 << 5)
1501 #define SYS_PINFUNC_P0B (1 << 4)
1502 #define SYS_PINFUNC_U0T (1 << 3)
1503 #define SYS_PINFUNC_S1B (1 << 2)
1506 #define SYS_TRIOUTRD 0xB1900100
1507 #define SYS_TRIOUTCLR 0xB1900100
1508 #define SYS_OUTPUTRD 0xB1900108
1509 #define SYS_OUTPUTSET 0xB1900108
1510 #define SYS_OUTPUTCLR 0xB190010C
1511 #define SYS_PINSTATERD 0xB1900110
1512 #define SYS_PININPUTEN 0xB1900110
1514 /* GPIO2, Au1500, Au1550 only */
1515 #define GPIO2_BASE 0xB1700000
1516 #define GPIO2_DIR (GPIO2_BASE + 0)
1517 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
1518 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1519 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1520 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1522 /* Power Management */
1523 #define SYS_SCRATCH0 0xB1900018
1524 #define SYS_SCRATCH1 0xB190001C
1525 #define SYS_WAKEMSK 0xB1900034
1526 #define SYS_ENDIAN 0xB1900038
1527 #define SYS_POWERCTRL 0xB190003C
1528 #define SYS_WAKESRC 0xB190005C
1529 #define SYS_SLPPWR 0xB1900078
1530 #define SYS_SLEEP 0xB190007C
1532 #define SYS_WAKEMSK_D2 (1 << 9)
1533 #define SYS_WAKEMSK_M2 (1 << 8)
1534 #define SYS_WAKEMSK_GPIO(x) (1 << (x))
1536 /* Clock Controller */
1537 #define SYS_FREQCTRL0 0xB1900020
1538 # define SYS_FC_FRDIV2_BIT 22
1539 # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1540 # define SYS_FC_FE2 (1 << 21)
1541 # define SYS_FC_FS2 (1 << 20)
1542 # define SYS_FC_FRDIV1_BIT 12
1543 # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1544 # define SYS_FC_FE1 (1 << 11)
1545 # define SYS_FC_FS1 (1 << 10)
1546 # define SYS_FC_FRDIV0_BIT 2
1547 # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1548 # define SYS_FC_FE0 (1 << 1)
1549 # define SYS_FC_FS0 (1 << 0)
1550 #define SYS_FREQCTRL1 0xB1900024
1551 # define SYS_FC_FRDIV5_BIT 22
1552 # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1553 # define SYS_FC_FE5 (1 << 21)
1554 # define SYS_FC_FS5 (1 << 20)
1555 # define SYS_FC_FRDIV4_BIT 12
1556 # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1557 # define SYS_FC_FE4 (1 << 11)
1558 # define SYS_FC_FS4 (1 << 10)
1559 # define SYS_FC_FRDIV3_BIT 2
1560 # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1561 # define SYS_FC_FE3 (1 << 1)
1562 # define SYS_FC_FS3 (1 << 0)
1563 #define SYS_CLKSRC 0xB1900028
1564 # define SYS_CS_ME1_BIT 27
1565 # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1566 # define SYS_CS_DE1 (1 << 26)
1567 # define SYS_CS_CE1 (1 << 25)
1568 # define SYS_CS_ME0_BIT 22
1569 # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1570 # define SYS_CS_DE0 (1 << 21)
1571 # define SYS_CS_CE0 (1 << 20)
1572 # define SYS_CS_MI2_BIT 17
1573 # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1574 # define SYS_CS_DI2 (1 << 16)
1575 # define SYS_CS_CI2 (1 << 15)
1576 #ifdef CONFIG_SOC_AU1100
1577 # define SYS_CS_ML_BIT 7
1578 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1579 # define SYS_CS_DL (1 << 6)
1580 # define SYS_CS_CL (1 << 5)
1582 # define SYS_CS_MUH_BIT 12
1583 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1584 # define SYS_CS_DUH (1 << 11)
1585 # define SYS_CS_CUH (1 << 10)
1586 # define SYS_CS_MUD_BIT 7
1587 # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1588 # define SYS_CS_DUD (1 << 6)
1589 # define SYS_CS_CUD (1 << 5)
1591 # define SYS_CS_MIR_BIT 2
1592 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1593 # define SYS_CS_DIR (1 << 1)
1594 # define SYS_CS_CIR (1 << 0)
1596 # define SYS_CS_MUX_AUX 0x1
1597 # define SYS_CS_MUX_FQ0 0x2
1598 # define SYS_CS_MUX_FQ1 0x3
1599 # define SYS_CS_MUX_FQ2 0x4
1600 # define SYS_CS_MUX_FQ3 0x5
1601 # define SYS_CS_MUX_FQ4 0x6
1602 # define SYS_CS_MUX_FQ5 0x7
1603 #define SYS_CPUPLL 0xB1900060
1604 #define SYS_AUXPLL 0xB1900064
1606 /* AC97 Controller */
1607 #define AC97C_CONFIG 0xB0000000
1608 # define AC97C_RECV_SLOTS_BIT 13
1609 # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1610 # define AC97C_XMIT_SLOTS_BIT 3
1611 # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1612 # define AC97C_SG (1 << 2)
1613 # define AC97C_SYNC (1 << 1)
1614 # define AC97C_RESET (1 << 0)
1615 #define AC97C_STATUS 0xB0000004
1616 # define AC97C_XU (1 << 11)
1617 # define AC97C_XO (1 << 10)
1618 # define AC97C_RU (1 << 9)
1619 # define AC97C_RO (1 << 8)
1620 # define AC97C_READY (1 << 7)
1621 # define AC97C_CP (1 << 6)
1622 # define AC97C_TR (1 << 5)
1623 # define AC97C_TE (1 << 4)
1624 # define AC97C_TF (1 << 3)
1625 # define AC97C_RR (1 << 2)
1626 # define AC97C_RE (1 << 1)
1627 # define AC97C_RF (1 << 0)
1628 #define AC97C_DATA 0xB0000008
1629 #define AC97C_CMD 0xB000000C
1630 # define AC97C_WD_BIT 16
1631 # define AC97C_READ (1 << 7)
1632 # define AC97C_INDEX_MASK 0x7f
1633 #define AC97C_CNTRL 0xB0000010
1634 # define AC97C_RS (1 << 1)
1635 # define AC97C_CE (1 << 0)
1637 /* Secure Digital (SD) Controller */
1638 #define SD0_XMIT_FIFO 0xB0600000
1639 #define SD0_RECV_FIFO 0xB0600004
1640 #define SD1_XMIT_FIFO 0xB0680000
1641 #define SD1_RECV_FIFO 0xB0680004
1643 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1644 /* Au1500 PCI Controller */
1645 #define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1646 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1647 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1648 # define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1649 (1 << 25) | (1 << 26) | (1 << 27))
1650 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1651 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1652 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1653 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1654 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1655 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1656 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1657 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1658 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1659 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1660 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1661 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1663 #define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1666 * All of our structures, like PCI resource, have 32-bit members.
1667 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1668 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1669 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1670 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1671 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1672 * ourselves and then adjust the device's resources.
1674 #define Au1500_EXT_CFG 0x600000000ULL
1675 #define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1676 #define Au1500_PCI_IO_START 0x500000000ULL
1677 #define Au1500_PCI_IO_END 0x5000FFFFFULL
1678 #define Au1500_PCI_MEM_START 0x440000000ULL
1679 #define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1681 #define PCI_IO_START 0x00001000
1682 #define PCI_IO_END 0x000FFFFF
1683 #define PCI_MEM_START 0x40000000
1684 #define PCI_MEM_END 0x4FFFFFFF
1686 #define PCI_FIRST_DEVFN (0 << 3)
1687 #define PCI_LAST_DEVFN (19 << 3)
1689 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1690 #define IOPORT_RESOURCE_END 0xffffffff
1691 #define IOMEM_RESOURCE_START 0x10000000
1692 #define IOMEM_RESOURCE_END 0xfffffffffULL
1694 #else /* Au1000 and Au1100 and Au1200 */
1696 /* Don't allow any legacy ports probing */
1697 #define IOPORT_RESOURCE_START 0x10000000
1698 #define IOPORT_RESOURCE_END 0xffffffff
1699 #define IOMEM_RESOURCE_START 0x10000000
1700 #define IOMEM_RESOURCE_END 0xfffffffffULL
1702 #define PCI_IO_START 0
1703 #define PCI_IO_END 0
1704 #define PCI_MEM_START 0
1705 #define PCI_MEM_END 0
1706 #define PCI_FIRST_DEVFN 0
1707 #define PCI_LAST_DEVFN 0