3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
38 #ifndef _LANGUAGE_ASSEMBLY
40 #include <linux/delay.h>
41 #include <linux/types.h>
44 #include <linux/irq.h>
46 /* cpu pipeline flush */
47 void static inline au_sync(void)
49 __asm__ volatile ("sync");
52 void static inline au_sync_udelay(int us)
54 __asm__ volatile ("sync");
58 void static inline au_sync_delay(int ms)
60 __asm__ volatile ("sync");
64 void static inline au_writeb(u8 val, unsigned long reg)
66 *(volatile u8 *)reg = val;
69 void static inline au_writew(u16 val, unsigned long reg)
71 *(volatile u16 *)reg = val;
74 void static inline au_writel(u32 val, unsigned long reg)
76 *(volatile u32 *)reg = val;
79 static inline u8 au_readb(unsigned long reg)
81 return *(volatile u8 *)reg;
84 static inline u16 au_readw(unsigned long reg)
86 return *(volatile u16 *)reg;
89 static inline u32 au_readl(unsigned long reg)
91 return *(volatile u32 *)reg;
94 /* Early Au1000 have a write-only SYS_CPUPLL register. */
95 static inline int au1xxx_cpu_has_pll_wo(void)
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
106 /* does CPU need CONFIG[OD] set to fix tons of errata? */
107 static inline int au1xxx_cpu_needs_config_od(void)
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
133 #define ALCHEMY_CPU_UNKNOWN -1
134 #define ALCHEMY_CPU_AU1000 0
135 #define ALCHEMY_CPU_AU1500 1
136 #define ALCHEMY_CPU_AU1100 2
137 #define ALCHEMY_CPU_AU1550 3
138 #define ALCHEMY_CPU_AU1200 4
140 static inline int alchemy_get_cputype(void)
142 switch (read_c0_prid() & 0xffff0000) {
144 return ALCHEMY_CPU_AU1000;
147 return ALCHEMY_CPU_AU1500;
150 return ALCHEMY_CPU_AU1100;
153 return ALCHEMY_CPU_AU1550;
157 return ALCHEMY_CPU_AU1200;
161 return ALCHEMY_CPU_UNKNOWN;
164 static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
166 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
169 /* check LSR TX_EMPTY bit */
172 if (__raw_readl(base + 0x1c) & 0x20)
175 for (i = 10000; i; i--)
176 asm volatile ("nop");
179 __raw_writel(c, base + 0x04); /* tx */
183 /* arch/mips/au1000/common/clocks.c */
184 extern void set_au1x00_speed(unsigned int new_freq);
185 extern unsigned int get_au1x00_speed(void);
186 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
187 extern unsigned long get_au1x00_uart_baud_base(void);
188 extern unsigned long au1xxx_calc_clock(void);
190 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
191 void alchemy_sleep_au1000(void);
192 void alchemy_sleep_au1550(void);
196 /* SOC Interrupt numbers */
198 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
199 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
200 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
201 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
202 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
204 enum soc_au1000_ints {
205 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
206 AU1000_UART0_INT = AU1000_FIRST_INT,
214 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
215 AU1000_TOY_MATCH0_INT,
216 AU1000_TOY_MATCH1_INT,
217 AU1000_TOY_MATCH2_INT,
219 AU1000_RTC_MATCH0_INT,
220 AU1000_RTC_MATCH1_INT,
221 AU1000_RTC_MATCH2_INT,
224 AU1000_USB_DEV_REQ_INT,
225 AU1000_USB_DEV_SUS_INT,
266 enum soc_au1100_ints {
267 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
268 AU1100_UART0_INT = AU1100_FIRST_INT,
276 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
277 AU1100_TOY_MATCH0_INT,
278 AU1100_TOY_MATCH1_INT,
279 AU1100_TOY_MATCH2_INT,
281 AU1100_RTC_MATCH0_INT,
282 AU1100_RTC_MATCH1_INT,
283 AU1100_RTC_MATCH2_INT,
286 AU1100_USB_DEV_REQ_INT,
287 AU1100_USB_DEV_SUS_INT,
291 AU1100_GPIO208_215_INT,
328 enum soc_au1500_ints {
329 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
330 AU1500_UART0_INT = AU1500_FIRST_INT,
338 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
339 AU1500_TOY_MATCH0_INT,
340 AU1500_TOY_MATCH1_INT,
341 AU1500_TOY_MATCH2_INT,
343 AU1500_RTC_MATCH0_INT,
344 AU1500_RTC_MATCH1_INT,
345 AU1500_RTC_MATCH2_INT,
348 AU1500_USB_DEV_REQ_INT,
349 AU1500_USB_DEV_SUS_INT,
354 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
386 AU1500_GPIO208_215_INT,
389 enum soc_au1550_ints {
390 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
391 AU1550_UART0_INT = AU1550_FIRST_INT,
406 AU1550_TOY_MATCH0_INT,
407 AU1550_TOY_MATCH1_INT,
408 AU1550_TOY_MATCH2_INT,
410 AU1550_RTC_MATCH0_INT,
411 AU1550_RTC_MATCH1_INT,
412 AU1550_RTC_MATCH2_INT,
414 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
415 AU1550_USB_DEV_REQ_INT,
416 AU1550_USB_DEV_SUS_INT,
420 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
437 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
451 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
454 enum soc_au1200_ints {
455 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
456 AU1200_UART0_INT = AU1200_FIRST_INT,
471 AU1200_TOY_MATCH0_INT,
472 AU1200_TOY_MATCH1_INT,
473 AU1200_TOY_MATCH2_INT,
475 AU1200_RTC_MATCH0_INT,
476 AU1200_RTC_MATCH1_INT,
477 AU1200_RTC_MATCH2_INT,
484 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
522 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
525 * SDRAM register offsets
527 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
528 defined(CONFIG_SOC_AU1100)
529 #define MEM_SDMODE0 0x0000
530 #define MEM_SDMODE1 0x0004
531 #define MEM_SDMODE2 0x0008
532 #define MEM_SDADDR0 0x000C
533 #define MEM_SDADDR1 0x0010
534 #define MEM_SDADDR2 0x0014
535 #define MEM_SDREFCFG 0x0018
536 #define MEM_SDPRECMD 0x001C
537 #define MEM_SDAUTOREF 0x0020
538 #define MEM_SDWRMD0 0x0024
539 #define MEM_SDWRMD1 0x0028
540 #define MEM_SDWRMD2 0x002C
541 #define MEM_SDSLEEP 0x0030
542 #define MEM_SDSMCKE 0x0034
545 * MEM_SDMODE register content definitions
547 #define MEM_SDMODE_F (1 << 22)
548 #define MEM_SDMODE_SR (1 << 21)
549 #define MEM_SDMODE_BS (1 << 20)
550 #define MEM_SDMODE_RS (3 << 18)
551 #define MEM_SDMODE_CS (7 << 15)
552 #define MEM_SDMODE_TRAS (15 << 11)
553 #define MEM_SDMODE_TMRD (3 << 9)
554 #define MEM_SDMODE_TWR (3 << 7)
555 #define MEM_SDMODE_TRP (3 << 5)
556 #define MEM_SDMODE_TRCD (3 << 3)
557 #define MEM_SDMODE_TCL (7 << 0)
559 #define MEM_SDMODE_BS_2Bank (0 << 20)
560 #define MEM_SDMODE_BS_4Bank (1 << 20)
561 #define MEM_SDMODE_RS_11Row (0 << 18)
562 #define MEM_SDMODE_RS_12Row (1 << 18)
563 #define MEM_SDMODE_RS_13Row (2 << 18)
564 #define MEM_SDMODE_RS_N(N) ((N) << 18)
565 #define MEM_SDMODE_CS_7Col (0 << 15)
566 #define MEM_SDMODE_CS_8Col (1 << 15)
567 #define MEM_SDMODE_CS_9Col (2 << 15)
568 #define MEM_SDMODE_CS_10Col (3 << 15)
569 #define MEM_SDMODE_CS_11Col (4 << 15)
570 #define MEM_SDMODE_CS_N(N) ((N) << 15)
571 #define MEM_SDMODE_TRAS_N(N) ((N) << 11)
572 #define MEM_SDMODE_TMRD_N(N) ((N) << 9)
573 #define MEM_SDMODE_TWR_N(N) ((N) << 7)
574 #define MEM_SDMODE_TRP_N(N) ((N) << 5)
575 #define MEM_SDMODE_TRCD_N(N) ((N) << 3)
576 #define MEM_SDMODE_TCL_N(N) ((N) << 0)
579 * MEM_SDADDR register contents definitions
581 #define MEM_SDADDR_E (1 << 20)
582 #define MEM_SDADDR_CSBA (0x03FF << 10)
583 #define MEM_SDADDR_CSMASK (0x03FF << 0)
584 #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
585 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
588 * MEM_SDREFCFG register content definitions
590 #define MEM_SDREFCFG_TRC (15 << 28)
591 #define MEM_SDREFCFG_TRPM (3 << 26)
592 #define MEM_SDREFCFG_E (1 << 25)
593 #define MEM_SDREFCFG_RE (0x1ffffff << 0)
594 #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
595 #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
596 #define MEM_SDREFCFG_REF_N(N) (N)
599 /***********************************************************************/
602 * Au1550 SDRAM Register Offsets
605 /***********************************************************************/
607 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
608 #define MEM_SDMODE0 0x0800
609 #define MEM_SDMODE1 0x0808
610 #define MEM_SDMODE2 0x0810
611 #define MEM_SDADDR0 0x0820
612 #define MEM_SDADDR1 0x0828
613 #define MEM_SDADDR2 0x0830
614 #define MEM_SDCONFIGA 0x0840
615 #define MEM_SDCONFIGB 0x0848
616 #define MEM_SDSTAT 0x0850
617 #define MEM_SDERRADDR 0x0858
618 #define MEM_SDSTRIDE0 0x0860
619 #define MEM_SDSTRIDE1 0x0868
620 #define MEM_SDSTRIDE2 0x0870
621 #define MEM_SDWRMD0 0x0880
622 #define MEM_SDWRMD1 0x0888
623 #define MEM_SDWRMD2 0x0890
624 #define MEM_SDPRECMD 0x08C0
625 #define MEM_SDAUTOREF 0x08C8
626 #define MEM_SDSREF 0x08D0
627 #define MEM_SDSLEEP MEM_SDSREF
632 * Physical base addresses for integrated peripherals
633 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
636 #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
637 #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
640 #ifdef CONFIG_SOC_AU1000
641 #define MEM_PHYS_ADDR 0x14000000
642 #define STATIC_MEM_PHYS_ADDR 0x14001000
643 #define DMA0_PHYS_ADDR 0x14002000
644 #define DMA1_PHYS_ADDR 0x14002100
645 #define DMA2_PHYS_ADDR 0x14002200
646 #define DMA3_PHYS_ADDR 0x14002300
647 #define DMA4_PHYS_ADDR 0x14002400
648 #define DMA5_PHYS_ADDR 0x14002500
649 #define DMA6_PHYS_ADDR 0x14002600
650 #define DMA7_PHYS_ADDR 0x14002700
651 #define AC97_PHYS_ADDR 0x10000000
652 #define USBH_PHYS_ADDR 0x10100000
653 #define USBD_PHYS_ADDR 0x10200000
654 #define IRDA_PHYS_ADDR 0x10300000
655 #define MAC0_PHYS_ADDR 0x10500000
656 #define MAC1_PHYS_ADDR 0x10510000
657 #define MACEN_PHYS_ADDR 0x10520000
658 #define MACDMA0_PHYS_ADDR 0x14004000
659 #define MACDMA1_PHYS_ADDR 0x14004200
660 #define I2S_PHYS_ADDR 0x11000000
661 #define UART0_PHYS_ADDR 0x11100000
662 #define UART1_PHYS_ADDR 0x11200000
663 #define UART2_PHYS_ADDR 0x11300000
664 #define UART3_PHYS_ADDR 0x11400000
665 #define SSI0_PHYS_ADDR 0x11600000
666 #define SSI1_PHYS_ADDR 0x11680000
667 #define SYS_PHYS_ADDR 0x11900000
668 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
669 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
670 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
673 /********************************************************************/
675 #ifdef CONFIG_SOC_AU1500
676 #define MEM_PHYS_ADDR 0x14000000
677 #define STATIC_MEM_PHYS_ADDR 0x14001000
678 #define DMA0_PHYS_ADDR 0x14002000
679 #define DMA1_PHYS_ADDR 0x14002100
680 #define DMA2_PHYS_ADDR 0x14002200
681 #define DMA3_PHYS_ADDR 0x14002300
682 #define DMA4_PHYS_ADDR 0x14002400
683 #define DMA5_PHYS_ADDR 0x14002500
684 #define DMA6_PHYS_ADDR 0x14002600
685 #define DMA7_PHYS_ADDR 0x14002700
686 #define AC97_PHYS_ADDR 0x10000000
687 #define USBH_PHYS_ADDR 0x10100000
688 #define USBD_PHYS_ADDR 0x10200000
689 #define PCI_PHYS_ADDR 0x14005000
690 #define MAC0_PHYS_ADDR 0x11500000
691 #define MAC1_PHYS_ADDR 0x11510000
692 #define MACEN_PHYS_ADDR 0x11520000
693 #define MACDMA0_PHYS_ADDR 0x14004000
694 #define MACDMA1_PHYS_ADDR 0x14004200
695 #define I2S_PHYS_ADDR 0x11000000
696 #define UART0_PHYS_ADDR 0x11100000
697 #define UART3_PHYS_ADDR 0x11400000
698 #define GPIO2_PHYS_ADDR 0x11700000
699 #define SYS_PHYS_ADDR 0x11900000
700 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
701 #define PCI_IO_PHYS_ADDR 0x500000000ULL
702 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
703 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
704 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
705 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
706 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
709 /********************************************************************/
711 #ifdef CONFIG_SOC_AU1100
712 #define MEM_PHYS_ADDR 0x14000000
713 #define STATIC_MEM_PHYS_ADDR 0x14001000
714 #define DMA0_PHYS_ADDR 0x14002000
715 #define DMA1_PHYS_ADDR 0x14002100
716 #define DMA2_PHYS_ADDR 0x14002200
717 #define DMA3_PHYS_ADDR 0x14002300
718 #define DMA4_PHYS_ADDR 0x14002400
719 #define DMA5_PHYS_ADDR 0x14002500
720 #define DMA6_PHYS_ADDR 0x14002600
721 #define DMA7_PHYS_ADDR 0x14002700
722 #define SD0_PHYS_ADDR 0x10600000
723 #define SD1_PHYS_ADDR 0x10680000
724 #define AC97_PHYS_ADDR 0x10000000
725 #define USBH_PHYS_ADDR 0x10100000
726 #define USBD_PHYS_ADDR 0x10200000
727 #define IRDA_PHYS_ADDR 0x10300000
728 #define MAC0_PHYS_ADDR 0x10500000
729 #define MACEN_PHYS_ADDR 0x10520000
730 #define MACDMA0_PHYS_ADDR 0x14004000
731 #define MACDMA1_PHYS_ADDR 0x14004200
732 #define I2S_PHYS_ADDR 0x11000000
733 #define UART0_PHYS_ADDR 0x11100000
734 #define UART1_PHYS_ADDR 0x11200000
735 #define UART3_PHYS_ADDR 0x11400000
736 #define SSI0_PHYS_ADDR 0x11600000
737 #define SSI1_PHYS_ADDR 0x11680000
738 #define GPIO2_PHYS_ADDR 0x11700000
739 #define SYS_PHYS_ADDR 0x11900000
740 #define LCD_PHYS_ADDR 0x15000000
741 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
742 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
743 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
746 /***********************************************************************/
748 #ifdef CONFIG_SOC_AU1550
749 #define MEM_PHYS_ADDR 0x14000000
750 #define STATIC_MEM_PHYS_ADDR 0x14001000
751 #define USBH_PHYS_ADDR 0x14020000
752 #define USBD_PHYS_ADDR 0x10200000
753 #define PCI_PHYS_ADDR 0x14005000
754 #define MAC0_PHYS_ADDR 0x10500000
755 #define MAC1_PHYS_ADDR 0x10510000
756 #define MACEN_PHYS_ADDR 0x10520000
757 #define MACDMA0_PHYS_ADDR 0x14004000
758 #define MACDMA1_PHYS_ADDR 0x14004200
759 #define UART0_PHYS_ADDR 0x11100000
760 #define UART1_PHYS_ADDR 0x11200000
761 #define UART3_PHYS_ADDR 0x11400000
762 #define GPIO2_PHYS_ADDR 0x11700000
763 #define SYS_PHYS_ADDR 0x11900000
764 #define DDMA_PHYS_ADDR 0x14002000
765 #define PE_PHYS_ADDR 0x14008000
766 #define PSC0_PHYS_ADDR 0x11A00000
767 #define PSC1_PHYS_ADDR 0x11B00000
768 #define PSC2_PHYS_ADDR 0x10A00000
769 #define PSC3_PHYS_ADDR 0x10B00000
770 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
771 #define PCI_IO_PHYS_ADDR 0x500000000ULL
772 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
773 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
774 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
775 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
776 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
779 /***********************************************************************/
781 #ifdef CONFIG_SOC_AU1200
782 #define MEM_PHYS_ADDR 0x14000000
783 #define STATIC_MEM_PHYS_ADDR 0x14001000
784 #define AES_PHYS_ADDR 0x10300000
785 #define CIM_PHYS_ADDR 0x14004000
786 #define USBM_PHYS_ADDR 0x14020000
787 #define USBH_PHYS_ADDR 0x14020100
788 #define UART0_PHYS_ADDR 0x11100000
789 #define UART1_PHYS_ADDR 0x11200000
790 #define GPIO2_PHYS_ADDR 0x11700000
791 #define SYS_PHYS_ADDR 0x11900000
792 #define DDMA_PHYS_ADDR 0x14002000
793 #define PSC0_PHYS_ADDR 0x11A00000
794 #define PSC1_PHYS_ADDR 0x11B00000
795 #define SD0_PHYS_ADDR 0x10600000
796 #define SD1_PHYS_ADDR 0x10680000
797 #define LCD_PHYS_ADDR 0x15000000
798 #define SWCNT_PHYS_ADDR 0x1110010C
799 #define MAEFE_PHYS_ADDR 0x14012000
800 #define MAEBE_PHYS_ADDR 0x14010000
801 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
802 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
803 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
806 /* Static Bus Controller */
807 #define MEM_STCFG0 0xB4001000
808 #define MEM_STTIME0 0xB4001004
809 #define MEM_STADDR0 0xB4001008
811 #define MEM_STCFG1 0xB4001010
812 #define MEM_STTIME1 0xB4001014
813 #define MEM_STADDR1 0xB4001018
815 #define MEM_STCFG2 0xB4001020
816 #define MEM_STTIME2 0xB4001024
817 #define MEM_STADDR2 0xB4001028
819 #define MEM_STCFG3 0xB4001030
820 #define MEM_STTIME3 0xB4001034
821 #define MEM_STADDR3 0xB4001038
823 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
824 #define MEM_STNDCTL 0xB4001100
825 #define MEM_STSTAT 0xB4001104
827 #define MEM_STNAND_CMD 0x0
828 #define MEM_STNAND_ADDR 0x4
829 #define MEM_STNAND_DATA 0x20
836 #ifdef CONFIG_SOC_AU1000
838 #define UART0_ADDR 0xB1100000
839 #define UART3_ADDR 0xB1400000
841 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
842 #define USB_HOST_CONFIG 0xB017FFFC
843 #define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
845 #define AU1000_ETH0_BASE 0xB0500000
846 #define AU1000_ETH1_BASE 0xB0510000
847 #define AU1000_MAC0_ENABLE 0xB0520000
848 #define AU1000_MAC1_ENABLE 0xB0520004
849 #define NUM_ETH_INTERFACES 2
850 #endif /* CONFIG_SOC_AU1000 */
853 #ifdef CONFIG_SOC_AU1500
855 #define UART0_ADDR 0xB1100000
856 #define UART3_ADDR 0xB1400000
858 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
859 #define USB_HOST_CONFIG 0xB017fffc
860 #define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
862 #define AU1500_ETH0_BASE 0xB1500000
863 #define AU1500_ETH1_BASE 0xB1510000
864 #define AU1500_MAC0_ENABLE 0xB1520000
865 #define AU1500_MAC1_ENABLE 0xB1520004
866 #define NUM_ETH_INTERFACES 2
867 #endif /* CONFIG_SOC_AU1500 */
870 #ifdef CONFIG_SOC_AU1100
872 #define UART0_ADDR 0xB1100000
873 #define UART3_ADDR 0xB1400000
875 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
876 #define USB_HOST_CONFIG 0xB017FFFC
877 #define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
879 #define AU1100_ETH0_BASE 0xB0500000
880 #define AU1100_MAC0_ENABLE 0xB0520000
881 #define NUM_ETH_INTERFACES 1
882 #endif /* CONFIG_SOC_AU1100 */
884 #ifdef CONFIG_SOC_AU1550
885 #define UART0_ADDR 0xB1100000
887 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
888 #define USB_OHCI_LEN 0x00060000
889 #define USB_HOST_CONFIG 0xB4027ffc
890 #define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
892 #define AU1550_ETH0_BASE 0xB0500000
893 #define AU1550_ETH1_BASE 0xB0510000
894 #define AU1550_MAC0_ENABLE 0xB0520000
895 #define AU1550_MAC1_ENABLE 0xB0520004
896 #define NUM_ETH_INTERFACES 2
897 #endif /* CONFIG_SOC_AU1550 */
900 #ifdef CONFIG_SOC_AU1200
902 #define UART0_ADDR 0xB1100000
904 #define USB_UOC_BASE 0x14020020
905 #define USB_UOC_LEN 0x20
906 #define USB_OHCI_BASE 0x14020100
907 #define USB_OHCI_LEN 0x100
908 #define USB_EHCI_BASE 0x14020200
909 #define USB_EHCI_LEN 0x100
910 #define USB_UDC_BASE 0x14022000
911 #define USB_UDC_LEN 0x2000
912 #define USB_MSR_BASE 0xB4020000
913 #define USB_MSR_MCFG 4
914 #define USBMSRMCFG_OMEMEN 0
915 #define USBMSRMCFG_OBMEN 1
916 #define USBMSRMCFG_EMEMEN 2
917 #define USBMSRMCFG_EBMEN 3
918 #define USBMSRMCFG_DMEMEN 4
919 #define USBMSRMCFG_DBMEN 5
920 #define USBMSRMCFG_GMEMEN 6
921 #define USBMSRMCFG_OHCCLKEN 16
922 #define USBMSRMCFG_EHCCLKEN 17
923 #define USBMSRMCFG_UDCCLKEN 18
924 #define USBMSRMCFG_PHYPLLEN 19
925 #define USBMSRMCFG_RDCOMB 30
926 #define USBMSRMCFG_PFEN 31
928 #define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
930 #endif /* CONFIG_SOC_AU1200 */
932 /* Programmable Counters 0 and 1 */
933 #define SYS_BASE 0xB1900000
934 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
935 # define SYS_CNTRL_E1S (1 << 23)
936 # define SYS_CNTRL_T1S (1 << 20)
937 # define SYS_CNTRL_M21 (1 << 19)
938 # define SYS_CNTRL_M11 (1 << 18)
939 # define SYS_CNTRL_M01 (1 << 17)
940 # define SYS_CNTRL_C1S (1 << 16)
941 # define SYS_CNTRL_BP (1 << 14)
942 # define SYS_CNTRL_EN1 (1 << 13)
943 # define SYS_CNTRL_BT1 (1 << 12)
944 # define SYS_CNTRL_EN0 (1 << 11)
945 # define SYS_CNTRL_BT0 (1 << 10)
946 # define SYS_CNTRL_E0 (1 << 8)
947 # define SYS_CNTRL_E0S (1 << 7)
948 # define SYS_CNTRL_32S (1 << 5)
949 # define SYS_CNTRL_T0S (1 << 4)
950 # define SYS_CNTRL_M20 (1 << 3)
951 # define SYS_CNTRL_M10 (1 << 2)
952 # define SYS_CNTRL_M00 (1 << 1)
953 # define SYS_CNTRL_C0S (1 << 0)
955 /* Programmable Counter 0 Registers */
956 #define SYS_TOYTRIM (SYS_BASE + 0)
957 #define SYS_TOYWRITE (SYS_BASE + 4)
958 #define SYS_TOYMATCH0 (SYS_BASE + 8)
959 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
960 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
961 #define SYS_TOYREAD (SYS_BASE + 0x40)
963 /* Programmable Counter 1 Registers */
964 #define SYS_RTCTRIM (SYS_BASE + 0x44)
965 #define SYS_RTCWRITE (SYS_BASE + 0x48)
966 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
967 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
968 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
969 #define SYS_RTCREAD (SYS_BASE + 0x58)
972 #define I2S_DATA 0xB1000000
973 # define I2S_DATA_MASK 0xffffff
974 #define I2S_CONFIG 0xB1000004
975 # define I2S_CONFIG_XU (1 << 25)
976 # define I2S_CONFIG_XO (1 << 24)
977 # define I2S_CONFIG_RU (1 << 23)
978 # define I2S_CONFIG_RO (1 << 22)
979 # define I2S_CONFIG_TR (1 << 21)
980 # define I2S_CONFIG_TE (1 << 20)
981 # define I2S_CONFIG_TF (1 << 19)
982 # define I2S_CONFIG_RR (1 << 18)
983 # define I2S_CONFIG_RE (1 << 17)
984 # define I2S_CONFIG_RF (1 << 16)
985 # define I2S_CONFIG_PD (1 << 11)
986 # define I2S_CONFIG_LB (1 << 10)
987 # define I2S_CONFIG_IC (1 << 9)
988 # define I2S_CONFIG_FM_BIT 7
989 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
990 # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
991 # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
992 # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
993 # define I2S_CONFIG_TN (1 << 6)
994 # define I2S_CONFIG_RN (1 << 5)
995 # define I2S_CONFIG_SZ_BIT 0
996 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
998 #define I2S_CONTROL 0xB1000008
999 # define I2S_CONTROL_D (1 << 1)
1000 # define I2S_CONTROL_CE (1 << 0)
1002 /* USB Host Controller */
1003 #ifndef USB_OHCI_LEN
1004 #define USB_OHCI_LEN 0x00100000
1007 #ifndef CONFIG_SOC_AU1200
1009 /* USB Device Controller */
1010 #define USBD_EP0RD 0xB0200000
1011 #define USBD_EP0WR 0xB0200004
1012 #define USBD_EP2WR 0xB0200008
1013 #define USBD_EP3WR 0xB020000C
1014 #define USBD_EP4RD 0xB0200010
1015 #define USBD_EP5RD 0xB0200014
1016 #define USBD_INTEN 0xB0200018
1017 #define USBD_INTSTAT 0xB020001C
1018 # define USBDEV_INT_SOF (1 << 12)
1019 # define USBDEV_INT_HF_BIT 6
1020 # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1021 # define USBDEV_INT_CMPLT_BIT 0
1022 # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1023 #define USBD_CONFIG 0xB0200020
1024 #define USBD_EP0CS 0xB0200024
1025 #define USBD_EP2CS 0xB0200028
1026 #define USBD_EP3CS 0xB020002C
1027 #define USBD_EP4CS 0xB0200030
1028 #define USBD_EP5CS 0xB0200034
1029 # define USBDEV_CS_SU (1 << 14)
1030 # define USBDEV_CS_NAK (1 << 13)
1031 # define USBDEV_CS_ACK (1 << 12)
1032 # define USBDEV_CS_BUSY (1 << 11)
1033 # define USBDEV_CS_TSIZE_BIT 1
1034 # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1035 # define USBDEV_CS_STALL (1 << 0)
1036 #define USBD_EP0RDSTAT 0xB0200040
1037 #define USBD_EP0WRSTAT 0xB0200044
1038 #define USBD_EP2WRSTAT 0xB0200048
1039 #define USBD_EP3WRSTAT 0xB020004C
1040 #define USBD_EP4RDSTAT 0xB0200050
1041 #define USBD_EP5RDSTAT 0xB0200054
1042 # define USBDEV_FSTAT_FLUSH (1 << 6)
1043 # define USBDEV_FSTAT_UF (1 << 5)
1044 # define USBDEV_FSTAT_OF (1 << 4)
1045 # define USBDEV_FSTAT_FCNT_BIT 0
1046 # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1047 #define USBD_ENABLE 0xB0200058
1048 # define USBDEV_ENABLE (1 << 1)
1049 # define USBDEV_CE (1 << 0)
1051 #endif /* !CONFIG_SOC_AU1200 */
1053 /* Ethernet Controllers */
1055 /* 4 byte offsets from AU1000_ETH_BASE */
1056 #define MAC_CONTROL 0x0
1057 # define MAC_RX_ENABLE (1 << 2)
1058 # define MAC_TX_ENABLE (1 << 3)
1059 # define MAC_DEF_CHECK (1 << 5)
1060 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
1061 # define MAC_AUTO_PAD (1 << 8)
1062 # define MAC_DISABLE_RETRY (1 << 10)
1063 # define MAC_DISABLE_BCAST (1 << 11)
1064 # define MAC_LATE_COL (1 << 12)
1065 # define MAC_HASH_MODE (1 << 13)
1066 # define MAC_HASH_ONLY (1 << 15)
1067 # define MAC_PASS_ALL (1 << 16)
1068 # define MAC_INVERSE_FILTER (1 << 17)
1069 # define MAC_PROMISCUOUS (1 << 18)
1070 # define MAC_PASS_ALL_MULTI (1 << 19)
1071 # define MAC_FULL_DUPLEX (1 << 20)
1072 # define MAC_NORMAL_MODE 0
1073 # define MAC_INT_LOOPBACK (1 << 21)
1074 # define MAC_EXT_LOOPBACK (1 << 22)
1075 # define MAC_DISABLE_RX_OWN (1 << 23)
1076 # define MAC_BIG_ENDIAN (1 << 30)
1077 # define MAC_RX_ALL (1 << 31)
1078 #define MAC_ADDRESS_HIGH 0x4
1079 #define MAC_ADDRESS_LOW 0x8
1080 #define MAC_MCAST_HIGH 0xC
1081 #define MAC_MCAST_LOW 0x10
1082 #define MAC_MII_CNTRL 0x14
1083 # define MAC_MII_BUSY (1 << 0)
1084 # define MAC_MII_READ 0
1085 # define MAC_MII_WRITE (1 << 1)
1086 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1087 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1088 #define MAC_MII_DATA 0x18
1089 #define MAC_FLOW_CNTRL 0x1C
1090 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
1091 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1092 # define MAC_PASS_CONTROL (1 << 2)
1093 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1094 #define MAC_VLAN1_TAG 0x20
1095 #define MAC_VLAN2_TAG 0x24
1097 /* Ethernet Controller Enable */
1099 # define MAC_EN_CLOCK_ENABLE (1 << 0)
1100 # define MAC_EN_RESET0 (1 << 1)
1101 # define MAC_EN_TOSS (0 << 2)
1102 # define MAC_EN_CACHEABLE (1 << 3)
1103 # define MAC_EN_RESET1 (1 << 4)
1104 # define MAC_EN_RESET2 (1 << 5)
1105 # define MAC_DMA_RESET (1 << 6)
1107 /* Ethernet Controller DMA Channels */
1109 #define MAC0_TX_DMA_ADDR 0xB4004000
1110 #define MAC1_TX_DMA_ADDR 0xB4004200
1111 /* offsets from MAC_TX_RING_ADDR address */
1112 #define MAC_TX_BUFF0_STATUS 0x0
1113 # define TX_FRAME_ABORTED (1 << 0)
1114 # define TX_JAB_TIMEOUT (1 << 1)
1115 # define TX_NO_CARRIER (1 << 2)
1116 # define TX_LOSS_CARRIER (1 << 3)
1117 # define TX_EXC_DEF (1 << 4)
1118 # define TX_LATE_COLL_ABORT (1 << 5)
1119 # define TX_EXC_COLL (1 << 6)
1120 # define TX_UNDERRUN (1 << 7)
1121 # define TX_DEFERRED (1 << 8)
1122 # define TX_LATE_COLL (1 << 9)
1123 # define TX_COLL_CNT_MASK (0xF << 10)
1124 # define TX_PKT_RETRY (1 << 31)
1125 #define MAC_TX_BUFF0_ADDR 0x4
1126 # define TX_DMA_ENABLE (1 << 0)
1127 # define TX_T_DONE (1 << 1)
1128 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1129 #define MAC_TX_BUFF0_LEN 0x8
1130 #define MAC_TX_BUFF1_STATUS 0x10
1131 #define MAC_TX_BUFF1_ADDR 0x14
1132 #define MAC_TX_BUFF1_LEN 0x18
1133 #define MAC_TX_BUFF2_STATUS 0x20
1134 #define MAC_TX_BUFF2_ADDR 0x24
1135 #define MAC_TX_BUFF2_LEN 0x28
1136 #define MAC_TX_BUFF3_STATUS 0x30
1137 #define MAC_TX_BUFF3_ADDR 0x34
1138 #define MAC_TX_BUFF3_LEN 0x38
1140 #define MAC0_RX_DMA_ADDR 0xB4004100
1141 #define MAC1_RX_DMA_ADDR 0xB4004300
1142 /* offsets from MAC_RX_RING_ADDR */
1143 #define MAC_RX_BUFF0_STATUS 0x0
1144 # define RX_FRAME_LEN_MASK 0x3fff
1145 # define RX_WDOG_TIMER (1 << 14)
1146 # define RX_RUNT (1 << 15)
1147 # define RX_OVERLEN (1 << 16)
1148 # define RX_COLL (1 << 17)
1149 # define RX_ETHER (1 << 18)
1150 # define RX_MII_ERROR (1 << 19)
1151 # define RX_DRIBBLING (1 << 20)
1152 # define RX_CRC_ERROR (1 << 21)
1153 # define RX_VLAN1 (1 << 22)
1154 # define RX_VLAN2 (1 << 23)
1155 # define RX_LEN_ERROR (1 << 24)
1156 # define RX_CNTRL_FRAME (1 << 25)
1157 # define RX_U_CNTRL_FRAME (1 << 26)
1158 # define RX_MCAST_FRAME (1 << 27)
1159 # define RX_BCAST_FRAME (1 << 28)
1160 # define RX_FILTER_FAIL (1 << 29)
1161 # define RX_PACKET_FILTER (1 << 30)
1162 # define RX_MISSED_FRAME (1 << 31)
1164 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1165 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1166 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1167 #define MAC_RX_BUFF0_ADDR 0x4
1168 # define RX_DMA_ENABLE (1 << 0)
1169 # define RX_T_DONE (1 << 1)
1170 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1171 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1172 #define MAC_RX_BUFF1_STATUS 0x10
1173 #define MAC_RX_BUFF1_ADDR 0x14
1174 #define MAC_RX_BUFF2_STATUS 0x20
1175 #define MAC_RX_BUFF2_ADDR 0x24
1176 #define MAC_RX_BUFF3_STATUS 0x30
1177 #define MAC_RX_BUFF3_ADDR 0x34
1179 #define UART_RX 0 /* Receive buffer */
1180 #define UART_TX 4 /* Transmit buffer */
1181 #define UART_IER 8 /* Interrupt Enable Register */
1182 #define UART_IIR 0xC /* Interrupt ID Register */
1183 #define UART_FCR 0x10 /* FIFO Control Register */
1184 #define UART_LCR 0x14 /* Line Control Register */
1185 #define UART_MCR 0x18 /* Modem Control Register */
1186 #define UART_LSR 0x1C /* Line Status Register */
1187 #define UART_MSR 0x20 /* Modem Status Register */
1188 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
1189 #define UART_MOD_CNTRL 0x100 /* Module Control */
1192 #define SSI0_STATUS 0xB1600000
1193 # define SSI_STATUS_BF (1 << 4)
1194 # define SSI_STATUS_OF (1 << 3)
1195 # define SSI_STATUS_UF (1 << 2)
1196 # define SSI_STATUS_D (1 << 1)
1197 # define SSI_STATUS_B (1 << 0)
1198 #define SSI0_INT 0xB1600004
1199 # define SSI_INT_OI (1 << 3)
1200 # define SSI_INT_UI (1 << 2)
1201 # define SSI_INT_DI (1 << 1)
1202 #define SSI0_INT_ENABLE 0xB1600008
1203 # define SSI_INTE_OIE (1 << 3)
1204 # define SSI_INTE_UIE (1 << 2)
1205 # define SSI_INTE_DIE (1 << 1)
1206 #define SSI0_CONFIG 0xB1600020
1207 # define SSI_CONFIG_AO (1 << 24)
1208 # define SSI_CONFIG_DO (1 << 23)
1209 # define SSI_CONFIG_ALEN_BIT 20
1210 # define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1211 # define SSI_CONFIG_DLEN_BIT 16
1212 # define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1213 # define SSI_CONFIG_DD (1 << 11)
1214 # define SSI_CONFIG_AD (1 << 10)
1215 # define SSI_CONFIG_BM_BIT 8
1216 # define SSI_CONFIG_BM_MASK (0x3 << 8)
1217 # define SSI_CONFIG_CE (1 << 7)
1218 # define SSI_CONFIG_DP (1 << 6)
1219 # define SSI_CONFIG_DL (1 << 5)
1220 # define SSI_CONFIG_EP (1 << 4)
1221 #define SSI0_ADATA 0xB1600024
1222 # define SSI_AD_D (1 << 24)
1223 # define SSI_AD_ADDR_BIT 16
1224 # define SSI_AD_ADDR_MASK (0xff << 16)
1225 # define SSI_AD_DATA_BIT 0
1226 # define SSI_AD_DATA_MASK (0xfff << 0)
1227 #define SSI0_CLKDIV 0xB1600028
1228 #define SSI0_CONTROL 0xB1600100
1229 # define SSI_CONTROL_CD (1 << 1)
1230 # define SSI_CONTROL_E (1 << 0)
1233 #define SSI1_STATUS 0xB1680000
1234 #define SSI1_INT 0xB1680004
1235 #define SSI1_INT_ENABLE 0xB1680008
1236 #define SSI1_CONFIG 0xB1680020
1237 #define SSI1_ADATA 0xB1680024
1238 #define SSI1_CLKDIV 0xB1680028
1239 #define SSI1_ENABLE 0xB1680100
1242 * Register content definitions
1244 #define SSI_STATUS_BF (1 << 4)
1245 #define SSI_STATUS_OF (1 << 3)
1246 #define SSI_STATUS_UF (1 << 2)
1247 #define SSI_STATUS_D (1 << 1)
1248 #define SSI_STATUS_B (1 << 0)
1251 #define SSI_INT_OI (1 << 3)
1252 #define SSI_INT_UI (1 << 2)
1253 #define SSI_INT_DI (1 << 1)
1256 #define SSI_INTEN_OIE (1 << 3)
1257 #define SSI_INTEN_UIE (1 << 2)
1258 #define SSI_INTEN_DIE (1 << 1)
1260 #define SSI_CONFIG_AO (1 << 24)
1261 #define SSI_CONFIG_DO (1 << 23)
1262 #define SSI_CONFIG_ALEN (7 << 20)
1263 #define SSI_CONFIG_DLEN (15 << 16)
1264 #define SSI_CONFIG_DD (1 << 11)
1265 #define SSI_CONFIG_AD (1 << 10)
1266 #define SSI_CONFIG_BM (3 << 8)
1267 #define SSI_CONFIG_CE (1 << 7)
1268 #define SSI_CONFIG_DP (1 << 6)
1269 #define SSI_CONFIG_DL (1 << 5)
1270 #define SSI_CONFIG_EP (1 << 4)
1271 #define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1272 #define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1273 #define SSI_CONFIG_BM_HI (0 << 8)
1274 #define SSI_CONFIG_BM_LO (1 << 8)
1275 #define SSI_CONFIG_BM_CY (2 << 8)
1277 #define SSI_ADATA_D (1 << 24)
1278 #define SSI_ADATA_ADDR (0xFF << 16)
1279 #define SSI_ADATA_DATA 0x0FFF
1280 #define SSI_ADATA_ADDR_N(N) (N << 16)
1282 #define SSI_ENABLE_CD (1 << 1)
1283 #define SSI_ENABLE_E (1 << 0)
1285 /* IrDA Controller */
1286 #define IRDA_BASE 0xB0300000
1287 #define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1288 #define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1289 #define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1290 #define IR_RING_SIZE (IRDA_BASE + 0x0C)
1291 #define IR_RING_PROMPT (IRDA_BASE + 0x10)
1292 #define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1293 #define IR_INT_CLEAR (IRDA_BASE + 0x18)
1294 #define IR_CONFIG_1 (IRDA_BASE + 0x20)
1295 # define IR_RX_INVERT_LED (1 << 0)
1296 # define IR_TX_INVERT_LED (1 << 1)
1297 # define IR_ST (1 << 2)
1298 # define IR_SF (1 << 3)
1299 # define IR_SIR (1 << 4)
1300 # define IR_MIR (1 << 5)
1301 # define IR_FIR (1 << 6)
1302 # define IR_16CRC (1 << 7)
1303 # define IR_TD (1 << 8)
1304 # define IR_RX_ALL (1 << 9)
1305 # define IR_DMA_ENABLE (1 << 10)
1306 # define IR_RX_ENABLE (1 << 11)
1307 # define IR_TX_ENABLE (1 << 12)
1308 # define IR_LOOPBACK (1 << 14)
1309 # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1310 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1311 #define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1312 #define IR_ENABLE (IRDA_BASE + 0x28)
1313 # define IR_RX_STATUS (1 << 9)
1314 # define IR_TX_STATUS (1 << 10)
1315 #define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1316 #define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1317 #define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1318 #define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1319 #define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1320 # define IR_MODE_INV (1 << 0)
1321 # define IR_ONE_PIN (1 << 1)
1322 #define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1325 #define SYS_PINFUNC 0xB190002C
1326 # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1327 # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1328 # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1329 # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1330 # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1331 # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1332 # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1333 # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1334 # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1335 # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1336 # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1337 # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1338 # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1339 # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1340 # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1341 # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1344 # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1345 # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1346 # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1347 # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1349 /* Au1550 only. Redefines lots of pins */
1350 # define SYS_PF_PSC2_MASK (7 << 17)
1351 # define SYS_PF_PSC2_AC97 0
1352 # define SYS_PF_PSC2_SPI 0
1353 # define SYS_PF_PSC2_I2S (1 << 17)
1354 # define SYS_PF_PSC2_SMBUS (3 << 17)
1355 # define SYS_PF_PSC2_GPIO (7 << 17)
1356 # define SYS_PF_PSC3_MASK (7 << 20)
1357 # define SYS_PF_PSC3_AC97 0
1358 # define SYS_PF_PSC3_SPI 0
1359 # define SYS_PF_PSC3_I2S (1 << 20)
1360 # define SYS_PF_PSC3_SMBUS (3 << 20)
1361 # define SYS_PF_PSC3_GPIO (7 << 20)
1362 # define SYS_PF_PSC1_S1 (1 << 1)
1363 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1366 #ifdef CONFIG_SOC_AU1200
1367 #define SYS_PINFUNC_DMA (1 << 31)
1368 #define SYS_PINFUNC_S0A (1 << 30)
1369 #define SYS_PINFUNC_S1A (1 << 29)
1370 #define SYS_PINFUNC_LP0 (1 << 28)
1371 #define SYS_PINFUNC_LP1 (1 << 27)
1372 #define SYS_PINFUNC_LD16 (1 << 26)
1373 #define SYS_PINFUNC_LD8 (1 << 25)
1374 #define SYS_PINFUNC_LD1 (1 << 24)
1375 #define SYS_PINFUNC_LD0 (1 << 23)
1376 #define SYS_PINFUNC_P1A (3 << 21)
1377 #define SYS_PINFUNC_P1B (1 << 20)
1378 #define SYS_PINFUNC_FS3 (1 << 19)
1379 #define SYS_PINFUNC_P0A (3 << 17)
1380 #define SYS_PINFUNC_CS (1 << 16)
1381 #define SYS_PINFUNC_CIM (1 << 15)
1382 #define SYS_PINFUNC_P1C (1 << 14)
1383 #define SYS_PINFUNC_U1T (1 << 12)
1384 #define SYS_PINFUNC_U1R (1 << 11)
1385 #define SYS_PINFUNC_EX1 (1 << 10)
1386 #define SYS_PINFUNC_EX0 (1 << 9)
1387 #define SYS_PINFUNC_U0R (1 << 8)
1388 #define SYS_PINFUNC_MC (1 << 7)
1389 #define SYS_PINFUNC_S0B (1 << 6)
1390 #define SYS_PINFUNC_S0C (1 << 5)
1391 #define SYS_PINFUNC_P0B (1 << 4)
1392 #define SYS_PINFUNC_U0T (1 << 3)
1393 #define SYS_PINFUNC_S1B (1 << 2)
1396 #define SYS_TRIOUTRD 0xB1900100
1397 #define SYS_TRIOUTCLR 0xB1900100
1398 #define SYS_OUTPUTRD 0xB1900108
1399 #define SYS_OUTPUTSET 0xB1900108
1400 #define SYS_OUTPUTCLR 0xB190010C
1401 #define SYS_PINSTATERD 0xB1900110
1402 #define SYS_PININPUTEN 0xB1900110
1404 /* GPIO2, Au1500, Au1550 only */
1405 #define GPIO2_BASE 0xB1700000
1406 #define GPIO2_DIR (GPIO2_BASE + 0)
1407 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
1408 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1409 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1410 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1412 /* Power Management */
1413 #define SYS_SCRATCH0 0xB1900018
1414 #define SYS_SCRATCH1 0xB190001C
1415 #define SYS_WAKEMSK 0xB1900034
1416 #define SYS_ENDIAN 0xB1900038
1417 #define SYS_POWERCTRL 0xB190003C
1418 #define SYS_WAKESRC 0xB190005C
1419 #define SYS_SLPPWR 0xB1900078
1420 #define SYS_SLEEP 0xB190007C
1422 #define SYS_WAKEMSK_D2 (1 << 9)
1423 #define SYS_WAKEMSK_M2 (1 << 8)
1424 #define SYS_WAKEMSK_GPIO(x) (1 << (x))
1426 /* Clock Controller */
1427 #define SYS_FREQCTRL0 0xB1900020
1428 # define SYS_FC_FRDIV2_BIT 22
1429 # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1430 # define SYS_FC_FE2 (1 << 21)
1431 # define SYS_FC_FS2 (1 << 20)
1432 # define SYS_FC_FRDIV1_BIT 12
1433 # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1434 # define SYS_FC_FE1 (1 << 11)
1435 # define SYS_FC_FS1 (1 << 10)
1436 # define SYS_FC_FRDIV0_BIT 2
1437 # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1438 # define SYS_FC_FE0 (1 << 1)
1439 # define SYS_FC_FS0 (1 << 0)
1440 #define SYS_FREQCTRL1 0xB1900024
1441 # define SYS_FC_FRDIV5_BIT 22
1442 # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1443 # define SYS_FC_FE5 (1 << 21)
1444 # define SYS_FC_FS5 (1 << 20)
1445 # define SYS_FC_FRDIV4_BIT 12
1446 # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1447 # define SYS_FC_FE4 (1 << 11)
1448 # define SYS_FC_FS4 (1 << 10)
1449 # define SYS_FC_FRDIV3_BIT 2
1450 # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1451 # define SYS_FC_FE3 (1 << 1)
1452 # define SYS_FC_FS3 (1 << 0)
1453 #define SYS_CLKSRC 0xB1900028
1454 # define SYS_CS_ME1_BIT 27
1455 # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1456 # define SYS_CS_DE1 (1 << 26)
1457 # define SYS_CS_CE1 (1 << 25)
1458 # define SYS_CS_ME0_BIT 22
1459 # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1460 # define SYS_CS_DE0 (1 << 21)
1461 # define SYS_CS_CE0 (1 << 20)
1462 # define SYS_CS_MI2_BIT 17
1463 # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1464 # define SYS_CS_DI2 (1 << 16)
1465 # define SYS_CS_CI2 (1 << 15)
1466 #ifdef CONFIG_SOC_AU1100
1467 # define SYS_CS_ML_BIT 7
1468 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1469 # define SYS_CS_DL (1 << 6)
1470 # define SYS_CS_CL (1 << 5)
1472 # define SYS_CS_MUH_BIT 12
1473 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1474 # define SYS_CS_DUH (1 << 11)
1475 # define SYS_CS_CUH (1 << 10)
1476 # define SYS_CS_MUD_BIT 7
1477 # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1478 # define SYS_CS_DUD (1 << 6)
1479 # define SYS_CS_CUD (1 << 5)
1481 # define SYS_CS_MIR_BIT 2
1482 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1483 # define SYS_CS_DIR (1 << 1)
1484 # define SYS_CS_CIR (1 << 0)
1486 # define SYS_CS_MUX_AUX 0x1
1487 # define SYS_CS_MUX_FQ0 0x2
1488 # define SYS_CS_MUX_FQ1 0x3
1489 # define SYS_CS_MUX_FQ2 0x4
1490 # define SYS_CS_MUX_FQ3 0x5
1491 # define SYS_CS_MUX_FQ4 0x6
1492 # define SYS_CS_MUX_FQ5 0x7
1493 #define SYS_CPUPLL 0xB1900060
1494 #define SYS_AUXPLL 0xB1900064
1496 /* AC97 Controller */
1497 #define AC97C_CONFIG 0xB0000000
1498 # define AC97C_RECV_SLOTS_BIT 13
1499 # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1500 # define AC97C_XMIT_SLOTS_BIT 3
1501 # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1502 # define AC97C_SG (1 << 2)
1503 # define AC97C_SYNC (1 << 1)
1504 # define AC97C_RESET (1 << 0)
1505 #define AC97C_STATUS 0xB0000004
1506 # define AC97C_XU (1 << 11)
1507 # define AC97C_XO (1 << 10)
1508 # define AC97C_RU (1 << 9)
1509 # define AC97C_RO (1 << 8)
1510 # define AC97C_READY (1 << 7)
1511 # define AC97C_CP (1 << 6)
1512 # define AC97C_TR (1 << 5)
1513 # define AC97C_TE (1 << 4)
1514 # define AC97C_TF (1 << 3)
1515 # define AC97C_RR (1 << 2)
1516 # define AC97C_RE (1 << 1)
1517 # define AC97C_RF (1 << 0)
1518 #define AC97C_DATA 0xB0000008
1519 #define AC97C_CMD 0xB000000C
1520 # define AC97C_WD_BIT 16
1521 # define AC97C_READ (1 << 7)
1522 # define AC97C_INDEX_MASK 0x7f
1523 #define AC97C_CNTRL 0xB0000010
1524 # define AC97C_RS (1 << 1)
1525 # define AC97C_CE (1 << 0)
1527 /* Secure Digital (SD) Controller */
1528 #define SD0_XMIT_FIFO 0xB0600000
1529 #define SD0_RECV_FIFO 0xB0600004
1530 #define SD1_XMIT_FIFO 0xB0680000
1531 #define SD1_RECV_FIFO 0xB0680004
1533 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1534 /* Au1500 PCI Controller */
1535 #define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1536 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1537 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1538 # define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1539 (1 << 25) | (1 << 26) | (1 << 27))
1540 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1541 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1542 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1543 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1544 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1545 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1546 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1547 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1548 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1549 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1550 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1551 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1553 #define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1556 * All of our structures, like PCI resource, have 32-bit members.
1557 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1558 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1559 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1560 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1561 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1562 * ourselves and then adjust the device's resources.
1564 #define Au1500_EXT_CFG 0x600000000ULL
1565 #define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1566 #define Au1500_PCI_IO_START 0x500000000ULL
1567 #define Au1500_PCI_IO_END 0x5000FFFFFULL
1568 #define Au1500_PCI_MEM_START 0x440000000ULL
1569 #define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1571 #define PCI_IO_START 0x00001000
1572 #define PCI_IO_END 0x000FFFFF
1573 #define PCI_MEM_START 0x40000000
1574 #define PCI_MEM_END 0x4FFFFFFF
1576 #define PCI_FIRST_DEVFN (0 << 3)
1577 #define PCI_LAST_DEVFN (19 << 3)
1579 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1580 #define IOPORT_RESOURCE_END 0xffffffff
1581 #define IOMEM_RESOURCE_START 0x10000000
1582 #define IOMEM_RESOURCE_END 0xfffffffffULL
1584 #else /* Au1000 and Au1100 and Au1200 */
1586 /* Don't allow any legacy ports probing */
1587 #define IOPORT_RESOURCE_START 0x10000000
1588 #define IOPORT_RESOURCE_END 0xffffffff
1589 #define IOMEM_RESOURCE_START 0x10000000
1590 #define IOMEM_RESOURCE_END 0xfffffffffULL
1592 #define PCI_IO_START 0
1593 #define PCI_IO_END 0
1594 #define PCI_MEM_START 0
1595 #define PCI_MEM_END 0
1596 #define PCI_FIRST_DEVFN 0
1597 #define PCI_LAST_DEVFN 0