2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
12 #ifdef CONFIG_SOC_TYPE_XWAY
17 #define SOC_ID_DANUBE1 0x129
18 #define SOC_ID_DANUBE2 0x12B
19 #define SOC_ID_TWINPASS 0x12D
20 #define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */
21 #define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */
22 #define SOC_ID_ARX188 0x16C
23 #define SOC_ID_ARX168_1 0x16D
24 #define SOC_ID_ARX168_2 0x16E
25 #define SOC_ID_ARX182 0x16F
26 #define SOC_ID_GRX188 0x170
27 #define SOC_ID_GRX168 0x171
29 #define SOC_ID_VRX288 0x1C0 /* v1.1 */
30 #define SOC_ID_VRX282 0x1C1 /* v1.1 */
31 #define SOC_ID_VRX268 0x1C2 /* v1.1 */
32 #define SOC_ID_GRX268 0x1C8 /* v1.1 */
33 #define SOC_ID_GRX288 0x1C9 /* v1.1 */
34 #define SOC_ID_VRX288_2 0x00B /* v1.2 */
35 #define SOC_ID_VRX268_2 0x00C /* v1.2 */
36 #define SOC_ID_GRX288_2 0x00D /* v1.2 */
37 #define SOC_ID_GRX282_2 0x00E /* v1.2 */
40 #define SOC_TYPE_DANUBE 0x01
41 #define SOC_TYPE_TWINPASS 0x02
42 #define SOC_TYPE_AR9 0x03
43 #define SOC_TYPE_VR9 0x04 /* v1.1 */
44 #define SOC_TYPE_VR9_2 0x05 /* v1.2 */
45 #define SOC_TYPE_AMAZON_SE 0x06
47 /* ASC0/1 - serial port */
48 #define LTQ_ASC0_BASE_ADDR 0x1E100400
49 #define LTQ_ASC1_BASE_ADDR 0x1E100C00
50 #define LTQ_ASC_SIZE 0x400
52 /* BOOT_SEL - find what boot media we have */
53 #define BS_EXT_ROM 0x0
62 /* helpers used to access the cgu */
63 #define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
64 #define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
65 extern __iomem void *ltq_cgu_membase;
68 * during early_printk no ioremap is possible
69 * lets use KSEG1 instead
71 #define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
73 /* RCU - reset control unit */
74 #define LTQ_RCU_BASE_ADDR 0x1F203000
75 #define LTQ_RCU_SIZE 0x1000
77 /* GPTU - general purpose timer unit */
78 #define LTQ_GPTU_BASE_ADDR 0x18000300
79 #define LTQ_GPTU_SIZE 0x100
81 /* EBU - external bus unit */
82 #define LTQ_EBU_GPIO_START 0x14000000
83 #define LTQ_EBU_GPIO_SIZE 0x1000
85 #define LTQ_EBU_BASE_ADDR 0x1E105300
86 #define LTQ_EBU_SIZE 0x100
88 #define LTQ_EBU_BUSCON0 0x0060
89 #define LTQ_EBU_PCC_CON 0x0090
90 #define LTQ_EBU_PCC_IEN 0x00A4
91 #define LTQ_EBU_PCC_ISTAT 0x00A0
92 #define LTQ_EBU_BUSCON1 0x0064
93 #define LTQ_EBU_ADDRSEL1 0x0024
94 #define EBU_WRDIS 0x80000000
96 /* CGU - clock generation unit */
97 #define LTQ_CGU_BASE_ADDR 0x1F103000
98 #define LTQ_CGU_SIZE 0x1000
100 /* ICU - interrupt control unit */
101 #define LTQ_ICU_BASE_ADDR 0x1F880200
102 #define LTQ_ICU_SIZE 0x100
104 /* EIU - external interrupt unit */
105 #define LTQ_EIU_BASE_ADDR 0x1F101000
106 #define LTQ_EIU_SIZE 0x1000
108 /* PMU - power management unit */
109 #define LTQ_PMU_BASE_ADDR 0x1F102000
110 #define LTQ_PMU_SIZE 0x1000
112 #define PMU_DMA 0x0020
113 #define PMU_USB 0x8041
114 #define PMU_LED 0x0800
115 #define PMU_GPT 0x1000
116 #define PMU_PPE 0x2000
117 #define PMU_FPI 0x4000
118 #define PMU_SWITCH 0x10000000
120 /* ETOP - ethernet */
121 #define LTQ_ETOP_BASE_ADDR 0x1E180000
122 #define LTQ_ETOP_SIZE 0x40000
125 #define LTQ_DMA_BASE_ADDR 0x1E104100
126 #define LTQ_DMA_SIZE 0x800
129 #define PCI_CR_BASE_ADDR 0x1E105400
130 #define PCI_CR_SIZE 0x400
133 #define LTQ_WDT_BASE_ADDR 0x1F8803F0
134 #define LTQ_WDT_SIZE 0x10
136 #define LTQ_RST_CAUSE_WDTRST 0x20
138 /* STP - serial to parallel conversion unit */
139 #define LTQ_STP_BASE_ADDR 0x1E100BB0
140 #define LTQ_STP_SIZE 0x40
143 #define LTQ_GPIO0_BASE_ADDR 0x1E100B10
144 #define LTQ_GPIO1_BASE_ADDR 0x1E100B40
145 #define LTQ_GPIO2_BASE_ADDR 0x1E100B70
146 #define LTQ_GPIO_SIZE 0x30
149 #define LTQ_SSC_BASE_ADDR 0x1e100800
150 #define LTQ_SSC_SIZE 0x100
153 #define LTQ_MEI_BASE_ADDR 0x1E116000
155 /* DEU - data encryption unit */
156 #define LTQ_DEU_BASE_ADDR 0x1E103100
158 /* MPS - multi processor unit (voice) */
159 #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
160 #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
162 /* request a non-gpio and set the PIO config */
163 extern void ltq_pmu_enable(unsigned int module);
164 extern void ltq_pmu_disable(unsigned int module);
166 static inline int ltq_is_ar9(void)
168 return (ltq_get_soc_type() == SOC_TYPE_AR9);
171 static inline int ltq_is_vr9(void)
173 return (ltq_get_soc_type() == SOC_TYPE_VR9);
176 #endif /* CONFIG_SOC_TYPE_XWAY */
177 #endif /* _LTQ_XWAY_H__ */