2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
16 #include <linux/linkage.h>
17 #include <linux/types.h>
18 #include <asm/hazards.h>
22 * The following macros are especially useful for __asm__
29 #define STR(x) __STR(x)
38 #define _ULCAST_ (unsigned long)
42 * Coprocessor 0 register names
46 #define CP0_ENTRYLO0 $2
47 #define CP0_ENTRYLO1 $3
49 #define CP0_CONTEXT $4
50 #define CP0_PAGEMASK $5
53 #define CP0_BADVADDR $8
55 #define CP0_ENTRYHI $10
56 #define CP0_COMPARE $11
57 #define CP0_STATUS $12
61 #define CP0_CONFIG $16
62 #define CP0_LLADDR $17
63 #define CP0_WATCHLO $18
64 #define CP0_WATCHHI $19
65 #define CP0_XCONTEXT $20
66 #define CP0_FRAMEMASK $21
67 #define CP0_DIAGNOSTIC $22
70 #define CP0_PERFORMANCE $25
72 #define CP0_CACHEERR $27
75 #define CP0_ERROREPC $30
76 #define CP0_DESAVE $31
79 * R4640/R4650 cp0 register names. These registers are listed
80 * here only for completeness; without MMU these CPUs are not useable
81 * by Linux. A future ELKS port might take make Linux run on them
89 #define CP0_IWATCH $18
90 #define CP0_DWATCH $19
93 * Coprocessor 0 Set 1 register names
95 #define CP0_S1_DERRADDR0 $26
96 #define CP0_S1_DERRADDR1 $27
97 #define CP0_S1_INTCONTROL $20
100 * Coprocessor 0 Set 2 register names
102 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
105 * Coprocessor 0 Set 3 register names
107 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
112 #define CP0_TX39_CACHE $7
115 * Coprocessor 1 (FPU) register names
117 #define CP1_REVISION $0
118 #define CP1_STATUS $31
121 * FPU Status Register Values
124 * Status Register Values
127 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
128 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
129 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
130 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
131 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
132 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
133 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
134 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
135 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
136 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
139 * Bits 18 - 20 of the FPU Status Register will be read as 0,
140 * and should be written as zero.
142 #define FPU_CSR_RSVD 0x001c0000
145 * X the exception cause indicator
146 * E the exception enable
147 * S the sticky/flag bit
149 #define FPU_CSR_ALL_X 0x0003f000
150 #define FPU_CSR_UNI_X 0x00020000
151 #define FPU_CSR_INV_X 0x00010000
152 #define FPU_CSR_DIV_X 0x00008000
153 #define FPU_CSR_OVF_X 0x00004000
154 #define FPU_CSR_UDF_X 0x00002000
155 #define FPU_CSR_INE_X 0x00001000
157 #define FPU_CSR_ALL_E 0x00000f80
158 #define FPU_CSR_INV_E 0x00000800
159 #define FPU_CSR_DIV_E 0x00000400
160 #define FPU_CSR_OVF_E 0x00000200
161 #define FPU_CSR_UDF_E 0x00000100
162 #define FPU_CSR_INE_E 0x00000080
164 #define FPU_CSR_ALL_S 0x0000007c
165 #define FPU_CSR_INV_S 0x00000040
166 #define FPU_CSR_DIV_S 0x00000020
167 #define FPU_CSR_OVF_S 0x00000010
168 #define FPU_CSR_UDF_S 0x00000008
169 #define FPU_CSR_INE_S 0x00000004
171 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
172 #define FPU_CSR_RM 0x00000003
173 #define FPU_CSR_RN 0x0 /* nearest */
174 #define FPU_CSR_RZ 0x1 /* towards zero */
175 #define FPU_CSR_RU 0x2 /* towards +Infinity */
176 #define FPU_CSR_RD 0x3 /* towards -Infinity */
180 * Values for PageMask register
182 #ifdef CONFIG_CPU_VR41XX
184 /* Why doesn't stupidity hurt ... */
186 #define PM_1K 0x00000000
187 #define PM_4K 0x00001800
188 #define PM_16K 0x00007800
189 #define PM_64K 0x0001f800
190 #define PM_256K 0x0007f800
194 #define PM_4K 0x00000000
195 #define PM_8K 0x00002000
196 #define PM_16K 0x00006000
197 #define PM_32K 0x0000e000
198 #define PM_64K 0x0001e000
199 #define PM_128K 0x0003e000
200 #define PM_256K 0x0007e000
201 #define PM_512K 0x000fe000
202 #define PM_1M 0x001fe000
203 #define PM_2M 0x003fe000
204 #define PM_4M 0x007fe000
205 #define PM_8M 0x00ffe000
206 #define PM_16M 0x01ffe000
207 #define PM_32M 0x03ffe000
208 #define PM_64M 0x07ffe000
209 #define PM_256M 0x1fffe000
210 #define PM_1G 0x7fffe000
215 * Default page size for a given kernel configuration
217 #ifdef CONFIG_PAGE_SIZE_4KB
218 #define PM_DEFAULT_MASK PM_4K
219 #elif defined(CONFIG_PAGE_SIZE_8KB)
220 #define PM_DEFAULT_MASK PM_8K
221 #elif defined(CONFIG_PAGE_SIZE_16KB)
222 #define PM_DEFAULT_MASK PM_16K
223 #elif defined(CONFIG_PAGE_SIZE_32KB)
224 #define PM_DEFAULT_MASK PM_32K
225 #elif defined(CONFIG_PAGE_SIZE_64KB)
226 #define PM_DEFAULT_MASK PM_64K
228 #error Bad page size configuration!
232 * Default huge tlb size for a given kernel configuration
234 #ifdef CONFIG_PAGE_SIZE_4KB
235 #define PM_HUGE_MASK PM_1M
236 #elif defined(CONFIG_PAGE_SIZE_8KB)
237 #define PM_HUGE_MASK PM_4M
238 #elif defined(CONFIG_PAGE_SIZE_16KB)
239 #define PM_HUGE_MASK PM_16M
240 #elif defined(CONFIG_PAGE_SIZE_32KB)
241 #define PM_HUGE_MASK PM_64M
242 #elif defined(CONFIG_PAGE_SIZE_64KB)
243 #define PM_HUGE_MASK PM_256M
244 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
245 #error Bad page size configuration for hugetlbfs!
249 * Values used for computation of new tlb entries
264 #define PG_RIE (_ULCAST_(1) << 31)
265 #define PG_XIE (_ULCAST_(1) << 30)
266 #define PG_ELPA (_ULCAST_(1) << 29)
267 #define PG_ESP (_ULCAST_(1) << 28)
268 #define PG_IEC (_ULCAST_(1) << 27)
271 * R4x00 interrupt enable / cause bits
273 #define IE_SW0 (_ULCAST_(1) << 8)
274 #define IE_SW1 (_ULCAST_(1) << 9)
275 #define IE_IRQ0 (_ULCAST_(1) << 10)
276 #define IE_IRQ1 (_ULCAST_(1) << 11)
277 #define IE_IRQ2 (_ULCAST_(1) << 12)
278 #define IE_IRQ3 (_ULCAST_(1) << 13)
279 #define IE_IRQ4 (_ULCAST_(1) << 14)
280 #define IE_IRQ5 (_ULCAST_(1) << 15)
283 * R4x00 interrupt cause bits
285 #define C_SW0 (_ULCAST_(1) << 8)
286 #define C_SW1 (_ULCAST_(1) << 9)
287 #define C_IRQ0 (_ULCAST_(1) << 10)
288 #define C_IRQ1 (_ULCAST_(1) << 11)
289 #define C_IRQ2 (_ULCAST_(1) << 12)
290 #define C_IRQ3 (_ULCAST_(1) << 13)
291 #define C_IRQ4 (_ULCAST_(1) << 14)
292 #define C_IRQ5 (_ULCAST_(1) << 15)
295 * Bitfields in the R4xx0 cp0 status register
297 #define ST0_IE 0x00000001
298 #define ST0_EXL 0x00000002
299 #define ST0_ERL 0x00000004
300 #define ST0_KSU 0x00000018
301 # define KSU_USER 0x00000010
302 # define KSU_SUPERVISOR 0x00000008
303 # define KSU_KERNEL 0x00000000
304 #define ST0_UX 0x00000020
305 #define ST0_SX 0x00000040
306 #define ST0_KX 0x00000080
307 #define ST0_DE 0x00010000
308 #define ST0_CE 0x00020000
311 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
312 * cacheops in userspace. This bit exists only on RM7000 and RM9000
315 #define ST0_CO 0x08000000
318 * Bitfields in the R[23]000 cp0 status register.
320 #define ST0_IEC 0x00000001
321 #define ST0_KUC 0x00000002
322 #define ST0_IEP 0x00000004
323 #define ST0_KUP 0x00000008
324 #define ST0_IEO 0x00000010
325 #define ST0_KUO 0x00000020
326 /* bits 6 & 7 are reserved on R[23]000 */
327 #define ST0_ISC 0x00010000
328 #define ST0_SWC 0x00020000
329 #define ST0_CM 0x00080000
332 * Bits specific to the R4640/R4650
334 #define ST0_UM (_ULCAST_(1) << 4)
335 #define ST0_IL (_ULCAST_(1) << 23)
336 #define ST0_DL (_ULCAST_(1) << 24)
339 * Enable the MIPS MDMX and DSP ASEs
341 #define ST0_MX 0x01000000
344 * Bitfields in the TX39 family CP0 Configuration Register 3
346 #define TX39_CONF_ICS_SHIFT 19
347 #define TX39_CONF_ICS_MASK 0x00380000
348 #define TX39_CONF_ICS_1KB 0x00000000
349 #define TX39_CONF_ICS_2KB 0x00080000
350 #define TX39_CONF_ICS_4KB 0x00100000
351 #define TX39_CONF_ICS_8KB 0x00180000
352 #define TX39_CONF_ICS_16KB 0x00200000
354 #define TX39_CONF_DCS_SHIFT 16
355 #define TX39_CONF_DCS_MASK 0x00070000
356 #define TX39_CONF_DCS_1KB 0x00000000
357 #define TX39_CONF_DCS_2KB 0x00010000
358 #define TX39_CONF_DCS_4KB 0x00020000
359 #define TX39_CONF_DCS_8KB 0x00030000
360 #define TX39_CONF_DCS_16KB 0x00040000
362 #define TX39_CONF_CWFON 0x00004000
363 #define TX39_CONF_WBON 0x00002000
364 #define TX39_CONF_RF_SHIFT 10
365 #define TX39_CONF_RF_MASK 0x00000c00
366 #define TX39_CONF_DOZE 0x00000200
367 #define TX39_CONF_HALT 0x00000100
368 #define TX39_CONF_LOCK 0x00000080
369 #define TX39_CONF_ICE 0x00000020
370 #define TX39_CONF_DCE 0x00000010
371 #define TX39_CONF_IRSIZE_SHIFT 2
372 #define TX39_CONF_IRSIZE_MASK 0x0000000c
373 #define TX39_CONF_DRSIZE_SHIFT 0
374 #define TX39_CONF_DRSIZE_MASK 0x00000003
377 * Status register bits available in all MIPS CPUs.
379 #define ST0_IM 0x0000ff00
380 #define STATUSB_IP0 8
381 #define STATUSF_IP0 (_ULCAST_(1) << 8)
382 #define STATUSB_IP1 9
383 #define STATUSF_IP1 (_ULCAST_(1) << 9)
384 #define STATUSB_IP2 10
385 #define STATUSF_IP2 (_ULCAST_(1) << 10)
386 #define STATUSB_IP3 11
387 #define STATUSF_IP3 (_ULCAST_(1) << 11)
388 #define STATUSB_IP4 12
389 #define STATUSF_IP4 (_ULCAST_(1) << 12)
390 #define STATUSB_IP5 13
391 #define STATUSF_IP5 (_ULCAST_(1) << 13)
392 #define STATUSB_IP6 14
393 #define STATUSF_IP6 (_ULCAST_(1) << 14)
394 #define STATUSB_IP7 15
395 #define STATUSF_IP7 (_ULCAST_(1) << 15)
396 #define STATUSB_IP8 0
397 #define STATUSF_IP8 (_ULCAST_(1) << 0)
398 #define STATUSB_IP9 1
399 #define STATUSF_IP9 (_ULCAST_(1) << 1)
400 #define STATUSB_IP10 2
401 #define STATUSF_IP10 (_ULCAST_(1) << 2)
402 #define STATUSB_IP11 3
403 #define STATUSF_IP11 (_ULCAST_(1) << 3)
404 #define STATUSB_IP12 4
405 #define STATUSF_IP12 (_ULCAST_(1) << 4)
406 #define STATUSB_IP13 5
407 #define STATUSF_IP13 (_ULCAST_(1) << 5)
408 #define STATUSB_IP14 6
409 #define STATUSF_IP14 (_ULCAST_(1) << 6)
410 #define STATUSB_IP15 7
411 #define STATUSF_IP15 (_ULCAST_(1) << 7)
412 #define ST0_CH 0x00040000
413 #define ST0_NMI 0x00080000
414 #define ST0_SR 0x00100000
415 #define ST0_TS 0x00200000
416 #define ST0_BEV 0x00400000
417 #define ST0_RE 0x02000000
418 #define ST0_FR 0x04000000
419 #define ST0_CU 0xf0000000
420 #define ST0_CU0 0x10000000
421 #define ST0_CU1 0x20000000
422 #define ST0_CU2 0x40000000
423 #define ST0_CU3 0x80000000
424 #define ST0_XX 0x80000000 /* MIPS IV naming */
427 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
429 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
431 #define INTCTLB_IPPCI 26
432 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
433 #define INTCTLB_IPTI 29
434 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
437 * Bitfields and bit numbers in the coprocessor 0 cause register.
439 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
441 #define CAUSEB_EXCCODE 2
442 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
444 #define CAUSEF_IP (_ULCAST_(255) << 8)
446 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
448 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
449 #define CAUSEB_IP2 10
450 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
451 #define CAUSEB_IP3 11
452 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
453 #define CAUSEB_IP4 12
454 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
455 #define CAUSEB_IP5 13
456 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
457 #define CAUSEB_IP6 14
458 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
459 #define CAUSEB_IP7 15
460 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
462 #define CAUSEF_IV (_ULCAST_(1) << 23)
463 #define CAUSEB_PCI 26
464 #define CAUSEF_PCI (_ULCAST_(1) << 26)
466 #define CAUSEF_CE (_ULCAST_(3) << 28)
468 #define CAUSEF_TI (_ULCAST_(1) << 30)
470 #define CAUSEF_BD (_ULCAST_(1) << 31)
473 * Bits in the coprocessor 0 config register.
476 #define CONF_CM_CACHABLE_NO_WA 0
477 #define CONF_CM_CACHABLE_WA 1
478 #define CONF_CM_UNCACHED 2
479 #define CONF_CM_CACHABLE_NONCOHERENT 3
480 #define CONF_CM_CACHABLE_CE 4
481 #define CONF_CM_CACHABLE_COW 5
482 #define CONF_CM_CACHABLE_CUW 6
483 #define CONF_CM_CACHABLE_ACCELERATED 7
484 #define CONF_CM_CMASK 7
485 #define CONF_BE (_ULCAST_(1) << 15)
487 /* Bits common to various processors. */
488 #define CONF_CU (_ULCAST_(1) << 3)
489 #define CONF_DB (_ULCAST_(1) << 4)
490 #define CONF_IB (_ULCAST_(1) << 5)
491 #define CONF_DC (_ULCAST_(7) << 6)
492 #define CONF_IC (_ULCAST_(7) << 9)
493 #define CONF_EB (_ULCAST_(1) << 13)
494 #define CONF_EM (_ULCAST_(1) << 14)
495 #define CONF_SM (_ULCAST_(1) << 16)
496 #define CONF_SC (_ULCAST_(1) << 17)
497 #define CONF_EW (_ULCAST_(3) << 18)
498 #define CONF_EP (_ULCAST_(15)<< 24)
499 #define CONF_EC (_ULCAST_(7) << 28)
500 #define CONF_CM (_ULCAST_(1) << 31)
502 /* Bits specific to the R4xx0. */
503 #define R4K_CONF_SW (_ULCAST_(1) << 20)
504 #define R4K_CONF_SS (_ULCAST_(1) << 21)
505 #define R4K_CONF_SB (_ULCAST_(3) << 22)
507 /* Bits specific to the R5000. */
508 #define R5K_CONF_SE (_ULCAST_(1) << 12)
509 #define R5K_CONF_SS (_ULCAST_(3) << 20)
511 /* Bits specific to the RM7000. */
512 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
513 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
514 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
515 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
516 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
517 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
519 /* Bits specific to the R10000. */
520 #define R10K_CONF_DN (_ULCAST_(3) << 3)
521 #define R10K_CONF_CT (_ULCAST_(1) << 5)
522 #define R10K_CONF_PE (_ULCAST_(1) << 6)
523 #define R10K_CONF_PM (_ULCAST_(3) << 7)
524 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
525 #define R10K_CONF_SB (_ULCAST_(1) << 13)
526 #define R10K_CONF_SK (_ULCAST_(1) << 14)
527 #define R10K_CONF_SS (_ULCAST_(7) << 16)
528 #define R10K_CONF_SC (_ULCAST_(7) << 19)
529 #define R10K_CONF_DC (_ULCAST_(7) << 26)
530 #define R10K_CONF_IC (_ULCAST_(7) << 29)
532 /* Bits specific to the VR41xx. */
533 #define VR41_CONF_CS (_ULCAST_(1) << 12)
534 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
535 #define VR41_CONF_BP (_ULCAST_(1) << 16)
536 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
537 #define VR41_CONF_AD (_ULCAST_(1) << 23)
539 /* Bits specific to the R30xx. */
540 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
541 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
542 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
543 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
544 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
545 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
546 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
547 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
548 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
550 /* Bits specific to the TX49. */
551 #define TX49_CONF_DC (_ULCAST_(1) << 16)
552 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
553 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
554 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
556 /* Bits specific to the MIPS32/64 PRA. */
557 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
558 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
559 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
560 #define MIPS_CONF_M (_ULCAST_(1) << 31)
563 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
565 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
566 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
567 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
568 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
569 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
570 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
571 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
572 #define MIPS_CONF1_DA_SHF 7
573 #define MIPS_CONF1_DA_SZ 3
574 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
575 #define MIPS_CONF1_DL_SHF 10
576 #define MIPS_CONF1_DL_SZ 3
577 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
578 #define MIPS_CONF1_DS_SHF 13
579 #define MIPS_CONF1_DS_SZ 3
580 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
581 #define MIPS_CONF1_IA_SHF 16
582 #define MIPS_CONF1_IA_SZ 3
583 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
584 #define MIPS_CONF1_IL_SHF 19
585 #define MIPS_CONF1_IL_SZ 3
586 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
587 #define MIPS_CONF1_IS_SHF 22
588 #define MIPS_CONF1_IS_SZ 3
589 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
590 #define MIPS_CONF1_TLBS_SHIFT (25)
591 #define MIPS_CONF1_TLBS_SIZE (6)
592 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
594 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
595 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
596 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
597 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
598 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
599 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
600 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
601 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
603 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
604 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
605 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
606 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
607 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
608 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
609 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
610 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
611 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
612 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
613 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
614 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
615 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
616 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
617 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
618 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
619 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
620 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
621 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
622 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
623 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
624 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
625 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
626 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
627 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
628 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
629 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
631 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
632 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
633 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
634 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
635 #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
636 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
637 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
638 /* bits 10:8 in FTLB-only configurations */
639 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
640 /* bits 12:8 in VTLB-FTLB only configurations */
641 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
642 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
643 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
644 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
645 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
646 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
647 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
648 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
649 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
650 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
651 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
653 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
654 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
655 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
656 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
657 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
658 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
659 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
660 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
661 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
663 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
664 /* proAptiv FTLB on/off bit */
665 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
667 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
669 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
671 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
672 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
674 /* MAAR bit definitions */
675 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
676 #define MIPS_MAAR_ADDR_SHIFT 12
677 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
678 #define MIPS_MAAR_V (_ULCAST_(1) << 0)
680 /* EntryHI bit definition */
681 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
683 /* CMGCRBase bit definitions */
684 #define MIPS_CMGCRB_BASE 11
685 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
688 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
690 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
691 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
692 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
693 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
694 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
695 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
696 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
697 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
700 * Bits in the MIPS32 Memory Segmentation registers.
702 #define MIPS_SEGCFG_PA_SHIFT 9
703 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
704 #define MIPS_SEGCFG_AM_SHIFT 4
705 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
706 #define MIPS_SEGCFG_EU_SHIFT 3
707 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
708 #define MIPS_SEGCFG_C_SHIFT 0
709 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
711 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
712 #define MIPS_SEGCFG_USK _ULCAST_(5)
713 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
714 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
715 #define MIPS_SEGCFG_MSK _ULCAST_(2)
716 #define MIPS_SEGCFG_MK _ULCAST_(1)
717 #define MIPS_SEGCFG_UK _ULCAST_(0)
719 #define MIPS_PWFIELD_GDI_SHIFT 24
720 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
721 #define MIPS_PWFIELD_UDI_SHIFT 18
722 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
723 #define MIPS_PWFIELD_MDI_SHIFT 12
724 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
725 #define MIPS_PWFIELD_PTI_SHIFT 6
726 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
727 #define MIPS_PWFIELD_PTEI_SHIFT 0
728 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
730 #define MIPS_PWSIZE_GDW_SHIFT 24
731 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
732 #define MIPS_PWSIZE_UDW_SHIFT 18
733 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
734 #define MIPS_PWSIZE_MDW_SHIFT 12
735 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
736 #define MIPS_PWSIZE_PTW_SHIFT 6
737 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
738 #define MIPS_PWSIZE_PTEW_SHIFT 0
739 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
741 #define MIPS_PWCTL_PWEN_SHIFT 31
742 #define MIPS_PWCTL_PWEN_MASK 0x80000000
743 #define MIPS_PWCTL_DPH_SHIFT 7
744 #define MIPS_PWCTL_DPH_MASK 0x00000080
745 #define MIPS_PWCTL_HUGEPG_SHIFT 6
746 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
747 #define MIPS_PWCTL_PSN_SHIFT 0
748 #define MIPS_PWCTL_PSN_MASK 0x0000003f
753 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
755 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
756 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
757 #define get_isa16_mode(x) ((x) & 0x1)
758 #define msk_isa16_mode(x) ((x) & ~0x1)
759 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
761 #define get_isa16_mode(x) 0
762 #define msk_isa16_mode(x) (x)
763 #define set_isa16_mode(x) do { } while(0)
767 * microMIPS instructions can be 16-bit or 32-bit in length. This
768 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
770 static inline int mm_insn_16bit(u16 insn)
772 u16 opcode = (insn >> 10) & 0x7;
774 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
778 * TLB Invalidate Flush
780 static inline void tlbinvf(void)
782 __asm__ __volatile__(
785 ".word 0x42000004\n\t" /* tlbinvf */
791 * Functions to access the R10000 performance counters. These are basically
792 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
793 * performance counter number encoded into bits 1 ... 5 of the instruction.
794 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
795 * disassembler these will look like an access to sel 0 or 1.
797 #define read_r10k_perf_cntr(counter) \
799 unsigned int __res; \
800 __asm__ __volatile__( \
808 #define write_r10k_perf_cntr(counter,val) \
810 __asm__ __volatile__( \
813 : "r" (val), "i" (counter)); \
816 #define read_r10k_perf_event(counter) \
818 unsigned int __res; \
819 __asm__ __volatile__( \
827 #define write_r10k_perf_cntl(counter,val) \
829 __asm__ __volatile__( \
832 : "r" (val), "i" (counter)); \
837 * Macros to access the system control coprocessor
840 #define __read_32bit_c0_register(source, sel) \
843 __asm__ __volatile__( \
844 "mfc0\t%0, " #source "\n\t" \
847 __asm__ __volatile__( \
849 "mfc0\t%0, " #source ", " #sel "\n\t" \
855 #define __read_64bit_c0_register(source, sel) \
856 ({ unsigned long long __res; \
857 if (sizeof(unsigned long) == 4) \
858 __res = __read_64bit_c0_split(source, sel); \
860 __asm__ __volatile__( \
862 "dmfc0\t%0, " #source "\n\t" \
866 __asm__ __volatile__( \
868 "dmfc0\t%0, " #source ", " #sel "\n\t" \
874 #define __write_32bit_c0_register(register, sel, value) \
877 __asm__ __volatile__( \
878 "mtc0\t%z0, " #register "\n\t" \
879 : : "Jr" ((unsigned int)(value))); \
881 __asm__ __volatile__( \
883 "mtc0\t%z0, " #register ", " #sel "\n\t" \
885 : : "Jr" ((unsigned int)(value))); \
888 #define __write_64bit_c0_register(register, sel, value) \
890 if (sizeof(unsigned long) == 4) \
891 __write_64bit_c0_split(register, sel, value); \
893 __asm__ __volatile__( \
895 "dmtc0\t%z0, " #register "\n\t" \
899 __asm__ __volatile__( \
901 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
906 #define __read_ulong_c0_register(reg, sel) \
907 ((sizeof(unsigned long) == 4) ? \
908 (unsigned long) __read_32bit_c0_register(reg, sel) : \
909 (unsigned long) __read_64bit_c0_register(reg, sel))
911 #define __write_ulong_c0_register(reg, sel, val) \
913 if (sizeof(unsigned long) == 4) \
914 __write_32bit_c0_register(reg, sel, val); \
916 __write_64bit_c0_register(reg, sel, val); \
920 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
922 #define __read_32bit_c0_ctrl_register(source) \
924 __asm__ __volatile__( \
925 "cfc0\t%0, " #source "\n\t" \
930 #define __write_32bit_c0_ctrl_register(register, value) \
932 __asm__ __volatile__( \
933 "ctc0\t%z0, " #register "\n\t" \
934 : : "Jr" ((unsigned int)(value))); \
938 * These versions are only needed for systems with more than 38 bits of
939 * physical address space running the 32-bit kernel. That's none atm :-)
941 #define __read_64bit_c0_split(source, sel) \
943 unsigned long long __val; \
944 unsigned long __flags; \
946 local_irq_save(__flags); \
948 __asm__ __volatile__( \
950 "dmfc0\t%M0, " #source "\n\t" \
951 "dsll\t%L0, %M0, 32\n\t" \
952 "dsra\t%M0, %M0, 32\n\t" \
953 "dsra\t%L0, %L0, 32\n\t" \
957 __asm__ __volatile__( \
959 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
960 "dsll\t%L0, %M0, 32\n\t" \
961 "dsra\t%M0, %M0, 32\n\t" \
962 "dsra\t%L0, %L0, 32\n\t" \
965 local_irq_restore(__flags); \
970 #define __write_64bit_c0_split(source, sel, val) \
972 unsigned long __flags; \
974 local_irq_save(__flags); \
976 __asm__ __volatile__( \
978 "dsll\t%L0, %L0, 32\n\t" \
979 "dsrl\t%L0, %L0, 32\n\t" \
980 "dsll\t%M0, %M0, 32\n\t" \
981 "or\t%L0, %L0, %M0\n\t" \
982 "dmtc0\t%L0, " #source "\n\t" \
986 __asm__ __volatile__( \
988 "dsll\t%L0, %L0, 32\n\t" \
989 "dsrl\t%L0, %L0, 32\n\t" \
990 "dsll\t%M0, %M0, 32\n\t" \
991 "or\t%L0, %L0, %M0\n\t" \
992 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
995 local_irq_restore(__flags); \
998 #define read_c0_index() __read_32bit_c0_register($0, 0)
999 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1001 #define read_c0_random() __read_32bit_c0_register($1, 0)
1002 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1004 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1005 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1007 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1008 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1010 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1011 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1013 #define read_c0_context() __read_ulong_c0_register($4, 0)
1014 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1016 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1017 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1019 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1020 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1022 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1023 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1025 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1026 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1028 #define read_c0_info() __read_32bit_c0_register($7, 0)
1030 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1031 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1033 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1034 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1036 #define read_c0_count() __read_32bit_c0_register($9, 0)
1037 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1039 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1040 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1042 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1043 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1045 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1046 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1048 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1049 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1051 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1052 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1054 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1055 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1057 #define read_c0_status() __read_32bit_c0_register($12, 0)
1059 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1061 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1062 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1064 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1065 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1067 #define read_c0_prid() __read_32bit_c0_register($15, 0)
1069 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1071 #define read_c0_config() __read_32bit_c0_register($16, 0)
1072 #define read_c0_config1() __read_32bit_c0_register($16, 1)
1073 #define read_c0_config2() __read_32bit_c0_register($16, 2)
1074 #define read_c0_config3() __read_32bit_c0_register($16, 3)
1075 #define read_c0_config4() __read_32bit_c0_register($16, 4)
1076 #define read_c0_config5() __read_32bit_c0_register($16, 5)
1077 #define read_c0_config6() __read_32bit_c0_register($16, 6)
1078 #define read_c0_config7() __read_32bit_c0_register($16, 7)
1079 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1080 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1081 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1082 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1083 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1084 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1085 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1086 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1088 #define read_c0_maar() __read_ulong_c0_register($17, 1)
1089 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1090 #define read_c0_maari() __read_32bit_c0_register($17, 2)
1091 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1094 * The WatchLo register. There may be up to 8 of them.
1096 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1097 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1098 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1099 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1100 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1101 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1102 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1103 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1104 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1105 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1106 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1107 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1108 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1109 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1110 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1111 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1114 * The WatchHi register. There may be up to 8 of them.
1116 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1117 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1118 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1119 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1120 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1121 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1122 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1123 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1125 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1126 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1127 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1128 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1129 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1130 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1131 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1132 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1134 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1135 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1137 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1138 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1140 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1141 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1143 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1144 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1146 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
1147 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1149 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
1150 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1152 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
1153 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1155 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
1156 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1158 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
1159 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1161 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1162 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1164 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1165 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1168 * MIPS32 / MIPS64 performance counters
1170 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1171 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1172 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1173 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1174 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1175 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1176 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1177 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1178 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1179 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1180 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1181 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1182 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1183 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1184 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1185 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1186 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1187 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1188 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1189 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1190 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1191 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1192 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1193 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1195 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1196 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1198 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1199 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1201 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1203 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1204 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1206 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1207 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1209 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1210 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1212 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1213 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1215 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1216 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1218 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1219 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1221 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1222 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1225 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1226 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1228 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1229 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1231 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1232 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1234 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1235 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1237 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1238 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1241 #define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1242 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1244 #define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1245 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1247 #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1248 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1250 /* Hardware Page Table Walker */
1251 #define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1252 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1254 #define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1255 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1257 #define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1258 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1260 #define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1261 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1263 /* Cavium OCTEON (cnMIPS) */
1264 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1265 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1267 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1268 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1270 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1271 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1273 * The cacheerr registers are not standardized. On OCTEON, they are
1276 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1277 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1279 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1280 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1283 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1284 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1286 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1287 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1289 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1290 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1293 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1294 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1296 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1297 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1299 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1300 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1302 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1303 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1305 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1306 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1309 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1310 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1312 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1313 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1315 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1316 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1318 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1319 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1321 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1322 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1324 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1325 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1328 * Macros to access the floating point coprocessor control registers
1330 #define _read_32bit_cp1_register(source, gas_hardfloat) \
1334 __asm__ __volatile__( \
1336 " .set reorder \n" \
1337 " # gas fails to assemble cfc1 for some archs, \n" \
1338 " # like Octeon. \n" \
1340 " "STR(gas_hardfloat)" \n" \
1341 " cfc1 %0,"STR(source)" \n" \
1347 #ifdef GAS_HAS_SET_HARDFLOAT
1348 #define read_32bit_cp1_register(source) \
1349 _read_32bit_cp1_register(source, .set hardfloat)
1351 #define read_32bit_cp1_register(source) \
1352 _read_32bit_cp1_register(source, )
1356 #define rddsp(mask) \
1358 unsigned int __dspctl; \
1360 __asm__ __volatile__( \
1363 " rddsp %0, %x1 \n" \
1370 #define wrdsp(val, mask) \
1372 __asm__ __volatile__( \
1375 " wrdsp %0, %x1 \n" \
1378 : "r" (val), "i" (mask)); \
1387 " mflo %0, $ac0 \n" \
1399 " mflo %0, $ac1 \n" \
1411 " mflo %0, $ac2 \n" \
1423 " mflo %0, $ac3 \n" \
1435 " mfhi %0, $ac0 \n" \
1447 " mfhi %0, $ac1 \n" \
1459 " mfhi %0, $ac2 \n" \
1471 " mfhi %0, $ac3 \n" \
1483 " mtlo %0, $ac0 \n" \
1494 " mtlo %0, $ac1 \n" \
1505 " mtlo %0, $ac2 \n" \
1516 " mtlo %0, $ac3 \n" \
1527 " mthi %0, $ac0 \n" \
1538 " mthi %0, $ac1 \n" \
1549 " mthi %0, $ac2 \n" \
1560 " mthi %0, $ac3 \n" \
1568 #ifdef CONFIG_CPU_MICROMIPS
1569 #define rddsp(mask) \
1571 unsigned int __res; \
1573 __asm__ __volatile__( \
1576 " # rddsp $1, %x1 \n" \
1577 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1578 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1586 #define wrdsp(val, mask) \
1588 __asm__ __volatile__( \
1592 " # wrdsp $1, %x1 \n" \
1593 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1594 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1597 : "r" (val), "i" (mask)); \
1600 #define _umips_dsp_mfxxx(ins) \
1602 unsigned long __treg; \
1604 __asm__ __volatile__( \
1607 " .hword 0x0001 \n" \
1616 #define _umips_dsp_mtxxx(val, ins) \
1618 __asm__ __volatile__( \
1622 " .hword 0x0001 \n" \
1626 : "r" (val), "i" (ins)); \
1629 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1630 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1632 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1633 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1635 #define mflo0() _umips_dsp_mflo(0)
1636 #define mflo1() _umips_dsp_mflo(1)
1637 #define mflo2() _umips_dsp_mflo(2)
1638 #define mflo3() _umips_dsp_mflo(3)
1640 #define mfhi0() _umips_dsp_mfhi(0)
1641 #define mfhi1() _umips_dsp_mfhi(1)
1642 #define mfhi2() _umips_dsp_mfhi(2)
1643 #define mfhi3() _umips_dsp_mfhi(3)
1645 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1646 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1647 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1648 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1650 #define mthi0(x) _umips_dsp_mthi(x, 0)
1651 #define mthi1(x) _umips_dsp_mthi(x, 1)
1652 #define mthi2(x) _umips_dsp_mthi(x, 2)
1653 #define mthi3(x) _umips_dsp_mthi(x, 3)
1655 #else /* !CONFIG_CPU_MICROMIPS */
1656 #define rddsp(mask) \
1658 unsigned int __res; \
1660 __asm__ __volatile__( \
1663 " # rddsp $1, %x1 \n" \
1664 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1672 #define wrdsp(val, mask) \
1674 __asm__ __volatile__( \
1678 " # wrdsp $1, %x1 \n" \
1679 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1682 : "r" (val), "i" (mask)); \
1685 #define _dsp_mfxxx(ins) \
1687 unsigned long __treg; \
1689 __asm__ __volatile__( \
1692 " .word (0x00000810 | %1) \n" \
1700 #define _dsp_mtxxx(val, ins) \
1702 __asm__ __volatile__( \
1706 " .word (0x00200011 | %1) \n" \
1709 : "r" (val), "i" (ins)); \
1712 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1713 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1715 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1716 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1718 #define mflo0() _dsp_mflo(0)
1719 #define mflo1() _dsp_mflo(1)
1720 #define mflo2() _dsp_mflo(2)
1721 #define mflo3() _dsp_mflo(3)
1723 #define mfhi0() _dsp_mfhi(0)
1724 #define mfhi1() _dsp_mfhi(1)
1725 #define mfhi2() _dsp_mfhi(2)
1726 #define mfhi3() _dsp_mfhi(3)
1728 #define mtlo0(x) _dsp_mtlo(x, 0)
1729 #define mtlo1(x) _dsp_mtlo(x, 1)
1730 #define mtlo2(x) _dsp_mtlo(x, 2)
1731 #define mtlo3(x) _dsp_mtlo(x, 3)
1733 #define mthi0(x) _dsp_mthi(x, 0)
1734 #define mthi1(x) _dsp_mthi(x, 1)
1735 #define mthi2(x) _dsp_mthi(x, 2)
1736 #define mthi3(x) _dsp_mthi(x, 3)
1738 #endif /* CONFIG_CPU_MICROMIPS */
1744 * It is responsibility of the caller to take care of any TLB hazards.
1746 static inline void tlb_probe(void)
1748 __asm__ __volatile__(
1749 ".set noreorder\n\t"
1754 static inline void tlb_read(void)
1756 #if MIPS34K_MISSED_ITLB_WAR
1759 __asm__ __volatile__(
1761 " .set noreorder \n"
1764 " .word 0x41610001 # dvpe $1 \n"
1770 instruction_hazard();
1773 __asm__ __volatile__(
1774 ".set noreorder\n\t"
1778 #if MIPS34K_MISSED_ITLB_WAR
1779 if ((res & _ULCAST_(1)))
1780 __asm__ __volatile__(
1782 " .set noreorder \n"
1785 " .word 0x41600021 # evpe \n"
1791 static inline void tlb_write_indexed(void)
1793 __asm__ __volatile__(
1794 ".set noreorder\n\t"
1799 static inline void tlb_write_random(void)
1801 __asm__ __volatile__(
1802 ".set noreorder\n\t"
1808 * Manipulate bits in a c0 register.
1810 #define __BUILD_SET_C0(name) \
1811 static inline unsigned int \
1812 set_c0_##name(unsigned int set) \
1814 unsigned int res, new; \
1816 res = read_c0_##name(); \
1818 write_c0_##name(new); \
1823 static inline unsigned int \
1824 clear_c0_##name(unsigned int clear) \
1826 unsigned int res, new; \
1828 res = read_c0_##name(); \
1829 new = res & ~clear; \
1830 write_c0_##name(new); \
1835 static inline unsigned int \
1836 change_c0_##name(unsigned int change, unsigned int val) \
1838 unsigned int res, new; \
1840 res = read_c0_##name(); \
1841 new = res & ~change; \
1842 new |= (val & change); \
1843 write_c0_##name(new); \
1848 __BUILD_SET_C0(status)
1849 __BUILD_SET_C0(cause)
1850 __BUILD_SET_C0(config)
1851 __BUILD_SET_C0(config5)
1852 __BUILD_SET_C0(intcontrol)
1853 __BUILD_SET_C0(intctl)
1854 __BUILD_SET_C0(srsmap)
1855 __BUILD_SET_C0(brcm_config_0)
1856 __BUILD_SET_C0(brcm_bus_pll)
1857 __BUILD_SET_C0(brcm_reset)
1858 __BUILD_SET_C0(brcm_cmt_intr)
1859 __BUILD_SET_C0(brcm_cmt_ctrl)
1860 __BUILD_SET_C0(brcm_config)
1861 __BUILD_SET_C0(brcm_mode)
1864 * Return low 10 bits of ebase.
1865 * Note that under KVM (MIPSVZ) this returns vcpu id.
1867 static inline unsigned int get_ebase_cpunum(void)
1869 return read_c0_ebase() & 0x3ff;
1872 #endif /* !__ASSEMBLY__ */
1874 #endif /* _ASM_MIPSREGS_H */