arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_WIRED $6
  52 #define CP0_INFO $7
  53 #define CP0_BADVADDR $8
  54 #define CP0_COUNT $9
  55 #define CP0_ENTRYHI $10
  56 #define CP0_COMPARE $11
  57 #define CP0_STATUS $12
  58 #define CP0_CAUSE $13
  59 #define CP0_EPC $14
  60 #define CP0_PRID $15
  61 #define CP0_CONFIG $16
  62 #define CP0_LLADDR $17
  63 #define CP0_WATCHLO $18
  64 #define CP0_WATCHHI $19
  65 #define CP0_XCONTEXT $20
  66 #define CP0_FRAMEMASK $21
  67 #define CP0_DIAGNOSTIC $22
  68 #define CP0_DEBUG $23
  69 #define CP0_DEPC $24
  70 #define CP0_PERFORMANCE $25
  71 #define CP0_ECC $26
  72 #define CP0_CACHEERR $27
  73 #define CP0_TAGLO $28
  74 #define CP0_TAGHI $29
  75 #define CP0_ERROREPC $30
  76 #define CP0_DESAVE $31
  77
  78 /*
  79  * R4640/R4650 cp0 register names.  These registers are listed
  80  * here only for completeness; without MMU these CPUs are not useable
  81  * by Linux.  A future ELKS port might take make Linux run on them
  82  * though ...
  83  */
  84 #define CP0_IBASE $0
  85 #define CP0_IBOUND $1
  86 #define CP0_DBASE $2
  87 #define CP0_DBOUND $3
  88 #define CP0_CALG $17
  89 #define CP0_IWATCH $18
  90 #define CP0_DWATCH $19
  91
  92 /*
  93  * Coprocessor 0 Set 1 register names
  94  */
  95 #define CP0_S1_DERRADDR0  $26
  96 #define CP0_S1_DERRADDR1  $27
  97 #define CP0_S1_INTCONTROL $20
  98
  99 /*
 100  * Coprocessor 0 Set 2 register names
 101  */
 102 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 103
 104 /*
 105  * Coprocessor 0 Set 3 register names
 106  */
 107 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 108
 109 /*
 110  *  TX39 Series
 111  */
 112 #define CP0_TX39_CACHE  $7
 113
 114 /*
 115  * Coprocessor 1 (FPU) register names
 116  */
 117 #define CP1_REVISION   $0
 118 #define CP1_STATUS     $31
 119
 120 /*
 121  * FPU Status Register Values
 122  */
 123 /*
 124  * Status Register Values
 125  */
 126
 127 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
 128 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
 129 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
 130 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
 131 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
 132 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
 133 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
 134 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
 135 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
 136 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
 137
 138 /*
 139  * Bits 18 - 20 of the FPU Status Register will be read as 0,
 140  * and should be written as zero.
 141  */
 142 #define FPU_CSR_RSVD    0x001c0000
 143
 144 /*
 145  * X the exception cause indicator
 146  * E the exception enable
 147  * S the sticky/flag bit
 148 */
 149 #define FPU_CSR_ALL_X   0x0003f000
 150 #define FPU_CSR_UNI_X   0x00020000
 151 #define FPU_CSR_INV_X   0x00010000
 152 #define FPU_CSR_DIV_X   0x00008000
 153 #define FPU_CSR_OVF_X   0x00004000
 154 #define FPU_CSR_UDF_X   0x00002000
 155 #define FPU_CSR_INE_X   0x00001000
 156
 157 #define FPU_CSR_ALL_E   0x00000f80
 158 #define FPU_CSR_INV_E   0x00000800
 159 #define FPU_CSR_DIV_E   0x00000400
 160 #define FPU_CSR_OVF_E   0x00000200
 161 #define FPU_CSR_UDF_E   0x00000100
 162 #define FPU_CSR_INE_E   0x00000080
 163
 164 #define FPU_CSR_ALL_S   0x0000007c
 165 #define FPU_CSR_INV_S   0x00000040
 166 #define FPU_CSR_DIV_S   0x00000020
 167 #define FPU_CSR_OVF_S   0x00000010
 168 #define FPU_CSR_UDF_S   0x00000008
 169 #define FPU_CSR_INE_S   0x00000004
 170
 171 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 172 #define FPU_CSR_RM      0x00000003
 173 #define FPU_CSR_RN      0x0     /* nearest */
 174 #define FPU_CSR_RZ      0x1     /* towards zero */
 175 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 176 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 177
 178
 179 /*
 180  * Values for PageMask register
 181  */
 182 #ifdef CONFIG_CPU_VR41XX
 183
 184 /* Why doesn't stupidity hurt ... */
 185
 186 #define PM_1K           0x00000000
 187 #define PM_4K           0x00001800
 188 #define PM_16K          0x00007800
 189 #define PM_64K          0x0001f800
 190 #define PM_256K         0x0007f800
 191
 192 #else
 193
 194 #define PM_4K           0x00000000
 195 #define PM_8K           0x00002000
 196 #define PM_16K          0x00006000
 197 #define PM_32K          0x0000e000
 198 #define PM_64K          0x0001e000
 199 #define PM_128K         0x0003e000
 200 #define PM_256K         0x0007e000
 201 #define PM_512K         0x000fe000
 202 #define PM_1M           0x001fe000
 203 #define PM_2M           0x003fe000
 204 #define PM_4M           0x007fe000
 205 #define PM_8M           0x00ffe000
 206 #define PM_16M          0x01ffe000
 207 #define PM_32M          0x03ffe000
 208 #define PM_64M          0x07ffe000
 209 #define PM_256M         0x1fffe000
 210 #define PM_1G           0x7fffe000
 211
 212 #endif
 213
 214 /*
 215  * Default page size for a given kernel configuration
 216  */
 217 #ifdef CONFIG_PAGE_SIZE_4KB
 218 #define PM_DEFAULT_MASK PM_4K
 219 #elif defined(CONFIG_PAGE_SIZE_8KB)
 220 #define PM_DEFAULT_MASK PM_8K
 221 #elif defined(CONFIG_PAGE_SIZE_16KB)
 222 #define PM_DEFAULT_MASK PM_16K
 223 #elif defined(CONFIG_PAGE_SIZE_32KB)
 224 #define PM_DEFAULT_MASK PM_32K
 225 #elif defined(CONFIG_PAGE_SIZE_64KB)
 226 #define PM_DEFAULT_MASK PM_64K
 227 #else
 228 #error Bad page size configuration!
 229 #endif
 230
 231 /*
 232  * Default huge tlb size for a given kernel configuration
 233  */
 234 #ifdef CONFIG_PAGE_SIZE_4KB
 235 #define PM_HUGE_MASK    PM_1M
 236 #elif defined(CONFIG_PAGE_SIZE_8KB)
 237 #define PM_HUGE_MASK    PM_4M
 238 #elif defined(CONFIG_PAGE_SIZE_16KB)
 239 #define PM_HUGE_MASK    PM_16M
 240 #elif defined(CONFIG_PAGE_SIZE_32KB)
 241 #define PM_HUGE_MASK    PM_64M
 242 #elif defined(CONFIG_PAGE_SIZE_64KB)
 243 #define PM_HUGE_MASK    PM_256M
 244 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 245 #error Bad page size configuration for hugetlbfs!
 246 #endif
 247
 248 /*
 249  * Values used for computation of new tlb entries
 250  */
 251 #define PL_4K           12
 252 #define PL_16K          14
 253 #define PL_64K          16
 254 #define PL_256K         18
 255 #define PL_1M           20
 256 #define PL_4M           22
 257 #define PL_16M          24
 258 #define PL_64M          26
 259 #define PL_256M         28
 260
 261 /*
 262  * PageGrain bits
 263  */
 264 #define PG_RIE          (_ULCAST_(1) <<  31)
 265 #define PG_XIE          (_ULCAST_(1) <<  30)
 266 #define PG_ELPA         (_ULCAST_(1) <<  29)
 267 #define PG_ESP          (_ULCAST_(1) <<  28)
 268
 269 /*
 270  * R4x00 interrupt enable / cause bits
 271  */
 272 #define IE_SW0          (_ULCAST_(1) <<  8)
 273 #define IE_SW1          (_ULCAST_(1) <<  9)
 274 #define IE_IRQ0         (_ULCAST_(1) << 10)
 275 #define IE_IRQ1         (_ULCAST_(1) << 11)
 276 #define IE_IRQ2         (_ULCAST_(1) << 12)
 277 #define IE_IRQ3         (_ULCAST_(1) << 13)
 278 #define IE_IRQ4         (_ULCAST_(1) << 14)
 279 #define IE_IRQ5         (_ULCAST_(1) << 15)
 280
 281 /*
 282  * R4x00 interrupt cause bits
 283  */
 284 #define C_SW0           (_ULCAST_(1) <<  8)
 285 #define C_SW1           (_ULCAST_(1) <<  9)
 286 #define C_IRQ0          (_ULCAST_(1) << 10)
 287 #define C_IRQ1          (_ULCAST_(1) << 11)
 288 #define C_IRQ2          (_ULCAST_(1) << 12)
 289 #define C_IRQ3          (_ULCAST_(1) << 13)
 290 #define C_IRQ4          (_ULCAST_(1) << 14)
 291 #define C_IRQ5          (_ULCAST_(1) << 15)
 292
 293 /*
 294  * Bitfields in the R4xx0 cp0 status register
 295  */
 296 #define ST0_IE                  0x00000001
 297 #define ST0_EXL                 0x00000002
 298 #define ST0_ERL                 0x00000004
 299 #define ST0_KSU                 0x00000018
 300 #  define KSU_USER              0x00000010
 301 #  define KSU_SUPERVISOR        0x00000008
 302 #  define KSU_KERNEL            0x00000000
 303 #define ST0_UX                  0x00000020
 304 #define ST0_SX                  0x00000040
 305 #define ST0_KX                  0x00000080
 306 #define ST0_DE                  0x00010000
 307 #define ST0_CE                  0x00020000
 308
 309 /*
 310  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 311  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 312  * processors.
 313  */
 314 #define ST0_CO                  0x08000000
 315
 316 /*
 317  * Bitfields in the R[23]000 cp0 status register.
 318  */
 319 #define ST0_IEC                 0x00000001
 320 #define ST0_KUC                 0x00000002
 321 #define ST0_IEP                 0x00000004
 322 #define ST0_KUP                 0x00000008
 323 #define ST0_IEO                 0x00000010
 324 #define ST0_KUO                 0x00000020
 325 /* bits 6 & 7 are reserved on R[23]000 */
 326 #define ST0_ISC                 0x00010000
 327 #define ST0_SWC                 0x00020000
 328 #define ST0_CM                  0x00080000
 329
 330 /*
 331  * Bits specific to the R4640/R4650
 332  */
 333 #define ST0_UM                  (_ULCAST_(1) <<  4)
 334 #define ST0_IL                  (_ULCAST_(1) << 23)
 335 #define ST0_DL                  (_ULCAST_(1) << 24)
 336
 337 /*
 338  * Enable the MIPS MDMX and DSP ASEs
 339  */
 340 #define ST0_MX                  0x01000000
 341
 342 /*
 343  * Bitfields in the TX39 family CP0 Configuration Register 3
 344  */
 345 #define TX39_CONF_ICS_SHIFT     19
 346 #define TX39_CONF_ICS_MASK      0x00380000
 347 #define TX39_CONF_ICS_1KB       0x00000000
 348 #define TX39_CONF_ICS_2KB       0x00080000
 349 #define TX39_CONF_ICS_4KB       0x00100000
 350 #define TX39_CONF_ICS_8KB       0x00180000
 351 #define TX39_CONF_ICS_16KB      0x00200000
 352
 353 #define TX39_CONF_DCS_SHIFT     16
 354 #define TX39_CONF_DCS_MASK      0x00070000
 355 #define TX39_CONF_DCS_1KB       0x00000000
 356 #define TX39_CONF_DCS_2KB       0x00010000
 357 #define TX39_CONF_DCS_4KB       0x00020000
 358 #define TX39_CONF_DCS_8KB       0x00030000
 359 #define TX39_CONF_DCS_16KB      0x00040000
 360
 361 #define TX39_CONF_CWFON         0x00004000
 362 #define TX39_CONF_WBON          0x00002000
 363 #define TX39_CONF_RF_SHIFT      10
 364 #define TX39_CONF_RF_MASK       0x00000c00
 365 #define TX39_CONF_DOZE          0x00000200
 366 #define TX39_CONF_HALT          0x00000100
 367 #define TX39_CONF_LOCK          0x00000080
 368 #define TX39_CONF_ICE           0x00000020
 369 #define TX39_CONF_DCE           0x00000010
 370 #define TX39_CONF_IRSIZE_SHIFT  2
 371 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 372 #define TX39_CONF_DRSIZE_SHIFT  0
 373 #define TX39_CONF_DRSIZE_MASK   0x00000003
 374
 375 /*
 376  * Status register bits available in all MIPS CPUs.
 377  */
 378 #define ST0_IM                  0x0000ff00
 379 #define  STATUSB_IP0            8
 380 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 381 #define  STATUSB_IP1            9
 382 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 383 #define  STATUSB_IP2            10
 384 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 385 #define  STATUSB_IP3            11
 386 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 387 #define  STATUSB_IP4            12
 388 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 389 #define  STATUSB_IP5            13
 390 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 391 #define  STATUSB_IP6            14
 392 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 393 #define  STATUSB_IP7            15
 394 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 395 #define  STATUSB_IP8            0
 396 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 397 #define  STATUSB_IP9            1
 398 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 399 #define  STATUSB_IP10           2
 400 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 401 #define  STATUSB_IP11           3
 402 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 403 #define  STATUSB_IP12           4
 404 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 405 #define  STATUSB_IP13           5
 406 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 407 #define  STATUSB_IP14           6
 408 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 409 #define  STATUSB_IP15           7
 410 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 411 #define ST0_CH                  0x00040000
 412 #define ST0_NMI                 0x00080000
 413 #define ST0_SR                  0x00100000
 414 #define ST0_TS                  0x00200000
 415 #define ST0_BEV                 0x00400000
 416 #define ST0_RE                  0x02000000
 417 #define ST0_FR                  0x04000000
 418 #define ST0_CU                  0xf0000000
 419 #define ST0_CU0                 0x10000000
 420 #define ST0_CU1                 0x20000000
 421 #define ST0_CU2                 0x40000000
 422 #define ST0_CU3                 0x80000000
 423 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 424
 425 /*
 426  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 427  *
 428  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 429  */
 430 #define INTCTLB_IPPCI           26
 431 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 432 #define INTCTLB_IPTI            29
 433 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 434
 435 /*
 436  * Bitfields and bit numbers in the coprocessor 0 cause register.
 437  *
 438  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 439  */
 440 #define  CAUSEB_EXCCODE         2
 441 #define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
 442 #define  CAUSEB_IP              8
 443 #define  CAUSEF_IP              (_ULCAST_(255) <<  8)
 444 #define  CAUSEB_IP0             8
 445 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 446 #define  CAUSEB_IP1             9
 447 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 448 #define  CAUSEB_IP2             10
 449 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 450 #define  CAUSEB_IP3             11
 451 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 452 #define  CAUSEB_IP4             12
 453 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 454 #define  CAUSEB_IP5             13
 455 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 456 #define  CAUSEB_IP6             14
 457 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 458 #define  CAUSEB_IP7             15
 459 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 460 #define  CAUSEB_IV              23
 461 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
 462 #define  CAUSEB_PCI             26
 463 #define  CAUSEF_PCI             (_ULCAST_(1)   << 26)
 464 #define  CAUSEB_CE              28
 465 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
 466 #define  CAUSEB_TI              30
 467 #define  CAUSEF_TI              (_ULCAST_(1)   << 30)
 468 #define  CAUSEB_BD              31
 469 #define  CAUSEF_BD              (_ULCAST_(1)   << 31)
 470
 471 /*
 472  * Bits in the coprocessor 0 config register.
 473  */
 474 /* Generic bits.  */
 475 #define CONF_CM_CACHABLE_NO_WA          0
 476 #define CONF_CM_CACHABLE_WA             1
 477 #define CONF_CM_UNCACHED                2
 478 #define CONF_CM_CACHABLE_NONCOHERENT    3
 479 #define CONF_CM_CACHABLE_CE             4
 480 #define CONF_CM_CACHABLE_COW            5
 481 #define CONF_CM_CACHABLE_CUW            6
 482 #define CONF_CM_CACHABLE_ACCELERATED    7
 483 #define CONF_CM_CMASK                   7
 484 #define CONF_BE                 (_ULCAST_(1) << 15)
 485
 486 /* Bits common to various processors.  */
 487 #define CONF_CU                 (_ULCAST_(1) <<  3)
 488 #define CONF_DB                 (_ULCAST_(1) <<  4)
 489 #define CONF_IB                 (_ULCAST_(1) <<  5)
 490 #define CONF_DC                 (_ULCAST_(7) <<  6)
 491 #define CONF_IC                 (_ULCAST_(7) <<  9)
 492 #define CONF_EB                 (_ULCAST_(1) << 13)
 493 #define CONF_EM                 (_ULCAST_(1) << 14)
 494 #define CONF_SM                 (_ULCAST_(1) << 16)
 495 #define CONF_SC                 (_ULCAST_(1) << 17)
 496 #define CONF_EW                 (_ULCAST_(3) << 18)
 497 #define CONF_EP                 (_ULCAST_(15)<< 24)
 498 #define CONF_EC                 (_ULCAST_(7) << 28)
 499 #define CONF_CM                 (_ULCAST_(1) << 31)
 500
 501 /* Bits specific to the R4xx0.  */
 502 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 503 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 504 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 505
 506 /* Bits specific to the R5000.  */
 507 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 508 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 509
 510 /* Bits specific to the RM7000.  */
 511 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 512 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 513 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 514 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 515 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 516 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 517
 518 /* Bits specific to the R10000.  */
 519 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 520 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 521 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 522 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 523 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 524 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 525 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 526 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 527 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 528 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 529 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 530
 531 /* Bits specific to the VR41xx.  */
 532 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 533 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 534 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 535 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 536 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 537
 538 /* Bits specific to the R30xx.  */
 539 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 540 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 541 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 542 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 543 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 544 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 545 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 546 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 547 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 548
 549 /* Bits specific to the TX49.  */
 550 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 551 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 552 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 553 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 554
 555 /* Bits specific to the MIPS32/64 PRA.  */
 556 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 557 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 558 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 559 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 560
 561 /*
 562  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 563  */
 564 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 565 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 566 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 567 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 568 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 569 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 570 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 571 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 572 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 573 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 574 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 575 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 576 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 577 #define MIPS_CONF1_TLBS_SHIFT   (25)
 578 #define MIPS_CONF1_TLBS_SIZE    (6)
 579 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 580
 581 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 582 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 583 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 584 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 585 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 586 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 587 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 588 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 589
 590 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 591 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 592 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 593 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 594 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 595 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 596 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 597 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 598 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 599 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 600 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 601 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 602 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 603 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 604 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 605 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 606 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 607 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 608 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 609 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 610 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 611 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 612 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 613 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 614 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 615 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 616 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 617
 618 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 619 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 620 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 621 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 622 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 623 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 624 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 625 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 626 /* bits 10:8 in FTLB-only configurations */
 627 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 628 /* bits 12:8 in VTLB-FTLB only configurations */
 629 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 630 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 631 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 632 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 633 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 634 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << 16)
 635 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 636 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 637 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 638 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 639 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 640
 641 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 642 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 643 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 644 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 645 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 646 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 647
 648 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 649 /* proAptiv FTLB on/off bit */
 650 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 651
 652 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 653
 654 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 655
 656 /*  EntryHI bit definition */
 657 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 658
 659 /*
 660  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 661  */
 662 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 663 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 664 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 665 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 666 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 667 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 668 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 669
 670 /*
 671  * Bits in the MIPS32 Memory Segmentation registers.
 672  */
 673 #define MIPS_SEGCFG_PA_SHIFT    9
 674 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 675 #define MIPS_SEGCFG_AM_SHIFT    4
 676 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 677 #define MIPS_SEGCFG_EU_SHIFT    3
 678 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 679 #define MIPS_SEGCFG_C_SHIFT     0
 680 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 681
 682 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 683 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 684 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 685 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 686 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 687 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 688 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 689
 690 #ifndef __ASSEMBLY__
 691
 692 /*
 693  * Macros for handling the ISA mode bit for microMIPS.
 694  */
 695 #define get_isa16_mode(x)               ((x) & 0x1)
 696 #define msk_isa16_mode(x)               ((x) & ~0x1)
 697 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
 698
 699 /*
 700  * microMIPS instructions can be 16-bit or 32-bit in length. This
 701  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
 702  */
 703 static inline int mm_insn_16bit(u16 insn)
 704 {
 705         u16 opcode = (insn >> 10) & 0x7;
 706
 707         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
 708 }
 709
 710 /*
 711  * TLB Invalidate Flush
 712  */
 713 static inline void tlbinvf(void)
 714 {
 715         __asm__ __volatile__(
 716                 ".set push\n\t"
 717                 ".set noreorder\n\t"
 718                 ".word 0x42000004\n\t" /* tlbinvf */
 719                 ".set pop");
 720 }
 721
 722
 723 /*
 724  * Functions to access the R10000 performance counters.  These are basically
 725  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 726  * performance counter number encoded into bits 1 ... 5 of the instruction.
 727  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 728  * disassembler these will look like an access to sel 0 or 1.
 729  */
 730 #define read_r10k_perf_cntr(counter)                            \
 731 ({                                                              \
 732         unsigned int __res;                                     \
 733         __asm__ __volatile__(                                   \
 734         "mfpc\t%0, %1"                                          \
 735         : "=r" (__res)                                          \
 736         : "i" (counter));                                       \
 737                                                                 \
 738         __res;                                                  \
 739 })
 740
 741 #define write_r10k_perf_cntr(counter,val)                       \
 742 do {                                                            \
 743         __asm__ __volatile__(                                   \
 744         "mtpc\t%0, %1"                                          \
 745         :                                                       \
 746         : "r" (val), "i" (counter));                            \
 747 } while (0)
 748
 749 #define read_r10k_perf_event(counter)                           \
 750 ({                                                              \
 751         unsigned int __res;                                     \
 752         __asm__ __volatile__(                                   \
 753         "mfps\t%0, %1"                                          \
 754         : "=r" (__res)                                          \
 755         : "i" (counter));                                       \
 756                                                                 \
 757         __res;                                                  \
 758 })
 759
 760 #define write_r10k_perf_cntl(counter,val)                       \
 761 do {                                                            \
 762         __asm__ __volatile__(                                   \
 763         "mtps\t%0, %1"                                          \
 764         :                                                       \
 765         : "r" (val), "i" (counter));                            \
 766 } while (0)
 767
 768
 769 /*
 770  * Macros to access the system control coprocessor
 771  */
 772
 773 #define __read_32bit_c0_register(source, sel)                           \
 774 ({ int __res;                                                           \
 775         if (sel == 0)                                                   \
 776                 __asm__ __volatile__(                                   \
 777                         "mfc0\t%0, " #source "\n\t"                     \
 778                         : "=r" (__res));                                \
 779         else                                                            \
 780                 __asm__ __volatile__(                                   \
 781                         ".set\tmips32\n\t"                              \
 782                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 783                         ".set\tmips0\n\t"                               \
 784                         : "=r" (__res));                                \
 785         __res;                                                          \
 786 })
 787
 788 #define __read_64bit_c0_register(source, sel)                           \
 789 ({ unsigned long long __res;                                            \
 790         if (sizeof(unsigned long) == 4)                                 \
 791                 __res = __read_64bit_c0_split(source, sel);             \
 792         else if (sel == 0)                                              \
 793                 __asm__ __volatile__(                                   \
 794                         ".set\tmips3\n\t"                               \
 795                         "dmfc0\t%0, " #source "\n\t"                    \
 796                         ".set\tmips0"                                   \
 797                         : "=r" (__res));                                \
 798         else                                                            \
 799                 __asm__ __volatile__(                                   \
 800                         ".set\tmips64\n\t"                              \
 801                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
 802                         ".set\tmips0"                                   \
 803                         : "=r" (__res));                                \
 804         __res;                                                          \
 805 })
 806
 807 #define __write_32bit_c0_register(register, sel, value)                 \
 808 do {                                                                    \
 809         if (sel == 0)                                                   \
 810                 __asm__ __volatile__(                                   \
 811                         "mtc0\t%z0, " #register "\n\t"                  \
 812                         : : "Jr" ((unsigned int)(value)));              \
 813         else                                                            \
 814                 __asm__ __volatile__(                                   \
 815                         ".set\tmips32\n\t"                              \
 816                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
 817                         ".set\tmips0"                                   \
 818                         : : "Jr" ((unsigned int)(value)));              \
 819 } while (0)
 820
 821 #define __write_64bit_c0_register(register, sel, value)                 \
 822 do {                                                                    \
 823         if (sizeof(unsigned long) == 4)                                 \
 824                 __write_64bit_c0_split(register, sel, value);           \
 825         else if (sel == 0)                                              \
 826                 __asm__ __volatile__(                                   \
 827                         ".set\tmips3\n\t"                               \
 828                         "dmtc0\t%z0, " #register "\n\t"                 \
 829                         ".set\tmips0"                                   \
 830                         : : "Jr" (value));                              \
 831         else                                                            \
 832                 __asm__ __volatile__(                                   \
 833                         ".set\tmips64\n\t"                              \
 834                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
 835                         ".set\tmips0"                                   \
 836                         : : "Jr" (value));                              \
 837 } while (0)
 838
 839 #define __read_ulong_c0_register(reg, sel)                              \
 840         ((sizeof(unsigned long) == 4) ?                                 \
 841         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
 842         (unsigned long) __read_64bit_c0_register(reg, sel))
 843
 844 #define __write_ulong_c0_register(reg, sel, val)                        \
 845 do {                                                                    \
 846         if (sizeof(unsigned long) == 4)                                 \
 847                 __write_32bit_c0_register(reg, sel, val);               \
 848         else                                                            \
 849                 __write_64bit_c0_register(reg, sel, val);               \
 850 } while (0)
 851
 852 /*
 853  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
 854  */
 855 #define __read_32bit_c0_ctrl_register(source)                           \
 856 ({ int __res;                                                           \
 857         __asm__ __volatile__(                                           \
 858                 "cfc0\t%0, " #source "\n\t"                             \
 859                 : "=r" (__res));                                        \
 860         __res;                                                          \
 861 })
 862
 863 #define __write_32bit_c0_ctrl_register(register, value)                 \
 864 do {                                                                    \
 865         __asm__ __volatile__(                                           \
 866                 "ctc0\t%z0, " #register "\n\t"                          \
 867                 : : "Jr" ((unsigned int)(value)));                      \
 868 } while (0)
 869
 870 /*
 871  * These versions are only needed for systems with more than 38 bits of
 872  * physical address space running the 32-bit kernel.  That's none atm :-)
 873  */
 874 #define __read_64bit_c0_split(source, sel)                              \
 875 ({                                                                      \
 876         unsigned long long __val;                                       \
 877         unsigned long __flags;                                          \
 878                                                                         \
 879         local_irq_save(__flags);                                        \
 880         if (sel == 0)                                                   \
 881                 __asm__ __volatile__(                                   \
 882                         ".set\tmips64\n\t"                              \
 883                         "dmfc0\t%M0, " #source "\n\t"                   \
 884                         "dsll\t%L0, %M0, 32\n\t"                        \
 885                         "dsra\t%M0, %M0, 32\n\t"                        \
 886                         "dsra\t%L0, %L0, 32\n\t"                        \
 887                         ".set\tmips0"                                   \
 888                         : "=r" (__val));                                \
 889         else                                                            \
 890                 __asm__ __volatile__(                                   \
 891                         ".set\tmips64\n\t"                              \
 892                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
 893                         "dsll\t%L0, %M0, 32\n\t"                        \
 894                         "dsra\t%M0, %M0, 32\n\t"                        \
 895                         "dsra\t%L0, %L0, 32\n\t"                        \
 896                         ".set\tmips0"                                   \
 897                         : "=r" (__val));                                \
 898         local_irq_restore(__flags);                                     \
 899                                                                         \
 900         __val;                                                          \
 901 })
 902
 903 #define __write_64bit_c0_split(source, sel, val)                        \
 904 do {                                                                    \
 905         unsigned long __flags;                                          \
 906                                                                         \
 907         local_irq_save(__flags);                                        \
 908         if (sel == 0)                                                   \
 909                 __asm__ __volatile__(                                   \
 910                         ".set\tmips64\n\t"                              \
 911                         "dsll\t%L0, %L0, 32\n\t"                        \
 912                         "dsrl\t%L0, %L0, 32\n\t"                        \
 913                         "dsll\t%M0, %M0, 32\n\t"                        \
 914                         "or\t%L0, %L0, %M0\n\t"                         \
 915                         "dmtc0\t%L0, " #source "\n\t"                   \
 916                         ".set\tmips0"                                   \
 917                         : : "r" (val));                                 \
 918         else                                                            \
 919                 __asm__ __volatile__(                                   \
 920                         ".set\tmips64\n\t"                              \
 921                         "dsll\t%L0, %L0, 32\n\t"                        \
 922                         "dsrl\t%L0, %L0, 32\n\t"                        \
 923                         "dsll\t%M0, %M0, 32\n\t"                        \
 924                         "or\t%L0, %L0, %M0\n\t"                         \
 925                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
 926                         ".set\tmips0"                                   \
 927                         : : "r" (val));                                 \
 928         local_irq_restore(__flags);                                     \
 929 } while (0)
 930
 931 #define read_c0_index()         __read_32bit_c0_register($0, 0)
 932 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
 933
 934 #define read_c0_random()        __read_32bit_c0_register($1, 0)
 935 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
 936
 937 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
 938 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
 939
 940 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
 941 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
 942
 943 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
 944 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
 945
 946 #define read_c0_context()       __read_ulong_c0_register($4, 0)
 947 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
 948
 949 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
 950 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
 951
 952 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
 953 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
 954
 955 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
 956 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
 957
 958 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
 959 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
 960
 961 #define read_c0_info()          __read_32bit_c0_register($7, 0)
 962
 963 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
 964 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
 965
 966 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
 967 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
 968
 969 #define read_c0_count()         __read_32bit_c0_register($9, 0)
 970 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
 971
 972 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
 973 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
 974
 975 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
 976 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
 977
 978 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
 979 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
 980
 981 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
 982 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
 983
 984 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
 985 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
 986
 987 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
 988 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
 989
 990 #define read_c0_status()        __read_32bit_c0_register($12, 0)
 991 #ifdef CONFIG_MIPS_MT_SMTC
 992 #define write_c0_status(val)                                            \
 993 do {                                                                    \
 994         __write_32bit_c0_register($12, 0, val);                         \
 995         __ehb();                                                        \
 996 } while (0)
 997 #else
 998 /*
 999  * Legacy non-SMTC code, which may be hazardous
1000  * but which might not support EHB
1001  */
1002 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1003 #endif /* CONFIG_MIPS_MT_SMTC */
1004
1005 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1006 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1007
1008 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1009 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1010
1011 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1012
1013 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1014 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1015 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1016 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1017 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1018 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1019 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1020 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1021 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1022 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1023 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1024 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1025 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1026 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1027 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1028 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1029
1030 /*
1031  * The WatchLo register.  There may be up to 8 of them.
1032  */
1033 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1034 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1035 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1036 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1037 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1038 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1039 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1040 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1041 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1042 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1043 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1044 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1045 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1046 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1047 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1048 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1049
1050 /*
1051  * The WatchHi register.  There may be up to 8 of them.
1052  */
1053 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1054 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1055 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1056 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1057 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1058 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1059 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1060 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1061
1062 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1063 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1064 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1065 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1066 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1067 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1068 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1069 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1070
1071 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1072 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1073
1074 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1075 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1076
1077 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1078 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1079
1080 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1081 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1082
1083 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1084 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1085
1086 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1087 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1088
1089 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1090 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1091
1092 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1093 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1094
1095 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1096 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1097
1098 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1099 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1100
1101 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1102 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1103
1104 /*
1105  * MIPS32 / MIPS64 performance counters
1106  */
1107 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1108 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1109 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1110 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1111 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1112 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1113 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1114 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1115 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1116 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1117 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1118 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1119 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1120 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1121 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1122 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1123 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1124 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1125 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1126 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1127 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1128 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1129 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1130 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1131
1132 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1133 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1134
1135 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1136 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1137
1138 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1139
1140 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1141 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1142
1143 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1144 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1145
1146 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1147 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1148
1149 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1150 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1151
1152 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1153 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1154
1155 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1156 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1157
1158 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1159 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1160
1161 /* MIPSR2 */
1162 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1163 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1164
1165 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1166 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1167
1168 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1169 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1170
1171 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1172 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1173
1174 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1175 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1176
1177 /* MIPSR3 */
1178 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1179 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1180
1181 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1182 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1183
1184 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1185 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1186
1187 /* Cavium OCTEON (cnMIPS) */
1188 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1189 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1190
1191 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1192 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1193
1194 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1195 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1196 /*
1197  * The cacheerr registers are not standardized.  On OCTEON, they are
1198  * 64 bits wide.
1199  */
1200 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1201 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1202
1203 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1204 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1205
1206 /* BMIPS3300 */
1207 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1208 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1209
1210 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1211 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1212
1213 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1214 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1215
1216 /* BMIPS43xx */
1217 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1218 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1219
1220 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1221 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1222
1223 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1224 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1225
1226 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1227 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1228
1229 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1230 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1231
1232 /* BMIPS5000 */
1233 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1234 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1235
1236 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1237 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1238
1239 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1240 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1241
1242 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1243 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1244
1245 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1246 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1247
1248 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1249 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1250
1251 /*
1252  * Macros to access the floating point coprocessor control registers
1253  */
1254 #define read_32bit_cp1_register(source)                                 \
1255 ({                                                                      \
1256         int __res;                                                      \
1257                                                                         \
1258         __asm__ __volatile__(                                           \
1259         "       .set    push                                    \n"     \
1260         "       .set    reorder                                 \n"     \
1261         "       # gas fails to assemble cfc1 for some archs,    \n"     \
1262         "       # like Octeon.                                  \n"     \
1263         "       .set    mips1                                   \n"     \
1264         "       cfc1    %0,"STR(source)"                        \n"     \
1265         "       .set    pop                                     \n"     \
1266         : "=r" (__res));                                                \
1267         __res;                                                          \
1268 })
1269
1270 #ifdef HAVE_AS_DSP
1271 #define rddsp(mask)                                                     \
1272 ({                                                                      \
1273         unsigned int __dspctl;                                          \
1274                                                                         \
1275         __asm__ __volatile__(                                           \
1276         "       .set push                                       \n"     \
1277         "       .set dsp                                        \n"     \
1278         "       rddsp   %0, %x1                                 \n"     \
1279         "       .set pop                                        \n"     \
1280         : "=r" (__dspctl)                                               \
1281         : "i" (mask));                                                  \
1282         __dspctl;                                                       \
1283 })
1284
1285 #define wrdsp(val, mask)                                                \
1286 do {                                                                    \
1287         __asm__ __volatile__(                                           \
1288         "       .set push                                       \n"     \
1289         "       .set dsp                                        \n"     \
1290         "       wrdsp   %0, %x1                                 \n"     \
1291         "       .set pop                                        \n"     \
1292         :                                                               \
1293         : "r" (val), "i" (mask));                                       \
1294 } while (0)
1295
1296 #define mflo0()                                                         \
1297 ({                                                                      \
1298         long mflo0;                                                     \
1299         __asm__(                                                        \
1300         "       .set push                                       \n"     \
1301         "       .set dsp                                        \n"     \
1302         "       mflo %0, $ac0                                   \n"     \
1303         "       .set pop                                        \n"     \
1304         : "=r" (mflo0));                                                \
1305         mflo0;                                                          \
1306 })
1307
1308 #define mflo1()                                                         \
1309 ({                                                                      \
1310         long mflo1;                                                     \
1311         __asm__(                                                        \
1312         "       .set push                                       \n"     \
1313         "       .set dsp                                        \n"     \
1314         "       mflo %0, $ac1                                   \n"     \
1315         "       .set pop                                        \n"     \
1316         : "=r" (mflo1));                                                \
1317         mflo1;                                                          \
1318 })
1319
1320 #define mflo2()                                                         \
1321 ({                                                                      \
1322         long mflo2;                                                     \
1323         __asm__(                                                        \
1324         "       .set push                                       \n"     \
1325         "       .set dsp                                        \n"     \
1326         "       mflo %0, $ac2                                   \n"     \
1327         "       .set pop                                        \n"     \
1328         : "=r" (mflo2));                                                \
1329         mflo2;                                                          \
1330 })
1331
1332 #define mflo3()                                                         \
1333 ({                                                                      \
1334         long mflo3;                                                     \
1335         __asm__(                                                        \
1336         "       .set push                                       \n"     \
1337         "       .set dsp                                        \n"     \
1338         "       mflo %0, $ac3                                   \n"     \
1339         "       .set pop                                        \n"     \
1340         : "=r" (mflo3));                                                \
1341         mflo3;                                                          \
1342 })
1343
1344 #define mfhi0()                                                         \
1345 ({                                                                      \
1346         long mfhi0;                                                     \
1347         __asm__(                                                        \
1348         "       .set push                                       \n"     \
1349         "       .set dsp                                        \n"     \
1350         "       mfhi %0, $ac0                                   \n"     \
1351         "       .set pop                                        \n"     \
1352         : "=r" (mfhi0));                                                \
1353         mfhi0;                                                          \
1354 })
1355
1356 #define mfhi1()                                                         \
1357 ({                                                                      \
1358         long mfhi1;                                                     \
1359         __asm__(                                                        \
1360         "       .set push                                       \n"     \
1361         "       .set dsp                                        \n"     \
1362         "       mfhi %0, $ac1                                   \n"     \
1363         "       .set pop                                        \n"     \
1364         : "=r" (mfhi1));                                                \
1365         mfhi1;                                                          \
1366 })
1367
1368 #define mfhi2()                                                         \
1369 ({                                                                      \
1370         long mfhi2;                                                     \
1371         __asm__(                                                        \
1372         "       .set push                                       \n"     \
1373         "       .set dsp                                        \n"     \
1374         "       mfhi %0, $ac2                                   \n"     \
1375         "       .set pop                                        \n"     \
1376         : "=r" (mfhi2));                                                \
1377         mfhi2;                                                          \
1378 })
1379
1380 #define mfhi3()                                                         \
1381 ({                                                                      \
1382         long mfhi3;                                                     \
1383         __asm__(                                                        \
1384         "       .set push                                       \n"     \
1385         "       .set dsp                                        \n"     \
1386         "       mfhi %0, $ac3                                   \n"     \
1387         "       .set pop                                        \n"     \
1388         : "=r" (mfhi3));                                                \
1389         mfhi3;                                                          \
1390 })
1391
1392
1393 #define mtlo0(x)                                                        \
1394 ({                                                                      \
1395         __asm__(                                                        \
1396         "       .set push                                       \n"     \
1397         "       .set dsp                                        \n"     \
1398         "       mtlo %0, $ac0                                   \n"     \
1399         "       .set pop                                        \n"     \
1400         :                                                               \
1401         : "r" (x));                                                     \
1402 })
1403
1404 #define mtlo1(x)                                                        \
1405 ({                                                                      \
1406         __asm__(                                                        \
1407         "       .set push                                       \n"     \
1408         "       .set dsp                                        \n"     \
1409         "       mtlo %0, $ac1                                   \n"     \
1410         "       .set pop                                        \n"     \
1411         :                                                               \
1412         : "r" (x));                                                     \
1413 })
1414
1415 #define mtlo2(x)                                                        \
1416 ({                                                                      \
1417         __asm__(                                                        \
1418         "       .set push                                       \n"     \
1419         "       .set dsp                                        \n"     \
1420         "       mtlo %0, $ac2                                   \n"     \
1421         "       .set pop                                        \n"     \
1422         :                                                               \
1423         : "r" (x));                                                     \
1424 })
1425
1426 #define mtlo3(x)                                                        \
1427 ({                                                                      \
1428         __asm__(                                                        \
1429         "       .set push                                       \n"     \
1430         "       .set dsp                                        \n"     \
1431         "       mtlo %0, $ac3                                   \n"     \
1432         "       .set pop                                        \n"     \
1433         :                                                               \
1434         : "r" (x));                                                     \
1435 })
1436
1437 #define mthi0(x)                                                        \
1438 ({                                                                      \
1439         __asm__(                                                        \
1440         "       .set push                                       \n"     \
1441         "       .set dsp                                        \n"     \
1442         "       mthi %0, $ac0                                   \n"     \
1443         "       .set pop                                        \n"     \
1444         :                                                               \
1445         : "r" (x));                                                     \
1446 })
1447
1448 #define mthi1(x)                                                        \
1449 ({                                                                      \
1450         __asm__(                                                        \
1451         "       .set push                                       \n"     \
1452         "       .set dsp                                        \n"     \
1453         "       mthi %0, $ac1                                   \n"     \
1454         "       .set pop                                        \n"     \
1455         :                                                               \
1456         : "r" (x));                                                     \
1457 })
1458
1459 #define mthi2(x)                                                        \
1460 ({                                                                      \
1461         __asm__(                                                        \
1462         "       .set push                                       \n"     \
1463         "       .set dsp                                        \n"     \
1464         "       mthi %0, $ac2                                   \n"     \
1465         "       .set pop                                        \n"     \
1466         :                                                               \
1467         : "r" (x));                                                     \
1468 })
1469
1470 #define mthi3(x)                                                        \
1471 ({                                                                      \
1472         __asm__(                                                        \
1473         "       .set push                                       \n"     \
1474         "       .set dsp                                        \n"     \
1475         "       mthi %0, $ac3                                   \n"     \
1476         "       .set pop                                        \n"     \
1477         :                                                               \
1478         : "r" (x));                                                     \
1479 })
1480
1481 #else
1482
1483 #ifdef CONFIG_CPU_MICROMIPS
1484 #define rddsp(mask)                                                     \
1485 ({                                                                      \
1486         unsigned int __res;                                             \
1487                                                                         \
1488         __asm__ __volatile__(                                           \
1489         "       .set    push                                    \n"     \
1490         "       .set    noat                                    \n"     \
1491         "       # rddsp $1, %x1                                 \n"     \
1492         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
1493         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
1494         "       move    %0, $1                                  \n"     \
1495         "       .set    pop                                     \n"     \
1496         : "=r" (__res)                                                  \
1497         : "i" (mask));                                                  \
1498         __res;                                                          \
1499 })
1500
1501 #define wrdsp(val, mask)                                                \
1502 do {                                                                    \
1503         __asm__ __volatile__(                                           \
1504         "       .set    push                                    \n"     \
1505         "       .set    noat                                    \n"     \
1506         "       move    $1, %0                                  \n"     \
1507         "       # wrdsp $1, %x1                                 \n"     \
1508         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
1509         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
1510         "       .set    pop                                     \n"     \
1511         :                                                               \
1512         : "r" (val), "i" (mask));                                       \
1513 } while (0)
1514
1515 #define _umips_dsp_mfxxx(ins)                                           \
1516 ({                                                                      \
1517         unsigned long __treg;                                           \
1518                                                                         \
1519         __asm__ __volatile__(                                           \
1520         "       .set    push                                    \n"     \
1521         "       .set    noat                                    \n"     \
1522         "       .hword  0x0001                                  \n"     \
1523         "       .hword  %x1                                     \n"     \
1524         "       move    %0, $1                                  \n"     \
1525         "       .set    pop                                     \n"     \
1526         : "=r" (__treg)                                                 \
1527         : "i" (ins));                                                   \
1528         __treg;                                                         \
1529 })
1530
1531 #define _umips_dsp_mtxxx(val, ins)                                      \
1532 do {                                                                    \
1533         __asm__ __volatile__(                                           \
1534         "       .set    push                                    \n"     \
1535         "       .set    noat                                    \n"     \
1536         "       move    $1, %0                                  \n"     \
1537         "       .hword  0x0001                                  \n"     \
1538         "       .hword  %x1                                     \n"     \
1539         "       .set    pop                                     \n"     \
1540         :                                                               \
1541         : "r" (val), "i" (ins));                                        \
1542 } while (0)
1543
1544 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1545 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1546
1547 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1548 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1549
1550 #define mflo0() _umips_dsp_mflo(0)
1551 #define mflo1() _umips_dsp_mflo(1)
1552 #define mflo2() _umips_dsp_mflo(2)
1553 #define mflo3() _umips_dsp_mflo(3)
1554
1555 #define mfhi0() _umips_dsp_mfhi(0)
1556 #define mfhi1() _umips_dsp_mfhi(1)
1557 #define mfhi2() _umips_dsp_mfhi(2)
1558 #define mfhi3() _umips_dsp_mfhi(3)
1559
1560 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1561 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1562 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1563 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1564
1565 #define mthi0(x) _umips_dsp_mthi(x, 0)
1566 #define mthi1(x) _umips_dsp_mthi(x, 1)
1567 #define mthi2(x) _umips_dsp_mthi(x, 2)
1568 #define mthi3(x) _umips_dsp_mthi(x, 3)
1569
1570 #else  /* !CONFIG_CPU_MICROMIPS */
1571 #define rddsp(mask)                                                     \
1572 ({                                                                      \
1573         unsigned int __res;                                             \
1574                                                                         \
1575         __asm__ __volatile__(                                           \
1576         "       .set    push                            \n"             \
1577         "       .set    noat                            \n"             \
1578         "       # rddsp $1, %x1                         \n"             \
1579         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1580         "       move    %0, $1                          \n"             \
1581         "       .set    pop                             \n"             \
1582         : "=r" (__res)                                                  \
1583         : "i" (mask));                                                  \
1584         __res;                                                          \
1585 })
1586
1587 #define wrdsp(val, mask)                                                \
1588 do {                                                                    \
1589         __asm__ __volatile__(                                           \
1590         "       .set    push                                    \n"     \
1591         "       .set    noat                                    \n"     \
1592         "       move    $1, %0                                  \n"     \
1593         "       # wrdsp $1, %x1                                 \n"     \
1594         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1595         "       .set    pop                                     \n"     \
1596         :                                                               \
1597         : "r" (val), "i" (mask));                                       \
1598 } while (0)
1599
1600 #define _dsp_mfxxx(ins)                                                 \
1601 ({                                                                      \
1602         unsigned long __treg;                                           \
1603                                                                         \
1604         __asm__ __volatile__(                                           \
1605         "       .set    push                                    \n"     \
1606         "       .set    noat                                    \n"     \
1607         "       .word   (0x00000810 | %1)                       \n"     \
1608         "       move    %0, $1                                  \n"     \
1609         "       .set    pop                                     \n"     \
1610         : "=r" (__treg)                                                 \
1611         : "i" (ins));                                                   \
1612         __treg;                                                         \
1613 })
1614
1615 #define _dsp_mtxxx(val, ins)                                            \
1616 do {                                                                    \
1617         __asm__ __volatile__(                                           \
1618         "       .set    push                                    \n"     \
1619         "       .set    noat                                    \n"     \
1620         "       move    $1, %0                                  \n"     \
1621         "       .word   (0x00200011 | %1)                       \n"     \
1622         "       .set    pop                                     \n"     \
1623         :                                                               \
1624         : "r" (val), "i" (ins));                                        \
1625 } while (0)
1626
1627 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1628 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1629
1630 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1631 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1632
1633 #define mflo0() _dsp_mflo(0)
1634 #define mflo1() _dsp_mflo(1)
1635 #define mflo2() _dsp_mflo(2)
1636 #define mflo3() _dsp_mflo(3)
1637
1638 #define mfhi0() _dsp_mfhi(0)
1639 #define mfhi1() _dsp_mfhi(1)
1640 #define mfhi2() _dsp_mfhi(2)
1641 #define mfhi3() _dsp_mfhi(3)
1642
1643 #define mtlo0(x) _dsp_mtlo(x, 0)
1644 #define mtlo1(x) _dsp_mtlo(x, 1)
1645 #define mtlo2(x) _dsp_mtlo(x, 2)
1646 #define mtlo3(x) _dsp_mtlo(x, 3)
1647
1648 #define mthi0(x) _dsp_mthi(x, 0)
1649 #define mthi1(x) _dsp_mthi(x, 1)
1650 #define mthi2(x) _dsp_mthi(x, 2)
1651 #define mthi3(x) _dsp_mthi(x, 3)
1652
1653 #endif /* CONFIG_CPU_MICROMIPS */
1654 #endif
1655
1656 /*
1657  * TLB operations.
1658  *
1659  * It is responsibility of the caller to take care of any TLB hazards.
1660  */
1661 static inline void tlb_probe(void)
1662 {
1663         __asm__ __volatile__(
1664                 ".set noreorder\n\t"
1665                 "tlbp\n\t"
1666                 ".set reorder");
1667 }
1668
1669 static inline void tlb_read(void)
1670 {
1671 #if MIPS34K_MISSED_ITLB_WAR
1672         int res = 0;
1673
1674         __asm__ __volatile__(
1675         "       .set    push                                    \n"
1676         "       .set    noreorder                               \n"
1677         "       .set    noat                                    \n"
1678         "       .set    mips32r2                                \n"
1679         "       .word   0x41610001              # dvpe $1       \n"
1680         "       move    %0, $1                                  \n"
1681         "       ehb                                             \n"
1682         "       .set    pop                                     \n"
1683         : "=r" (res));
1684
1685         instruction_hazard();
1686 #endif
1687
1688         __asm__ __volatile__(
1689                 ".set noreorder\n\t"
1690                 "tlbr\n\t"
1691                 ".set reorder");
1692
1693 #if MIPS34K_MISSED_ITLB_WAR
1694         if ((res & _ULCAST_(1)))
1695                 __asm__ __volatile__(
1696                 "       .set    push                            \n"
1697                 "       .set    noreorder                       \n"
1698                 "       .set    noat                            \n"
1699                 "       .set    mips32r2                        \n"
1700                 "       .word   0x41600021      # evpe          \n"
1701                 "       ehb                                     \n"
1702                 "       .set    pop                             \n");
1703 #endif
1704 }
1705
1706 static inline void tlb_write_indexed(void)
1707 {
1708         __asm__ __volatile__(
1709                 ".set noreorder\n\t"
1710                 "tlbwi\n\t"
1711                 ".set reorder");
1712 }
1713
1714 static inline void tlb_write_random(void)
1715 {
1716         __asm__ __volatile__(
1717                 ".set noreorder\n\t"
1718                 "tlbwr\n\t"
1719                 ".set reorder");
1720 }
1721
1722 /*
1723  * Manipulate bits in a c0 register.
1724  */
1725 #ifndef CONFIG_MIPS_MT_SMTC
1726 /*
1727  * SMTC Linux requires shutting-down microthread scheduling
1728  * during CP0 register read-modify-write sequences.
1729  */
1730 #define __BUILD_SET_C0(name)                                    \
1731 static inline unsigned int                                      \
1732 set_c0_##name(unsigned int set)                                 \
1733 {                                                               \
1734         unsigned int res, new;                                  \
1735                                                                 \
1736         res = read_c0_##name();                                 \
1737         new = res | set;                                        \
1738         write_c0_##name(new);                                   \
1739                                                                 \
1740         return res;                                             \
1741 }                                                               \
1742                                                                 \
1743 static inline unsigned int                                      \
1744 clear_c0_##name(unsigned int clear)                             \
1745 {                                                               \
1746         unsigned int res, new;                                  \
1747                                                                 \
1748         res = read_c0_##name();                                 \
1749         new = res & ~clear;                                     \
1750         write_c0_##name(new);                                   \
1751                                                                 \
1752         return res;                                             \
1753 }                                                               \
1754                                                                 \
1755 static inline unsigned int                                      \
1756 change_c0_##name(unsigned int change, unsigned int val)         \
1757 {                                                               \
1758         unsigned int res, new;                                  \
1759                                                                 \
1760         res = read_c0_##name();                                 \
1761         new = res & ~change;                                    \
1762         new |= (val & change);                                  \
1763         write_c0_##name(new);                                   \
1764                                                                 \
1765         return res;                                             \
1766 }
1767
1768 #else /* SMTC versions that manage MT scheduling */
1769
1770 #include <linux/irqflags.h>
1771
1772 /*
1773  * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1774  * header file recursion.
1775  */
1776 static inline unsigned int __dmt(void)
1777 {
1778         int res;
1779
1780         __asm__ __volatile__(
1781         "       .set    push                                            \n"
1782         "       .set    mips32r2                                        \n"
1783         "       .set    noat                                            \n"
1784         "       .word   0x41610BC1                      # dmt $1        \n"
1785         "       ehb                                                     \n"
1786         "       move    %0, $1                                          \n"
1787         "       .set    pop                                             \n"
1788         : "=r" (res));
1789
1790         instruction_hazard();
1791
1792         return res;
1793 }
1794
1795 #define __VPECONTROL_TE_SHIFT   15
1796 #define __VPECONTROL_TE         (1UL << __VPECONTROL_TE_SHIFT)
1797
1798 #define __EMT_ENABLE            __VPECONTROL_TE
1799
1800 static inline void __emt(unsigned int previous)
1801 {
1802         if ((previous & __EMT_ENABLE))
1803                 __asm__ __volatile__(
1804                 "       .set    mips32r2                                \n"
1805                 "       .word   0x41600be1              # emt           \n"
1806                 "       ehb                                             \n"
1807                 "       .set    mips0                                   \n");
1808 }
1809
1810 static inline void __ehb(void)
1811 {
1812         __asm__ __volatile__(
1813         "       .set    mips32r2                                        \n"
1814         "       ehb                                                     \n"             "       .set    mips0                                           \n");
1815 }
1816
1817 /*
1818  * Note that local_irq_save/restore affect TC-specific IXMT state,
1819  * not Status.IE as in non-SMTC kernel.
1820  */
1821
1822 #define __BUILD_SET_C0(name)                                    \
1823 static inline unsigned int                                      \
1824 set_c0_##name(unsigned int set)                                 \
1825 {                                                               \
1826         unsigned int res;                                       \
1827         unsigned int new;                                       \
1828         unsigned int omt;                                       \
1829         unsigned long flags;                                    \
1830                                                                 \
1831         local_irq_save(flags);                                  \
1832         omt = __dmt();                                          \
1833         res = read_c0_##name();                                 \
1834         new = res | set;                                        \
1835         write_c0_##name(new);                                   \
1836         __emt(omt);                                             \
1837         local_irq_restore(flags);                               \
1838                                                                 \
1839         return res;                                             \
1840 }                                                               \
1841                                                                 \
1842 static inline unsigned int                                      \
1843 clear_c0_##name(unsigned int clear)                             \
1844 {                                                               \
1845         unsigned int res;                                       \
1846         unsigned int new;                                       \
1847         unsigned int omt;                                       \
1848         unsigned long flags;                                    \
1849                                                                 \
1850         local_irq_save(flags);                                  \
1851         omt = __dmt();                                          \
1852         res = read_c0_##name();                                 \
1853         new = res & ~clear;                                     \
1854         write_c0_##name(new);                                   \
1855         __emt(omt);                                             \
1856         local_irq_restore(flags);                               \
1857                                                                 \
1858         return res;                                             \
1859 }                                                               \
1860                                                                 \
1861 static inline unsigned int                                      \
1862 change_c0_##name(unsigned int change, unsigned int newbits)     \
1863 {                                                               \
1864         unsigned int res;                                       \
1865         unsigned int new;                                       \
1866         unsigned int omt;                                       \
1867         unsigned long flags;                                    \
1868                                                                 \
1869         local_irq_save(flags);                                  \
1870                                                                 \
1871         omt = __dmt();                                          \
1872         res = read_c0_##name();                                 \
1873         new = res & ~change;                                    \
1874         new |= (newbits & change);                              \
1875         write_c0_##name(new);                                   \
1876         __emt(omt);                                             \
1877         local_irq_restore(flags);                               \
1878                                                                 \
1879         return res;                                             \
1880 }
1881 #endif
1882
1883 __BUILD_SET_C0(status)
1884 __BUILD_SET_C0(cause)
1885 __BUILD_SET_C0(config)
1886 __BUILD_SET_C0(intcontrol)
1887 __BUILD_SET_C0(intctl)
1888 __BUILD_SET_C0(srsmap)
1889 __BUILD_SET_C0(brcm_config_0)
1890 __BUILD_SET_C0(brcm_bus_pll)
1891 __BUILD_SET_C0(brcm_reset)
1892 __BUILD_SET_C0(brcm_cmt_intr)
1893 __BUILD_SET_C0(brcm_cmt_ctrl)
1894 __BUILD_SET_C0(brcm_config)
1895 __BUILD_SET_C0(brcm_mode)
1896
1897 #endif /* !__ASSEMBLY__ */
1898
1899 #endif /* _ASM_MIPSREGS_H */