2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
16 #include <linux/linkage.h>
17 #include <linux/types.h>
18 #include <asm/hazards.h>
22 * The following macros are especially useful for __asm__
29 #define STR(x) __STR(x)
38 #define _ULCAST_ (unsigned long)
42 * Coprocessor 0 register names
46 #define CP0_ENTRYLO0 $2
47 #define CP0_ENTRYLO1 $3
49 #define CP0_CONTEXT $4
50 #define CP0_PAGEMASK $5
53 #define CP0_BADVADDR $8
55 #define CP0_ENTRYHI $10
56 #define CP0_COMPARE $11
57 #define CP0_STATUS $12
61 #define CP0_CONFIG $16
62 #define CP0_LLADDR $17
63 #define CP0_WATCHLO $18
64 #define CP0_WATCHHI $19
65 #define CP0_XCONTEXT $20
66 #define CP0_FRAMEMASK $21
67 #define CP0_DIAGNOSTIC $22
70 #define CP0_PERFORMANCE $25
72 #define CP0_CACHEERR $27
75 #define CP0_ERROREPC $30
76 #define CP0_DESAVE $31
79 * R4640/R4650 cp0 register names. These registers are listed
80 * here only for completeness; without MMU these CPUs are not useable
81 * by Linux. A future ELKS port might take make Linux run on them
89 #define CP0_IWATCH $18
90 #define CP0_DWATCH $19
93 * Coprocessor 0 Set 1 register names
95 #define CP0_S1_DERRADDR0 $26
96 #define CP0_S1_DERRADDR1 $27
97 #define CP0_S1_INTCONTROL $20
100 * Coprocessor 0 Set 2 register names
102 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
105 * Coprocessor 0 Set 3 register names
107 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
112 #define CP0_TX39_CACHE $7
116 * Values for PageMask register
118 #ifdef CONFIG_CPU_VR41XX
120 /* Why doesn't stupidity hurt ... */
122 #define PM_1K 0x00000000
123 #define PM_4K 0x00001800
124 #define PM_16K 0x00007800
125 #define PM_64K 0x0001f800
126 #define PM_256K 0x0007f800
130 #define PM_4K 0x00000000
131 #define PM_8K 0x00002000
132 #define PM_16K 0x00006000
133 #define PM_32K 0x0000e000
134 #define PM_64K 0x0001e000
135 #define PM_128K 0x0003e000
136 #define PM_256K 0x0007e000
137 #define PM_512K 0x000fe000
138 #define PM_1M 0x001fe000
139 #define PM_2M 0x003fe000
140 #define PM_4M 0x007fe000
141 #define PM_8M 0x00ffe000
142 #define PM_16M 0x01ffe000
143 #define PM_32M 0x03ffe000
144 #define PM_64M 0x07ffe000
145 #define PM_256M 0x1fffe000
146 #define PM_1G 0x7fffe000
151 * Default page size for a given kernel configuration
153 #ifdef CONFIG_PAGE_SIZE_4KB
154 #define PM_DEFAULT_MASK PM_4K
155 #elif defined(CONFIG_PAGE_SIZE_8KB)
156 #define PM_DEFAULT_MASK PM_8K
157 #elif defined(CONFIG_PAGE_SIZE_16KB)
158 #define PM_DEFAULT_MASK PM_16K
159 #elif defined(CONFIG_PAGE_SIZE_32KB)
160 #define PM_DEFAULT_MASK PM_32K
161 #elif defined(CONFIG_PAGE_SIZE_64KB)
162 #define PM_DEFAULT_MASK PM_64K
164 #error Bad page size configuration!
168 * Default huge tlb size for a given kernel configuration
170 #ifdef CONFIG_PAGE_SIZE_4KB
171 #define PM_HUGE_MASK PM_1M
172 #elif defined(CONFIG_PAGE_SIZE_8KB)
173 #define PM_HUGE_MASK PM_4M
174 #elif defined(CONFIG_PAGE_SIZE_16KB)
175 #define PM_HUGE_MASK PM_16M
176 #elif defined(CONFIG_PAGE_SIZE_32KB)
177 #define PM_HUGE_MASK PM_64M
178 #elif defined(CONFIG_PAGE_SIZE_64KB)
179 #define PM_HUGE_MASK PM_256M
180 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
181 #error Bad page size configuration for hugetlbfs!
185 * Values used for computation of new tlb entries
200 #define PG_RIE (_ULCAST_(1) << 31)
201 #define PG_XIE (_ULCAST_(1) << 30)
202 #define PG_ELPA (_ULCAST_(1) << 29)
203 #define PG_ESP (_ULCAST_(1) << 28)
204 #define PG_IEC (_ULCAST_(1) << 27)
207 * R4x00 interrupt enable / cause bits
209 #define IE_SW0 (_ULCAST_(1) << 8)
210 #define IE_SW1 (_ULCAST_(1) << 9)
211 #define IE_IRQ0 (_ULCAST_(1) << 10)
212 #define IE_IRQ1 (_ULCAST_(1) << 11)
213 #define IE_IRQ2 (_ULCAST_(1) << 12)
214 #define IE_IRQ3 (_ULCAST_(1) << 13)
215 #define IE_IRQ4 (_ULCAST_(1) << 14)
216 #define IE_IRQ5 (_ULCAST_(1) << 15)
219 * R4x00 interrupt cause bits
221 #define C_SW0 (_ULCAST_(1) << 8)
222 #define C_SW1 (_ULCAST_(1) << 9)
223 #define C_IRQ0 (_ULCAST_(1) << 10)
224 #define C_IRQ1 (_ULCAST_(1) << 11)
225 #define C_IRQ2 (_ULCAST_(1) << 12)
226 #define C_IRQ3 (_ULCAST_(1) << 13)
227 #define C_IRQ4 (_ULCAST_(1) << 14)
228 #define C_IRQ5 (_ULCAST_(1) << 15)
231 * Bitfields in the R4xx0 cp0 status register
233 #define ST0_IE 0x00000001
234 #define ST0_EXL 0x00000002
235 #define ST0_ERL 0x00000004
236 #define ST0_KSU 0x00000018
237 # define KSU_USER 0x00000010
238 # define KSU_SUPERVISOR 0x00000008
239 # define KSU_KERNEL 0x00000000
240 #define ST0_UX 0x00000020
241 #define ST0_SX 0x00000040
242 #define ST0_KX 0x00000080
243 #define ST0_DE 0x00010000
244 #define ST0_CE 0x00020000
247 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
248 * cacheops in userspace. This bit exists only on RM7000 and RM9000
251 #define ST0_CO 0x08000000
254 * Bitfields in the R[23]000 cp0 status register.
256 #define ST0_IEC 0x00000001
257 #define ST0_KUC 0x00000002
258 #define ST0_IEP 0x00000004
259 #define ST0_KUP 0x00000008
260 #define ST0_IEO 0x00000010
261 #define ST0_KUO 0x00000020
262 /* bits 6 & 7 are reserved on R[23]000 */
263 #define ST0_ISC 0x00010000
264 #define ST0_SWC 0x00020000
265 #define ST0_CM 0x00080000
268 * Bits specific to the R4640/R4650
270 #define ST0_UM (_ULCAST_(1) << 4)
271 #define ST0_IL (_ULCAST_(1) << 23)
272 #define ST0_DL (_ULCAST_(1) << 24)
275 * Enable the MIPS MDMX and DSP ASEs
277 #define ST0_MX 0x01000000
280 * Status register bits available in all MIPS CPUs.
282 #define ST0_IM 0x0000ff00
283 #define STATUSB_IP0 8
284 #define STATUSF_IP0 (_ULCAST_(1) << 8)
285 #define STATUSB_IP1 9
286 #define STATUSF_IP1 (_ULCAST_(1) << 9)
287 #define STATUSB_IP2 10
288 #define STATUSF_IP2 (_ULCAST_(1) << 10)
289 #define STATUSB_IP3 11
290 #define STATUSF_IP3 (_ULCAST_(1) << 11)
291 #define STATUSB_IP4 12
292 #define STATUSF_IP4 (_ULCAST_(1) << 12)
293 #define STATUSB_IP5 13
294 #define STATUSF_IP5 (_ULCAST_(1) << 13)
295 #define STATUSB_IP6 14
296 #define STATUSF_IP6 (_ULCAST_(1) << 14)
297 #define STATUSB_IP7 15
298 #define STATUSF_IP7 (_ULCAST_(1) << 15)
299 #define STATUSB_IP8 0
300 #define STATUSF_IP8 (_ULCAST_(1) << 0)
301 #define STATUSB_IP9 1
302 #define STATUSF_IP9 (_ULCAST_(1) << 1)
303 #define STATUSB_IP10 2
304 #define STATUSF_IP10 (_ULCAST_(1) << 2)
305 #define STATUSB_IP11 3
306 #define STATUSF_IP11 (_ULCAST_(1) << 3)
307 #define STATUSB_IP12 4
308 #define STATUSF_IP12 (_ULCAST_(1) << 4)
309 #define STATUSB_IP13 5
310 #define STATUSF_IP13 (_ULCAST_(1) << 5)
311 #define STATUSB_IP14 6
312 #define STATUSF_IP14 (_ULCAST_(1) << 6)
313 #define STATUSB_IP15 7
314 #define STATUSF_IP15 (_ULCAST_(1) << 7)
315 #define ST0_CH 0x00040000
316 #define ST0_NMI 0x00080000
317 #define ST0_SR 0x00100000
318 #define ST0_TS 0x00200000
319 #define ST0_BEV 0x00400000
320 #define ST0_RE 0x02000000
321 #define ST0_FR 0x04000000
322 #define ST0_CU 0xf0000000
323 #define ST0_CU0 0x10000000
324 #define ST0_CU1 0x20000000
325 #define ST0_CU2 0x40000000
326 #define ST0_CU3 0x80000000
327 #define ST0_XX 0x80000000 /* MIPS IV naming */
330 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
332 #define INTCTLB_IPFDC 23
333 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
334 #define INTCTLB_IPPCI 26
335 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
336 #define INTCTLB_IPTI 29
337 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
340 * Bitfields and bit numbers in the coprocessor 0 cause register.
342 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
344 #define CAUSEB_EXCCODE 2
345 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
347 #define CAUSEF_IP (_ULCAST_(255) << 8)
349 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
351 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
352 #define CAUSEB_IP2 10
353 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
354 #define CAUSEB_IP3 11
355 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
356 #define CAUSEB_IP4 12
357 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
358 #define CAUSEB_IP5 13
359 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
360 #define CAUSEB_IP6 14
361 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
362 #define CAUSEB_IP7 15
363 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
364 #define CAUSEB_FDCI 21
365 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
367 #define CAUSEF_IV (_ULCAST_(1) << 23)
368 #define CAUSEB_PCI 26
369 #define CAUSEF_PCI (_ULCAST_(1) << 26)
371 #define CAUSEF_CE (_ULCAST_(3) << 28)
373 #define CAUSEF_TI (_ULCAST_(1) << 30)
375 #define CAUSEF_BD (_ULCAST_(1) << 31)
378 * Bits in the coprocessor 0 config register.
381 #define CONF_CM_CACHABLE_NO_WA 0
382 #define CONF_CM_CACHABLE_WA 1
383 #define CONF_CM_UNCACHED 2
384 #define CONF_CM_CACHABLE_NONCOHERENT 3
385 #define CONF_CM_CACHABLE_CE 4
386 #define CONF_CM_CACHABLE_COW 5
387 #define CONF_CM_CACHABLE_CUW 6
388 #define CONF_CM_CACHABLE_ACCELERATED 7
389 #define CONF_CM_CMASK 7
390 #define CONF_BE (_ULCAST_(1) << 15)
392 /* Bits common to various processors. */
393 #define CONF_CU (_ULCAST_(1) << 3)
394 #define CONF_DB (_ULCAST_(1) << 4)
395 #define CONF_IB (_ULCAST_(1) << 5)
396 #define CONF_DC (_ULCAST_(7) << 6)
397 #define CONF_IC (_ULCAST_(7) << 9)
398 #define CONF_EB (_ULCAST_(1) << 13)
399 #define CONF_EM (_ULCAST_(1) << 14)
400 #define CONF_SM (_ULCAST_(1) << 16)
401 #define CONF_SC (_ULCAST_(1) << 17)
402 #define CONF_EW (_ULCAST_(3) << 18)
403 #define CONF_EP (_ULCAST_(15)<< 24)
404 #define CONF_EC (_ULCAST_(7) << 28)
405 #define CONF_CM (_ULCAST_(1) << 31)
407 /* Bits specific to the R4xx0. */
408 #define R4K_CONF_SW (_ULCAST_(1) << 20)
409 #define R4K_CONF_SS (_ULCAST_(1) << 21)
410 #define R4K_CONF_SB (_ULCAST_(3) << 22)
412 /* Bits specific to the R5000. */
413 #define R5K_CONF_SE (_ULCAST_(1) << 12)
414 #define R5K_CONF_SS (_ULCAST_(3) << 20)
416 /* Bits specific to the RM7000. */
417 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
418 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
419 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
420 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
421 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
422 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
424 /* Bits specific to the R10000. */
425 #define R10K_CONF_DN (_ULCAST_(3) << 3)
426 #define R10K_CONF_CT (_ULCAST_(1) << 5)
427 #define R10K_CONF_PE (_ULCAST_(1) << 6)
428 #define R10K_CONF_PM (_ULCAST_(3) << 7)
429 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
430 #define R10K_CONF_SB (_ULCAST_(1) << 13)
431 #define R10K_CONF_SK (_ULCAST_(1) << 14)
432 #define R10K_CONF_SS (_ULCAST_(7) << 16)
433 #define R10K_CONF_SC (_ULCAST_(7) << 19)
434 #define R10K_CONF_DC (_ULCAST_(7) << 26)
435 #define R10K_CONF_IC (_ULCAST_(7) << 29)
437 /* Bits specific to the VR41xx. */
438 #define VR41_CONF_CS (_ULCAST_(1) << 12)
439 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
440 #define VR41_CONF_BP (_ULCAST_(1) << 16)
441 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
442 #define VR41_CONF_AD (_ULCAST_(1) << 23)
444 /* Bits specific to the R30xx. */
445 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
446 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
447 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
448 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
449 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
450 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
451 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
452 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
453 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
455 /* Bits specific to the TX49. */
456 #define TX49_CONF_DC (_ULCAST_(1) << 16)
457 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
458 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
459 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
461 /* Bits specific to the MIPS32/64 PRA. */
462 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
463 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
464 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
465 #define MIPS_CONF_M (_ULCAST_(1) << 31)
468 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
470 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
471 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
472 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
473 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
474 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
475 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
476 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
477 #define MIPS_CONF1_DA_SHF 7
478 #define MIPS_CONF1_DA_SZ 3
479 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
480 #define MIPS_CONF1_DL_SHF 10
481 #define MIPS_CONF1_DL_SZ 3
482 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
483 #define MIPS_CONF1_DS_SHF 13
484 #define MIPS_CONF1_DS_SZ 3
485 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
486 #define MIPS_CONF1_IA_SHF 16
487 #define MIPS_CONF1_IA_SZ 3
488 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
489 #define MIPS_CONF1_IL_SHF 19
490 #define MIPS_CONF1_IL_SZ 3
491 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
492 #define MIPS_CONF1_IS_SHF 22
493 #define MIPS_CONF1_IS_SZ 3
494 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
495 #define MIPS_CONF1_TLBS_SHIFT (25)
496 #define MIPS_CONF1_TLBS_SIZE (6)
497 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
499 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
500 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
501 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
502 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
503 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
504 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
505 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
506 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
508 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
509 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
510 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
511 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
512 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
513 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
514 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
515 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
516 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
517 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
518 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
519 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
520 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
521 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
522 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
523 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
524 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
525 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
526 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
527 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
528 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
529 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
530 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
531 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
532 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
533 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
534 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
536 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
537 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
538 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
539 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
540 #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
541 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
542 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
543 /* bits 10:8 in FTLB-only configurations */
544 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
545 /* bits 12:8 in VTLB-FTLB only configurations */
546 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
547 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
548 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
549 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
550 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
551 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
552 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
553 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
554 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
555 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
556 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
558 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
559 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
560 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
561 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
562 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
563 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
564 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
565 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
566 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
567 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
568 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
570 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
571 /* proAptiv FTLB on/off bit */
572 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
573 /* FTLB probability bits */
574 #define MIPS_CONF6_FTLBP_SHIFT (16)
576 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
578 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
580 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
581 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
583 /* MAAR bit definitions */
584 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
585 #define MIPS_MAAR_ADDR_SHIFT 12
586 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
587 #define MIPS_MAAR_V (_ULCAST_(1) << 0)
589 /* EntryHI bit definition */
590 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
592 /* R3000 EntryLo bit definitions */
593 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
594 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
595 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
596 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
598 /* R4000 compatible EntryLo bit definitions */
599 #define MIPS_ENTRYLO_G (_ULCAST_(1) << 0)
600 #define MIPS_ENTRYLO_V (_ULCAST_(1) << 1)
601 #define MIPS_ENTRYLO_D (_ULCAST_(1) << 2)
602 #define MIPS_ENTRYLO_C_SHIFT 3
603 #define MIPS_ENTRYLO_C (_ULCAST_(7) << MIPS_ENTRYLO_C_SHIFT)
605 /* as read by dmfc0 */
606 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << 62)
607 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << 63)
609 /* as read by mfc0 */
610 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << 30)
611 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << 31)
614 /* CMGCRBase bit definitions */
615 #define MIPS_CMGCRB_BASE 11
616 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
619 * Bits in the MIPS32 Memory Segmentation registers.
621 #define MIPS_SEGCFG_PA_SHIFT 9
622 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
623 #define MIPS_SEGCFG_AM_SHIFT 4
624 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
625 #define MIPS_SEGCFG_EU_SHIFT 3
626 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
627 #define MIPS_SEGCFG_C_SHIFT 0
628 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
630 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
631 #define MIPS_SEGCFG_USK _ULCAST_(5)
632 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
633 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
634 #define MIPS_SEGCFG_MSK _ULCAST_(2)
635 #define MIPS_SEGCFG_MK _ULCAST_(1)
636 #define MIPS_SEGCFG_UK _ULCAST_(0)
638 #define MIPS_PWFIELD_GDI_SHIFT 24
639 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
640 #define MIPS_PWFIELD_UDI_SHIFT 18
641 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
642 #define MIPS_PWFIELD_MDI_SHIFT 12
643 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
644 #define MIPS_PWFIELD_PTI_SHIFT 6
645 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
646 #define MIPS_PWFIELD_PTEI_SHIFT 0
647 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
649 #define MIPS_PWSIZE_GDW_SHIFT 24
650 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
651 #define MIPS_PWSIZE_UDW_SHIFT 18
652 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
653 #define MIPS_PWSIZE_MDW_SHIFT 12
654 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
655 #define MIPS_PWSIZE_PTW_SHIFT 6
656 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
657 #define MIPS_PWSIZE_PTEW_SHIFT 0
658 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
660 #define MIPS_PWCTL_PWEN_SHIFT 31
661 #define MIPS_PWCTL_PWEN_MASK 0x80000000
662 #define MIPS_PWCTL_DPH_SHIFT 7
663 #define MIPS_PWCTL_DPH_MASK 0x00000080
664 #define MIPS_PWCTL_HUGEPG_SHIFT 6
665 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
666 #define MIPS_PWCTL_PSN_SHIFT 0
667 #define MIPS_PWCTL_PSN_MASK 0x0000003f
669 /* CDMMBase register bit definitions */
670 #define MIPS_CDMMBASE_SIZE_SHIFT 0
671 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
672 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
673 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
674 #define MIPS_CDMMBASE_ADDR_SHIFT 11
675 #define MIPS_CDMMBASE_ADDR_START 15
678 * Bitfields in the TX39 family CP0 Configuration Register 3
680 #define TX39_CONF_ICS_SHIFT 19
681 #define TX39_CONF_ICS_MASK 0x00380000
682 #define TX39_CONF_ICS_1KB 0x00000000
683 #define TX39_CONF_ICS_2KB 0x00080000
684 #define TX39_CONF_ICS_4KB 0x00100000
685 #define TX39_CONF_ICS_8KB 0x00180000
686 #define TX39_CONF_ICS_16KB 0x00200000
688 #define TX39_CONF_DCS_SHIFT 16
689 #define TX39_CONF_DCS_MASK 0x00070000
690 #define TX39_CONF_DCS_1KB 0x00000000
691 #define TX39_CONF_DCS_2KB 0x00010000
692 #define TX39_CONF_DCS_4KB 0x00020000
693 #define TX39_CONF_DCS_8KB 0x00030000
694 #define TX39_CONF_DCS_16KB 0x00040000
696 #define TX39_CONF_CWFON 0x00004000
697 #define TX39_CONF_WBON 0x00002000
698 #define TX39_CONF_RF_SHIFT 10
699 #define TX39_CONF_RF_MASK 0x00000c00
700 #define TX39_CONF_DOZE 0x00000200
701 #define TX39_CONF_HALT 0x00000100
702 #define TX39_CONF_LOCK 0x00000080
703 #define TX39_CONF_ICE 0x00000020
704 #define TX39_CONF_DCE 0x00000010
705 #define TX39_CONF_IRSIZE_SHIFT 2
706 #define TX39_CONF_IRSIZE_MASK 0x0000000c
707 #define TX39_CONF_DRSIZE_SHIFT 0
708 #define TX39_CONF_DRSIZE_MASK 0x00000003
711 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
713 /* Disable Branch Target Address Cache */
714 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
715 /* Enable Branch Prediction Global History */
716 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
717 /* Disable Branch Return Cache */
718 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
721 * Coprocessor 1 (FPU) register names
723 #define CP1_REVISION $0
729 #define CP1_STATUS $31
733 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
735 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
736 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
737 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
738 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
739 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
740 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
741 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
742 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
743 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
744 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
747 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
749 #define MIPS_FCCR_CONDX_S 0
750 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
751 #define MIPS_FCCR_COND0_S 0
752 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
753 #define MIPS_FCCR_COND1_S 1
754 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
755 #define MIPS_FCCR_COND2_S 2
756 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
757 #define MIPS_FCCR_COND3_S 3
758 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
759 #define MIPS_FCCR_COND4_S 4
760 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
761 #define MIPS_FCCR_COND5_S 5
762 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
763 #define MIPS_FCCR_COND6_S 6
764 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
765 #define MIPS_FCCR_COND7_S 7
766 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
769 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
771 #define MIPS_FENR_FS_S 2
772 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
775 * FPU Status Register Values
777 #define FPU_CSR_COND_S 23 /* $fcc0 */
778 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
780 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
781 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
783 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
784 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
785 #define FPU_CSR_COND1_S 25 /* $fcc1 */
786 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
787 #define FPU_CSR_COND2_S 26 /* $fcc2 */
788 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
789 #define FPU_CSR_COND3_S 27 /* $fcc3 */
790 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
791 #define FPU_CSR_COND4_S 28 /* $fcc4 */
792 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
793 #define FPU_CSR_COND5_S 29 /* $fcc5 */
794 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
795 #define FPU_CSR_COND6_S 30 /* $fcc6 */
796 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
797 #define FPU_CSR_COND7_S 31 /* $fcc7 */
798 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
801 * Bits 22:20 of the FPU Status Register will be read as 0,
802 * and should be written as zero.
804 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
806 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
807 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
810 * X the exception cause indicator
811 * E the exception enable
812 * S the sticky/flag bit
814 #define FPU_CSR_ALL_X 0x0003f000
815 #define FPU_CSR_UNI_X 0x00020000
816 #define FPU_CSR_INV_X 0x00010000
817 #define FPU_CSR_DIV_X 0x00008000
818 #define FPU_CSR_OVF_X 0x00004000
819 #define FPU_CSR_UDF_X 0x00002000
820 #define FPU_CSR_INE_X 0x00001000
822 #define FPU_CSR_ALL_E 0x00000f80
823 #define FPU_CSR_INV_E 0x00000800
824 #define FPU_CSR_DIV_E 0x00000400
825 #define FPU_CSR_OVF_E 0x00000200
826 #define FPU_CSR_UDF_E 0x00000100
827 #define FPU_CSR_INE_E 0x00000080
829 #define FPU_CSR_ALL_S 0x0000007c
830 #define FPU_CSR_INV_S 0x00000040
831 #define FPU_CSR_DIV_S 0x00000020
832 #define FPU_CSR_OVF_S 0x00000010
833 #define FPU_CSR_UDF_S 0x00000008
834 #define FPU_CSR_INE_S 0x00000004
836 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
837 #define FPU_CSR_RM 0x00000003
838 #define FPU_CSR_RN 0x0 /* nearest */
839 #define FPU_CSR_RZ 0x1 /* towards zero */
840 #define FPU_CSR_RU 0x2 /* towards +Infinity */
841 #define FPU_CSR_RD 0x3 /* towards -Infinity */
847 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
849 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
850 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
851 #define get_isa16_mode(x) ((x) & 0x1)
852 #define msk_isa16_mode(x) ((x) & ~0x1)
853 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
855 #define get_isa16_mode(x) 0
856 #define msk_isa16_mode(x) (x)
857 #define set_isa16_mode(x) do { } while(0)
861 * microMIPS instructions can be 16-bit or 32-bit in length. This
862 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
864 static inline int mm_insn_16bit(u16 insn)
866 u16 opcode = (insn >> 10) & 0x7;
868 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
872 * TLB Invalidate Flush
874 static inline void tlbinvf(void)
876 __asm__ __volatile__(
879 ".word 0x42000004\n\t" /* tlbinvf */
885 * Functions to access the R10000 performance counters. These are basically
886 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
887 * performance counter number encoded into bits 1 ... 5 of the instruction.
888 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
889 * disassembler these will look like an access to sel 0 or 1.
891 #define read_r10k_perf_cntr(counter) \
893 unsigned int __res; \
894 __asm__ __volatile__( \
902 #define write_r10k_perf_cntr(counter,val) \
904 __asm__ __volatile__( \
907 : "r" (val), "i" (counter)); \
910 #define read_r10k_perf_event(counter) \
912 unsigned int __res; \
913 __asm__ __volatile__( \
921 #define write_r10k_perf_cntl(counter,val) \
923 __asm__ __volatile__( \
926 : "r" (val), "i" (counter)); \
931 * Macros to access the system control coprocessor
934 #define __read_32bit_c0_register(source, sel) \
937 __asm__ __volatile__( \
938 "mfc0\t%0, " #source "\n\t" \
941 __asm__ __volatile__( \
943 "mfc0\t%0, " #source ", " #sel "\n\t" \
949 #define __read_64bit_c0_register(source, sel) \
950 ({ unsigned long long __res; \
951 if (sizeof(unsigned long) == 4) \
952 __res = __read_64bit_c0_split(source, sel); \
954 __asm__ __volatile__( \
956 "dmfc0\t%0, " #source "\n\t" \
960 __asm__ __volatile__( \
962 "dmfc0\t%0, " #source ", " #sel "\n\t" \
968 #define __write_32bit_c0_register(register, sel, value) \
971 __asm__ __volatile__( \
972 "mtc0\t%z0, " #register "\n\t" \
973 : : "Jr" ((unsigned int)(value))); \
975 __asm__ __volatile__( \
977 "mtc0\t%z0, " #register ", " #sel "\n\t" \
979 : : "Jr" ((unsigned int)(value))); \
982 #define __write_64bit_c0_register(register, sel, value) \
984 if (sizeof(unsigned long) == 4) \
985 __write_64bit_c0_split(register, sel, value); \
987 __asm__ __volatile__( \
989 "dmtc0\t%z0, " #register "\n\t" \
993 __asm__ __volatile__( \
995 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1000 #define __read_ulong_c0_register(reg, sel) \
1001 ((sizeof(unsigned long) == 4) ? \
1002 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1003 (unsigned long) __read_64bit_c0_register(reg, sel))
1005 #define __write_ulong_c0_register(reg, sel, val) \
1007 if (sizeof(unsigned long) == 4) \
1008 __write_32bit_c0_register(reg, sel, val); \
1010 __write_64bit_c0_register(reg, sel, val); \
1014 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1016 #define __read_32bit_c0_ctrl_register(source) \
1018 __asm__ __volatile__( \
1019 "cfc0\t%0, " #source "\n\t" \
1024 #define __write_32bit_c0_ctrl_register(register, value) \
1026 __asm__ __volatile__( \
1027 "ctc0\t%z0, " #register "\n\t" \
1028 : : "Jr" ((unsigned int)(value))); \
1032 * These versions are only needed for systems with more than 38 bits of
1033 * physical address space running the 32-bit kernel. That's none atm :-)
1035 #define __read_64bit_c0_split(source, sel) \
1037 unsigned long long __val; \
1038 unsigned long __flags; \
1040 local_irq_save(__flags); \
1042 __asm__ __volatile__( \
1043 ".set\tmips64\n\t" \
1044 "dmfc0\t%M0, " #source "\n\t" \
1045 "dsll\t%L0, %M0, 32\n\t" \
1046 "dsra\t%M0, %M0, 32\n\t" \
1047 "dsra\t%L0, %L0, 32\n\t" \
1051 __asm__ __volatile__( \
1052 ".set\tmips64\n\t" \
1053 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
1054 "dsll\t%L0, %M0, 32\n\t" \
1055 "dsra\t%M0, %M0, 32\n\t" \
1056 "dsra\t%L0, %L0, 32\n\t" \
1059 local_irq_restore(__flags); \
1064 #define __write_64bit_c0_split(source, sel, val) \
1066 unsigned long __flags; \
1068 local_irq_save(__flags); \
1070 __asm__ __volatile__( \
1071 ".set\tmips64\n\t" \
1072 "dsll\t%L0, %L0, 32\n\t" \
1073 "dsrl\t%L0, %L0, 32\n\t" \
1074 "dsll\t%M0, %M0, 32\n\t" \
1075 "or\t%L0, %L0, %M0\n\t" \
1076 "dmtc0\t%L0, " #source "\n\t" \
1080 __asm__ __volatile__( \
1081 ".set\tmips64\n\t" \
1082 "dsll\t%L0, %L0, 32\n\t" \
1083 "dsrl\t%L0, %L0, 32\n\t" \
1084 "dsll\t%M0, %M0, 32\n\t" \
1085 "or\t%L0, %L0, %M0\n\t" \
1086 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1089 local_irq_restore(__flags); \
1092 #define __readx_32bit_c0_register(source) \
1094 unsigned int __res; \
1096 __asm__ __volatile__( \
1099 " .set mips32r2 \n" \
1101 " # mfhc0 $1, %1 \n" \
1102 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
1110 #define __writex_32bit_c0_register(register, value) \
1112 __asm__ __volatile__( \
1115 " .set mips32r2 \n" \
1117 " # mthc0 $1, %1 \n" \
1119 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
1122 : "r" (value), "i" (register)); \
1125 #define read_c0_index() __read_32bit_c0_register($0, 0)
1126 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1128 #define read_c0_random() __read_32bit_c0_register($1, 0)
1129 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1131 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1132 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1134 #define readx_c0_entrylo0() __readx_32bit_c0_register(2)
1135 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1137 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1138 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1140 #define readx_c0_entrylo1() __readx_32bit_c0_register(3)
1141 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1143 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1144 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1146 #define read_c0_context() __read_ulong_c0_register($4, 0)
1147 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1149 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1150 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1152 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1153 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1155 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1156 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1158 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1159 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1161 #define read_c0_info() __read_32bit_c0_register($7, 0)
1163 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1164 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1166 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1167 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1169 #define read_c0_count() __read_32bit_c0_register($9, 0)
1170 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1172 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1173 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1175 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1176 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1178 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1179 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1181 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1182 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1184 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1185 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1187 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1188 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1190 #define read_c0_status() __read_32bit_c0_register($12, 0)
1192 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1194 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1195 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1197 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1198 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1200 #define read_c0_prid() __read_32bit_c0_register($15, 0)
1202 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1204 #define read_c0_config() __read_32bit_c0_register($16, 0)
1205 #define read_c0_config1() __read_32bit_c0_register($16, 1)
1206 #define read_c0_config2() __read_32bit_c0_register($16, 2)
1207 #define read_c0_config3() __read_32bit_c0_register($16, 3)
1208 #define read_c0_config4() __read_32bit_c0_register($16, 4)
1209 #define read_c0_config5() __read_32bit_c0_register($16, 5)
1210 #define read_c0_config6() __read_32bit_c0_register($16, 6)
1211 #define read_c0_config7() __read_32bit_c0_register($16, 7)
1212 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1213 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1214 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1215 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1216 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1217 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1218 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1219 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1221 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1222 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1223 #define read_c0_maar() __read_ulong_c0_register($17, 1)
1224 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1225 #define read_c0_maari() __read_32bit_c0_register($17, 2)
1226 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1229 * The WatchLo register. There may be up to 8 of them.
1231 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1232 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1233 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1234 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1235 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1236 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1237 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1238 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1239 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1240 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1241 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1242 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1243 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1244 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1245 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1246 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1249 * The WatchHi register. There may be up to 8 of them.
1251 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1252 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1253 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1254 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1255 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1256 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1257 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1258 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1260 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1261 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1262 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1263 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1264 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1265 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1266 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1267 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1269 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1270 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1272 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1273 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1275 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1276 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1278 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1279 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1281 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1282 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1283 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1285 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
1286 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1288 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
1289 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1291 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
1292 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1294 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
1295 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1297 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
1298 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1300 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1301 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1303 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1304 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1307 * MIPS32 / MIPS64 performance counters
1309 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1310 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1311 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1312 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1313 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1314 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1315 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1316 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1317 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1318 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1319 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1320 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1321 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1322 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1323 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1324 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1325 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1326 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1327 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1328 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1329 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1330 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1331 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1332 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1334 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1335 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1337 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1338 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1340 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1342 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1343 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1345 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1346 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1348 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1349 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1351 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1352 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1354 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1355 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1357 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1358 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1360 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1361 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1364 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1365 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1367 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1368 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1370 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1371 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1373 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1374 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1376 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1377 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1379 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1380 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1383 #define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1384 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1386 #define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1387 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1389 #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1390 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1392 /* Hardware Page Table Walker */
1393 #define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1394 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1396 #define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1397 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1399 #define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1400 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1402 #define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1403 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1405 /* Cavium OCTEON (cnMIPS) */
1406 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1407 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1409 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1410 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1412 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1413 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1415 * The cacheerr registers are not standardized. On OCTEON, they are
1418 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1419 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1421 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1422 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1425 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1426 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1428 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1429 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1431 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1432 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1435 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1436 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1438 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1439 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1441 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1442 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1444 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1445 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1447 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1448 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1451 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1452 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1454 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1455 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1457 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1458 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1460 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1461 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1463 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1464 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1466 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1467 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1470 * Macros to access the floating point coprocessor control registers
1472 #define _read_32bit_cp1_register(source, gas_hardfloat) \
1476 __asm__ __volatile__( \
1478 " .set reorder \n" \
1479 " # gas fails to assemble cfc1 for some archs, \n" \
1480 " # like Octeon. \n" \
1482 " "STR(gas_hardfloat)" \n" \
1483 " cfc1 %0,"STR(source)" \n" \
1489 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
1491 __asm__ __volatile__( \
1493 " .set reorder \n" \
1494 " "STR(gas_hardfloat)" \n" \
1495 " ctc1 %0,"STR(dest)" \n" \
1500 #ifdef GAS_HAS_SET_HARDFLOAT
1501 #define read_32bit_cp1_register(source) \
1502 _read_32bit_cp1_register(source, .set hardfloat)
1503 #define write_32bit_cp1_register(dest, val) \
1504 _write_32bit_cp1_register(dest, val, .set hardfloat)
1506 #define read_32bit_cp1_register(source) \
1507 _read_32bit_cp1_register(source, )
1508 #define write_32bit_cp1_register(dest, val) \
1509 _write_32bit_cp1_register(dest, val, )
1513 #define rddsp(mask) \
1515 unsigned int __dspctl; \
1517 __asm__ __volatile__( \
1520 " rddsp %0, %x1 \n" \
1527 #define wrdsp(val, mask) \
1529 __asm__ __volatile__( \
1532 " wrdsp %0, %x1 \n" \
1535 : "r" (val), "i" (mask)); \
1544 " mflo %0, $ac0 \n" \
1556 " mflo %0, $ac1 \n" \
1568 " mflo %0, $ac2 \n" \
1580 " mflo %0, $ac3 \n" \
1592 " mfhi %0, $ac0 \n" \
1604 " mfhi %0, $ac1 \n" \
1616 " mfhi %0, $ac2 \n" \
1628 " mfhi %0, $ac3 \n" \
1640 " mtlo %0, $ac0 \n" \
1651 " mtlo %0, $ac1 \n" \
1662 " mtlo %0, $ac2 \n" \
1673 " mtlo %0, $ac3 \n" \
1684 " mthi %0, $ac0 \n" \
1695 " mthi %0, $ac1 \n" \
1706 " mthi %0, $ac2 \n" \
1717 " mthi %0, $ac3 \n" \
1725 #ifdef CONFIG_CPU_MICROMIPS
1726 #define rddsp(mask) \
1728 unsigned int __res; \
1730 __asm__ __volatile__( \
1733 " # rddsp $1, %x1 \n" \
1734 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1735 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1743 #define wrdsp(val, mask) \
1745 __asm__ __volatile__( \
1749 " # wrdsp $1, %x1 \n" \
1750 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1751 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1754 : "r" (val), "i" (mask)); \
1757 #define _umips_dsp_mfxxx(ins) \
1759 unsigned long __treg; \
1761 __asm__ __volatile__( \
1764 " .hword 0x0001 \n" \
1773 #define _umips_dsp_mtxxx(val, ins) \
1775 __asm__ __volatile__( \
1779 " .hword 0x0001 \n" \
1783 : "r" (val), "i" (ins)); \
1786 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1787 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1789 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1790 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1792 #define mflo0() _umips_dsp_mflo(0)
1793 #define mflo1() _umips_dsp_mflo(1)
1794 #define mflo2() _umips_dsp_mflo(2)
1795 #define mflo3() _umips_dsp_mflo(3)
1797 #define mfhi0() _umips_dsp_mfhi(0)
1798 #define mfhi1() _umips_dsp_mfhi(1)
1799 #define mfhi2() _umips_dsp_mfhi(2)
1800 #define mfhi3() _umips_dsp_mfhi(3)
1802 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1803 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1804 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1805 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1807 #define mthi0(x) _umips_dsp_mthi(x, 0)
1808 #define mthi1(x) _umips_dsp_mthi(x, 1)
1809 #define mthi2(x) _umips_dsp_mthi(x, 2)
1810 #define mthi3(x) _umips_dsp_mthi(x, 3)
1812 #else /* !CONFIG_CPU_MICROMIPS */
1813 #define rddsp(mask) \
1815 unsigned int __res; \
1817 __asm__ __volatile__( \
1820 " # rddsp $1, %x1 \n" \
1821 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1829 #define wrdsp(val, mask) \
1831 __asm__ __volatile__( \
1835 " # wrdsp $1, %x1 \n" \
1836 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1839 : "r" (val), "i" (mask)); \
1842 #define _dsp_mfxxx(ins) \
1844 unsigned long __treg; \
1846 __asm__ __volatile__( \
1849 " .word (0x00000810 | %1) \n" \
1857 #define _dsp_mtxxx(val, ins) \
1859 __asm__ __volatile__( \
1863 " .word (0x00200011 | %1) \n" \
1866 : "r" (val), "i" (ins)); \
1869 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1870 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1872 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1873 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1875 #define mflo0() _dsp_mflo(0)
1876 #define mflo1() _dsp_mflo(1)
1877 #define mflo2() _dsp_mflo(2)
1878 #define mflo3() _dsp_mflo(3)
1880 #define mfhi0() _dsp_mfhi(0)
1881 #define mfhi1() _dsp_mfhi(1)
1882 #define mfhi2() _dsp_mfhi(2)
1883 #define mfhi3() _dsp_mfhi(3)
1885 #define mtlo0(x) _dsp_mtlo(x, 0)
1886 #define mtlo1(x) _dsp_mtlo(x, 1)
1887 #define mtlo2(x) _dsp_mtlo(x, 2)
1888 #define mtlo3(x) _dsp_mtlo(x, 3)
1890 #define mthi0(x) _dsp_mthi(x, 0)
1891 #define mthi1(x) _dsp_mthi(x, 1)
1892 #define mthi2(x) _dsp_mthi(x, 2)
1893 #define mthi3(x) _dsp_mthi(x, 3)
1895 #endif /* CONFIG_CPU_MICROMIPS */
1901 * It is responsibility of the caller to take care of any TLB hazards.
1903 static inline void tlb_probe(void)
1905 __asm__ __volatile__(
1906 ".set noreorder\n\t"
1911 static inline void tlb_read(void)
1913 #if MIPS34K_MISSED_ITLB_WAR
1916 __asm__ __volatile__(
1918 " .set noreorder \n"
1921 " .word 0x41610001 # dvpe $1 \n"
1927 instruction_hazard();
1930 __asm__ __volatile__(
1931 ".set noreorder\n\t"
1935 #if MIPS34K_MISSED_ITLB_WAR
1936 if ((res & _ULCAST_(1)))
1937 __asm__ __volatile__(
1939 " .set noreorder \n"
1942 " .word 0x41600021 # evpe \n"
1948 static inline void tlb_write_indexed(void)
1950 __asm__ __volatile__(
1951 ".set noreorder\n\t"
1956 static inline void tlb_write_random(void)
1958 __asm__ __volatile__(
1959 ".set noreorder\n\t"
1965 * Manipulate bits in a c0 register.
1967 #define __BUILD_SET_C0(name) \
1968 static inline unsigned int \
1969 set_c0_##name(unsigned int set) \
1971 unsigned int res, new; \
1973 res = read_c0_##name(); \
1975 write_c0_##name(new); \
1980 static inline unsigned int \
1981 clear_c0_##name(unsigned int clear) \
1983 unsigned int res, new; \
1985 res = read_c0_##name(); \
1986 new = res & ~clear; \
1987 write_c0_##name(new); \
1992 static inline unsigned int \
1993 change_c0_##name(unsigned int change, unsigned int val) \
1995 unsigned int res, new; \
1997 res = read_c0_##name(); \
1998 new = res & ~change; \
1999 new |= (val & change); \
2000 write_c0_##name(new); \
2005 __BUILD_SET_C0(status)
2006 __BUILD_SET_C0(cause)
2007 __BUILD_SET_C0(config)
2008 __BUILD_SET_C0(config5)
2009 __BUILD_SET_C0(intcontrol)
2010 __BUILD_SET_C0(intctl)
2011 __BUILD_SET_C0(srsmap)
2012 __BUILD_SET_C0(pagegrain)
2013 __BUILD_SET_C0(brcm_config_0)
2014 __BUILD_SET_C0(brcm_bus_pll)
2015 __BUILD_SET_C0(brcm_reset)
2016 __BUILD_SET_C0(brcm_cmt_intr)
2017 __BUILD_SET_C0(brcm_cmt_ctrl)
2018 __BUILD_SET_C0(brcm_config)
2019 __BUILD_SET_C0(brcm_mode)
2022 * Return low 10 bits of ebase.
2023 * Note that under KVM (MIPSVZ) this returns vcpu id.
2025 static inline unsigned int get_ebase_cpunum(void)
2027 return read_c0_ebase() & 0x3ff;
2030 #endif /* !__ASSEMBLY__ */
2032 #endif /* _ASM_MIPSREGS_H */