2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <asm/addrspace.h>
13 #include <asm/asm-offsets.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
16 #include <asm/mipsregs.h>
18 #define GCR_CL_COHERENCE_OFS 0x2008
20 .section .text.cps-vec
24 LEAF(mips_cps_core_entry)
26 * These first 8 bytes will be patched by cps_smp_setup to load the
27 * base address of the CM GCRs into register v1.
31 /* Check whether we're here due to an NMI */
48 li t0, ST0_CU1 | ST0_CU0
52 * Clear the bits used to index the caches. Note that the architecture
53 * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
54 * be valid for all MIPS32 CPUs, even those for which said writes are
57 mtc0 zero, CP0_TAGLO, 0
58 mtc0 zero, CP0_TAGHI, 0
59 mtc0 zero, CP0_TAGLO, 2
60 mtc0 zero, CP0_TAGHI, 2
63 /* Primary cache configuration is indicated by Config1 */
64 mfc0 v0, CP0_CONFIG, 1
66 /* Detect I-cache line size */
67 _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
72 /* Detect I-cache size */
73 _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
79 1: /* At this point t1 == I-cache sets per way */
80 _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
87 1: cache Index_Store_Tag_I, 0(a0)
93 /* Detect D-cache line size */
94 _EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
99 /* Detect D-cache size */
100 _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
106 1: /* At this point t1 == D-cache sets per way */
107 _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
115 1: cache Index_Store_Tag_D, 0(a0)
120 /* Set Kseg0 cacheable, coherent, write-back, write-allocate */
127 /* Enter the coherent domain */
129 sw t0, GCR_CL_COHERENCE_OFS(v1)
137 1: /* We're up, cached & coherent */
140 * TODO: We should check the VPE number we intended to boot here, and
141 * if non-zero we should start that VPE and stop this one. For
142 * the moment this doesn't matter since CPUs are brought up
143 * sequentially and in order, but once hotplug is implemented
144 * this will need revisiting.
148 la t0, mips_cps_bootcfg
149 lw t1, BOOTCFG_PC(t0)
150 lw gp, BOOTCFG_GP(t0)
151 lw sp, BOOTCFG_SP(t0)
154 END(mips_cps_core_entry)
188 la k0, ejtag_debug_handler