arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-type.h>
  24 #include <asm/fpu.h>
  25 #include <asm/mipsregs.h>
  26 #include <asm/msa.h>
  27 #include <asm/watch.h>
  28 #include <asm/elf.h>
  29 #include <asm/spram.h>
  30 #include <asm/uaccess.h>
  31
  32 static int mips_fpu_disabled;
  33
  34 static int __init fpu_disable(char *s)
  35 {
  36         cpu_data[0].options &= ~MIPS_CPU_FPU;
  37         mips_fpu_disabled = 1;
  38
  39         return 1;
  40 }
  41
  42 __setup("nofpu", fpu_disable);
  43
  44 int mips_dsp_disabled;
  45
  46 static int __init dsp_disable(char *s)
  47 {
  48         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
  49         mips_dsp_disabled = 1;
  50
  51         return 1;
  52 }
  53
  54 __setup("nodsp", dsp_disable);
  55
  56 static inline void check_errata(void)
  57 {
  58         struct cpuinfo_mips *c = &current_cpu_data;
  59
  60         switch (current_cpu_type()) {
  61         case CPU_34K:
  62                 /*
  63                  * Erratum "RPS May Cause Incorrect Instruction Execution"
  64                  * This code only handles VPE0, any SMP/SMTC/RTOS code
  65                  * making use of VPE1 will be responsable for that VPE.
  66                  */
  67                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
  68                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
  69                 break;
  70         default:
  71                 break;
  72         }
  73 }
  74
  75 void __init check_bugs32(void)
  76 {
  77         check_errata();
  78 }
  79
  80 /*
  81  * Probe whether cpu has config register by trying to play with
  82  * alternate cache bit and see whether it matters.
  83  * It's used by cpu_probe to distinguish between R3000A and R3081.
  84  */
  85 static inline int cpu_has_confreg(void)
  86 {
  87 #ifdef CONFIG_CPU_R3000
  88         extern unsigned long r3k_cache_size(unsigned long);
  89         unsigned long size1, size2;
  90         unsigned long cfg = read_c0_conf();
  91
  92         size1 = r3k_cache_size(ST0_ISC);
  93         write_c0_conf(cfg ^ R30XX_CONF_AC);
  94         size2 = r3k_cache_size(ST0_ISC);
  95         write_c0_conf(cfg);
  96         return size1 != size2;
  97 #else
  98         return 0;
  99 #endif
 100 }
 101
 102 static inline void set_elf_platform(int cpu, const char *plat)
 103 {
 104         if (cpu == 0)
 105                 __elf_platform = plat;
 106 }
 107
 108 /*
 109  * Get the FPU Implementation/Revision.
 110  */
 111 static inline unsigned long cpu_get_fpu_id(void)
 112 {
 113         unsigned long tmp, fpu_id;
 114
 115         tmp = read_c0_status();
 116         __enable_fpu(FPU_AS_IS);
 117         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 118         write_c0_status(tmp);
 119         return fpu_id;
 120 }
 121
 122 /*
 123  * Check the CPU has an FPU the official way.
 124  */
 125 static inline int __cpu_has_fpu(void)
 126 {
 127         return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
 128 }
 129
 130 static inline unsigned long cpu_get_msa_id(void)
 131 {
 132         unsigned long status, conf5, msa_id;
 133
 134         status = read_c0_status();
 135         __enable_fpu(FPU_64BIT);
 136         conf5 = read_c0_config5();
 137         enable_msa();
 138         msa_id = read_msa_ir();
 139         write_c0_config5(conf5);
 140         write_c0_status(status);
 141         return msa_id;
 142 }
 143
 144 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 145 {
 146 #ifdef __NEED_VMBITS_PROBE
 147         write_c0_entryhi(0x3fffffffffffe000ULL);
 148         back_to_back_c0_hazard();
 149         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 150 #endif
 151 }
 152
 153 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 154 {
 155         switch (isa) {
 156         case MIPS_CPU_ISA_M64R2:
 157                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 158         case MIPS_CPU_ISA_M64R1:
 159                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 160         case MIPS_CPU_ISA_V:
 161                 c->isa_level |= MIPS_CPU_ISA_V;
 162         case MIPS_CPU_ISA_IV:
 163                 c->isa_level |= MIPS_CPU_ISA_IV;
 164         case MIPS_CPU_ISA_III:
 165                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 166                 break;
 167
 168         case MIPS_CPU_ISA_M32R2:
 169                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 170         case MIPS_CPU_ISA_M32R1:
 171                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 172         case MIPS_CPU_ISA_II:
 173                 c->isa_level |= MIPS_CPU_ISA_II;
 174                 break;
 175         }
 176 }
 177
 178 static char unknown_isa[] = KERN_ERR \
 179         "Unsupported ISA type, c0.config0: %d.";
 180
 181 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 182 {
 183         unsigned int config6;
 184
 185         /* It's implementation dependent how the FTLB can be enabled */
 186         switch (c->cputype) {
 187         case CPU_PROAPTIV:
 188         case CPU_P5600:
 189                 /* proAptiv & related cores use Config6 to enable the FTLB */
 190                 config6 = read_c0_config6();
 191                 if (enable)
 192                         /* Enable FTLB */
 193                         write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
 194                 else
 195                         /* Disable FTLB */
 196                         write_c0_config6(config6 &  ~MIPS_CONF6_FTLBEN);
 197                 back_to_back_c0_hazard();
 198                 break;
 199         }
 200 }
 201
 202 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 203 {
 204         unsigned int config0;
 205         int isa;
 206
 207         config0 = read_c0_config();
 208
 209         /*
 210          * Look for Standard TLB or Dual VTLB and FTLB
 211          */
 212         if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
 213             (((config0 & MIPS_CONF_MT) >> 7) == 4))
 214                 c->options |= MIPS_CPU_TLB;
 215
 216         isa = (config0 & MIPS_CONF_AT) >> 13;
 217         switch (isa) {
 218         case 0:
 219                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 220                 case 0:
 221                         set_isa(c, MIPS_CPU_ISA_M32R1);
 222                         break;
 223                 case 1:
 224                         set_isa(c, MIPS_CPU_ISA_M32R2);
 225                         break;
 226                 default:
 227                         goto unknown;
 228                 }
 229                 break;
 230         case 2:
 231                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 232                 case 0:
 233                         set_isa(c, MIPS_CPU_ISA_M64R1);
 234                         break;
 235                 case 1:
 236                         set_isa(c, MIPS_CPU_ISA_M64R2);
 237                         break;
 238                 default:
 239                         goto unknown;
 240                 }
 241                 break;
 242         default:
 243                 goto unknown;
 244         }
 245
 246         return config0 & MIPS_CONF_M;
 247
 248 unknown:
 249         panic(unknown_isa, config0);
 250 }
 251
 252 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 253 {
 254         unsigned int config1;
 255
 256         config1 = read_c0_config1();
 257
 258         if (config1 & MIPS_CONF1_MD)
 259                 c->ases |= MIPS_ASE_MDMX;
 260         if (config1 & MIPS_CONF1_WR)
 261                 c->options |= MIPS_CPU_WATCH;
 262         if (config1 & MIPS_CONF1_CA)
 263                 c->ases |= MIPS_ASE_MIPS16;
 264         if (config1 & MIPS_CONF1_EP)
 265                 c->options |= MIPS_CPU_EJTAG;
 266         if (config1 & MIPS_CONF1_FP) {
 267                 c->options |= MIPS_CPU_FPU;
 268                 c->options |= MIPS_CPU_32FPR;
 269         }
 270         if (cpu_has_tlb) {
 271                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 272                 c->tlbsizevtlb = c->tlbsize;
 273                 c->tlbsizeftlbsets = 0;
 274         }
 275
 276         return config1 & MIPS_CONF_M;
 277 }
 278
 279 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 280 {
 281         unsigned int config2;
 282
 283         config2 = read_c0_config2();
 284
 285         if (config2 & MIPS_CONF2_SL)
 286                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 287
 288         return config2 & MIPS_CONF_M;
 289 }
 290
 291 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 292 {
 293         unsigned int config3;
 294
 295         config3 = read_c0_config3();
 296
 297         if (config3 & MIPS_CONF3_SM) {
 298                 c->ases |= MIPS_ASE_SMARTMIPS;
 299                 c->options |= MIPS_CPU_RIXI;
 300         }
 301         if (config3 & MIPS_CONF3_RXI)
 302                 c->options |= MIPS_CPU_RIXI;
 303         if (config3 & MIPS_CONF3_DSP)
 304                 c->ases |= MIPS_ASE_DSP;
 305         if (config3 & MIPS_CONF3_DSP2P)
 306                 c->ases |= MIPS_ASE_DSP2P;
 307         if (config3 & MIPS_CONF3_VINT)
 308                 c->options |= MIPS_CPU_VINT;
 309         if (config3 & MIPS_CONF3_VEIC)
 310                 c->options |= MIPS_CPU_VEIC;
 311         if (config3 & MIPS_CONF3_MT)
 312                 c->ases |= MIPS_ASE_MIPSMT;
 313         if (config3 & MIPS_CONF3_ULRI)
 314                 c->options |= MIPS_CPU_ULRI;
 315         if (config3 & MIPS_CONF3_ISA)
 316                 c->options |= MIPS_CPU_MICROMIPS;
 317         if (config3 & MIPS_CONF3_VZ)
 318                 c->ases |= MIPS_ASE_VZ;
 319         if (config3 & MIPS_CONF3_SC)
 320                 c->options |= MIPS_CPU_SEGMENTS;
 321         if (config3 & MIPS_CONF3_MSA)
 322                 c->ases |= MIPS_ASE_MSA;
 323
 324         return config3 & MIPS_CONF_M;
 325 }
 326
 327 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 328 {
 329         unsigned int config4;
 330         unsigned int newcf4;
 331         unsigned int mmuextdef;
 332         unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 333
 334         config4 = read_c0_config4();
 335
 336         if (cpu_has_tlb) {
 337                 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
 338                         c->options |= MIPS_CPU_TLBINV;
 339                 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 340                 switch (mmuextdef) {
 341                 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
 342                         c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 343                         c->tlbsizevtlb = c->tlbsize;
 344                         break;
 345                 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
 346                         c->tlbsizevtlb +=
 347                                 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
 348                                   MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
 349                         c->tlbsize = c->tlbsizevtlb;
 350                         ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
 351                         /* fall through */
 352                 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
 353                         newcf4 = (config4 & ~ftlb_page) |
 354                                 (page_size_ftlb(mmuextdef) <<
 355                                  MIPS_CONF4_FTLBPAGESIZE_SHIFT);
 356                         write_c0_config4(newcf4);
 357                         back_to_back_c0_hazard();
 358                         config4 = read_c0_config4();
 359                         if (config4 != newcf4) {
 360                                 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
 361                                        PAGE_SIZE, config4);
 362                                 /* Switch FTLB off */
 363                                 set_ftlb_enable(c, 0);
 364                                 break;
 365                         }
 366                         c->tlbsizeftlbsets = 1 <<
 367                                 ((config4 & MIPS_CONF4_FTLBSETS) >>
 368                                  MIPS_CONF4_FTLBSETS_SHIFT);
 369                         c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
 370                                               MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
 371                         c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
 372                         break;
 373                 }
 374         }
 375
 376         c->kscratch_mask = (config4 >> 16) & 0xff;
 377
 378         return config4 & MIPS_CONF_M;
 379 }
 380
 381 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 382 {
 383         unsigned int config5;
 384
 385         config5 = read_c0_config5();
 386         config5 &= ~MIPS_CONF5_UFR;
 387         write_c0_config5(config5);
 388
 389         if (config5 & MIPS_CONF5_EVA)
 390                 c->options |= MIPS_CPU_EVA;
 391
 392         return config5 & MIPS_CONF_M;
 393 }
 394
 395 static void decode_configs(struct cpuinfo_mips *c)
 396 {
 397         int ok;
 398
 399         /* MIPS32 or MIPS64 compliant CPU.  */
 400         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 401                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 402
 403         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 404
 405         /* Enable FTLB if present */
 406         set_ftlb_enable(c, 1);
 407
 408         ok = decode_config0(c);                 /* Read Config registers.  */
 409         BUG_ON(!ok);                            /* Arch spec violation!  */
 410         if (ok)
 411                 ok = decode_config1(c);
 412         if (ok)
 413                 ok = decode_config2(c);
 414         if (ok)
 415                 ok = decode_config3(c);
 416         if (ok)
 417                 ok = decode_config4(c);
 418         if (ok)
 419                 ok = decode_config5(c);
 420
 421         mips_probe_watch_registers(c);
 422
 423 #ifndef CONFIG_MIPS_CPS
 424         if (cpu_has_mips_r2)
 425                 c->core = read_c0_ebase() & 0x3ff;
 426 #endif
 427 }
 428
 429 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 430                 | MIPS_CPU_COUNTER)
 431
 432 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 433 {
 434         switch (c->processor_id & PRID_IMP_MASK) {
 435         case PRID_IMP_R2000:
 436                 c->cputype = CPU_R2000;
 437                 __cpu_name[cpu] = "R2000";
 438                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 439                              MIPS_CPU_NOFPUEX;
 440                 if (__cpu_has_fpu())
 441                         c->options |= MIPS_CPU_FPU;
 442                 c->tlbsize = 64;
 443                 break;
 444         case PRID_IMP_R3000:
 445                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
 446                         if (cpu_has_confreg()) {
 447                                 c->cputype = CPU_R3081E;
 448                                 __cpu_name[cpu] = "R3081";
 449                         } else {
 450                                 c->cputype = CPU_R3000A;
 451                                 __cpu_name[cpu] = "R3000A";
 452                         }
 453                 } else {
 454                         c->cputype = CPU_R3000;
 455                         __cpu_name[cpu] = "R3000";
 456                 }
 457                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 458                              MIPS_CPU_NOFPUEX;
 459                 if (__cpu_has_fpu())
 460                         c->options |= MIPS_CPU_FPU;
 461                 c->tlbsize = 64;
 462                 break;
 463         case PRID_IMP_R4000:
 464                 if (read_c0_config() & CONF_SC) {
 465                         if ((c->processor_id & PRID_REV_MASK) >=
 466                             PRID_REV_R4400) {
 467                                 c->cputype = CPU_R4400PC;
 468                                 __cpu_name[cpu] = "R4400PC";
 469                         } else {
 470                                 c->cputype = CPU_R4000PC;
 471                                 __cpu_name[cpu] = "R4000PC";
 472                         }
 473                 } else {
 474                         int cca = read_c0_config() & CONF_CM_CMASK;
 475                         int mc;
 476
 477                         /*
 478                          * SC and MC versions can't be reliably told apart,
 479                          * but only the latter support coherent caching
 480                          * modes so assume the firmware has set the KSEG0
 481                          * coherency attribute reasonably (if uncached, we
 482                          * assume SC).
 483                          */
 484                         switch (cca) {
 485                         case CONF_CM_CACHABLE_CE:
 486                         case CONF_CM_CACHABLE_COW:
 487                         case CONF_CM_CACHABLE_CUW:
 488                                 mc = 1;
 489                                 break;
 490                         default:
 491                                 mc = 0;
 492                                 break;
 493                         }
 494                         if ((c->processor_id & PRID_REV_MASK) >=
 495                             PRID_REV_R4400) {
 496                                 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
 497                                 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
 498                         } else {
 499                                 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
 500                                 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
 501                         }
 502                 }
 503
 504                 set_isa(c, MIPS_CPU_ISA_III);
 505                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 506                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 507                              MIPS_CPU_LLSC;
 508                 c->tlbsize = 48;
 509                 break;
 510         case PRID_IMP_VR41XX:
 511                 set_isa(c, MIPS_CPU_ISA_III);
 512                 c->options = R4K_OPTS;
 513                 c->tlbsize = 32;
 514                 switch (c->processor_id & 0xf0) {
 515                 case PRID_REV_VR4111:
 516                         c->cputype = CPU_VR4111;
 517                         __cpu_name[cpu] = "NEC VR4111";
 518                         break;
 519                 case PRID_REV_VR4121:
 520                         c->cputype = CPU_VR4121;
 521                         __cpu_name[cpu] = "NEC VR4121";
 522                         break;
 523                 case PRID_REV_VR4122:
 524                         if ((c->processor_id & 0xf) < 0x3) {
 525                                 c->cputype = CPU_VR4122;
 526                                 __cpu_name[cpu] = "NEC VR4122";
 527                         } else {
 528                                 c->cputype = CPU_VR4181A;
 529                                 __cpu_name[cpu] = "NEC VR4181A";
 530                         }
 531                         break;
 532                 case PRID_REV_VR4130:
 533                         if ((c->processor_id & 0xf) < 0x4) {
 534                                 c->cputype = CPU_VR4131;
 535                                 __cpu_name[cpu] = "NEC VR4131";
 536                         } else {
 537                                 c->cputype = CPU_VR4133;
 538                                 c->options |= MIPS_CPU_LLSC;
 539                                 __cpu_name[cpu] = "NEC VR4133";
 540                         }
 541                         break;
 542                 default:
 543                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 544                         c->cputype = CPU_VR41XX;
 545                         __cpu_name[cpu] = "NEC Vr41xx";
 546                         break;
 547                 }
 548                 break;
 549         case PRID_IMP_R4300:
 550                 c->cputype = CPU_R4300;
 551                 __cpu_name[cpu] = "R4300";
 552                 set_isa(c, MIPS_CPU_ISA_III);
 553                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 554                              MIPS_CPU_LLSC;
 555                 c->tlbsize = 32;
 556                 break;
 557         case PRID_IMP_R4600:
 558                 c->cputype = CPU_R4600;
 559                 __cpu_name[cpu] = "R4600";
 560                 set_isa(c, MIPS_CPU_ISA_III);
 561                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 562                              MIPS_CPU_LLSC;
 563                 c->tlbsize = 48;
 564                 break;
 565         #if 0
 566         case PRID_IMP_R4650:
 567                 /*
 568                  * This processor doesn't have an MMU, so it's not
 569                  * "real easy" to run Linux on it. It is left purely
 570                  * for documentation.  Commented out because it shares
 571                  * it's c0_prid id number with the TX3900.
 572                  */
 573                 c->cputype = CPU_R4650;
 574                 __cpu_name[cpu] = "R4650";
 575                 set_isa(c, MIPS_CPU_ISA_III);
 576                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 577                 c->tlbsize = 48;
 578                 break;
 579         #endif
 580         case PRID_IMP_TX39:
 581                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 582
 583                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 584                         c->cputype = CPU_TX3927;
 585                         __cpu_name[cpu] = "TX3927";
 586                         c->tlbsize = 64;
 587                 } else {
 588                         switch (c->processor_id & PRID_REV_MASK) {
 589                         case PRID_REV_TX3912:
 590                                 c->cputype = CPU_TX3912;
 591                                 __cpu_name[cpu] = "TX3912";
 592                                 c->tlbsize = 32;
 593                                 break;
 594                         case PRID_REV_TX3922:
 595                                 c->cputype = CPU_TX3922;
 596                                 __cpu_name[cpu] = "TX3922";
 597                                 c->tlbsize = 64;
 598                                 break;
 599                         }
 600                 }
 601                 break;
 602         case PRID_IMP_R4700:
 603                 c->cputype = CPU_R4700;
 604                 __cpu_name[cpu] = "R4700";
 605                 set_isa(c, MIPS_CPU_ISA_III);
 606                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 607                              MIPS_CPU_LLSC;
 608                 c->tlbsize = 48;
 609                 break;
 610         case PRID_IMP_TX49:
 611                 c->cputype = CPU_TX49XX;
 612                 __cpu_name[cpu] = "R49XX";
 613                 set_isa(c, MIPS_CPU_ISA_III);
 614                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 615                 if (!(c->processor_id & 0x08))
 616                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 617                 c->tlbsize = 48;
 618                 break;
 619         case PRID_IMP_R5000:
 620                 c->cputype = CPU_R5000;
 621                 __cpu_name[cpu] = "R5000";
 622                 set_isa(c, MIPS_CPU_ISA_IV);
 623                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 624                              MIPS_CPU_LLSC;
 625                 c->tlbsize = 48;
 626                 break;
 627         case PRID_IMP_R5432:
 628                 c->cputype = CPU_R5432;
 629                 __cpu_name[cpu] = "R5432";
 630                 set_isa(c, MIPS_CPU_ISA_IV);
 631                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 632                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 633                 c->tlbsize = 48;
 634                 break;
 635         case PRID_IMP_R5500:
 636                 c->cputype = CPU_R5500;
 637                 __cpu_name[cpu] = "R5500";
 638                 set_isa(c, MIPS_CPU_ISA_IV);
 639                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 640                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 641                 c->tlbsize = 48;
 642                 break;
 643         case PRID_IMP_NEVADA:
 644                 c->cputype = CPU_NEVADA;
 645                 __cpu_name[cpu] = "Nevada";
 646                 set_isa(c, MIPS_CPU_ISA_IV);
 647                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 648                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 649                 c->tlbsize = 48;
 650                 break;
 651         case PRID_IMP_R6000:
 652                 c->cputype = CPU_R6000;
 653                 __cpu_name[cpu] = "R6000";
 654                 set_isa(c, MIPS_CPU_ISA_II);
 655                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 656                              MIPS_CPU_LLSC;
 657                 c->tlbsize = 32;
 658                 break;
 659         case PRID_IMP_R6000A:
 660                 c->cputype = CPU_R6000A;
 661                 __cpu_name[cpu] = "R6000A";
 662                 set_isa(c, MIPS_CPU_ISA_II);
 663                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 664                              MIPS_CPU_LLSC;
 665                 c->tlbsize = 32;
 666                 break;
 667         case PRID_IMP_RM7000:
 668                 c->cputype = CPU_RM7000;
 669                 __cpu_name[cpu] = "RM7000";
 670                 set_isa(c, MIPS_CPU_ISA_IV);
 671                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 672                              MIPS_CPU_LLSC;
 673                 /*
 674                  * Undocumented RM7000:  Bit 29 in the info register of
 675                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 676                  * entries.
 677                  *
 678                  * 29      1 =>    64 entry JTLB
 679                  *         0 =>    48 entry JTLB
 680                  */
 681                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 682                 break;
 683         case PRID_IMP_RM9000:
 684                 c->cputype = CPU_RM9000;
 685                 __cpu_name[cpu] = "RM9000";
 686                 set_isa(c, MIPS_CPU_ISA_IV);
 687                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 688                              MIPS_CPU_LLSC;
 689                 /*
 690                  * Bit 29 in the info register of the RM9000
 691                  * indicates if the TLB has 48 or 64 entries.
 692                  *
 693                  * 29      1 =>    64 entry JTLB
 694                  *         0 =>    48 entry JTLB
 695                  */
 696                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 697                 break;
 698         case PRID_IMP_R8000:
 699                 c->cputype = CPU_R8000;
 700                 __cpu_name[cpu] = "RM8000";
 701                 set_isa(c, MIPS_CPU_ISA_IV);
 702                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 703                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 704                              MIPS_CPU_LLSC;
 705                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 706                 break;
 707         case PRID_IMP_R10000:
 708                 c->cputype = CPU_R10000;
 709                 __cpu_name[cpu] = "R10000";
 710                 set_isa(c, MIPS_CPU_ISA_IV);
 711                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 712                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 713                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 714                              MIPS_CPU_LLSC;
 715                 c->tlbsize = 64;
 716                 break;
 717         case PRID_IMP_R12000:
 718                 c->cputype = CPU_R12000;
 719                 __cpu_name[cpu] = "R12000";
 720                 set_isa(c, MIPS_CPU_ISA_IV);
 721                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 722                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 723                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 724                              MIPS_CPU_LLSC;
 725                 c->tlbsize = 64;
 726                 break;
 727         case PRID_IMP_R14000:
 728                 c->cputype = CPU_R14000;
 729                 __cpu_name[cpu] = "R14000";
 730                 set_isa(c, MIPS_CPU_ISA_IV);
 731                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 732                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 733                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 734                              MIPS_CPU_LLSC;
 735                 c->tlbsize = 64;
 736                 break;
 737         case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
 738                 switch (c->processor_id & PRID_REV_MASK) {
 739                 case PRID_REV_LOONGSON2E:
 740                         c->cputype = CPU_LOONGSON2;
 741                         __cpu_name[cpu] = "ICT Loongson-2";
 742                         set_elf_platform(cpu, "loongson2e");
 743                         break;
 744                 case PRID_REV_LOONGSON2F:
 745                         c->cputype = CPU_LOONGSON2;
 746                         __cpu_name[cpu] = "ICT Loongson-2";
 747                         set_elf_platform(cpu, "loongson2f");
 748                         break;
 749                 case PRID_REV_LOONGSON3A:
 750                         c->cputype = CPU_LOONGSON3;
 751                         __cpu_name[cpu] = "ICT Loongson-3";
 752                         set_elf_platform(cpu, "loongson3a");
 753                         break;
 754                 }
 755
 756                 set_isa(c, MIPS_CPU_ISA_III);
 757                 c->options = R4K_OPTS |
 758                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 759                              MIPS_CPU_32FPR;
 760                 c->tlbsize = 64;
 761                 break;
 762         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
 763                 decode_configs(c);
 764
 765                 c->cputype = CPU_LOONGSON1;
 766
 767                 switch (c->processor_id & PRID_REV_MASK) {
 768                 case PRID_REV_LOONGSON1B:
 769                         __cpu_name[cpu] = "Loongson 1B";
 770                         break;
 771                 }
 772
 773                 break;
 774         }
 775 }
 776
 777 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 778 {
 779         switch (c->processor_id & PRID_IMP_MASK) {
 780         case PRID_IMP_4KC:
 781                 c->cputype = CPU_4KC;
 782                 __cpu_name[cpu] = "MIPS 4Kc";
 783                 break;
 784         case PRID_IMP_4KEC:
 785         case PRID_IMP_4KECR2:
 786                 c->cputype = CPU_4KEC;
 787                 __cpu_name[cpu] = "MIPS 4KEc";
 788                 break;
 789         case PRID_IMP_4KSC:
 790         case PRID_IMP_4KSD:
 791                 c->cputype = CPU_4KSC;
 792                 __cpu_name[cpu] = "MIPS 4KSc";
 793                 break;
 794         case PRID_IMP_5KC:
 795                 c->cputype = CPU_5KC;
 796                 __cpu_name[cpu] = "MIPS 5Kc";
 797                 break;
 798         case PRID_IMP_5KE:
 799                 c->cputype = CPU_5KE;
 800                 __cpu_name[cpu] = "MIPS 5KE";
 801                 break;
 802         case PRID_IMP_20KC:
 803                 c->cputype = CPU_20KC;
 804                 __cpu_name[cpu] = "MIPS 20Kc";
 805                 break;
 806         case PRID_IMP_24K:
 807                 c->cputype = CPU_24K;
 808                 __cpu_name[cpu] = "MIPS 24Kc";
 809                 break;
 810         case PRID_IMP_24KE:
 811                 c->cputype = CPU_24K;
 812                 __cpu_name[cpu] = "MIPS 24KEc";
 813                 break;
 814         case PRID_IMP_25KF:
 815                 c->cputype = CPU_25KF;
 816                 __cpu_name[cpu] = "MIPS 25Kc";
 817                 break;
 818         case PRID_IMP_34K:
 819                 c->cputype = CPU_34K;
 820                 __cpu_name[cpu] = "MIPS 34Kc";
 821                 break;
 822         case PRID_IMP_74K:
 823                 c->cputype = CPU_74K;
 824                 __cpu_name[cpu] = "MIPS 74Kc";
 825                 break;
 826         case PRID_IMP_M14KC:
 827                 c->cputype = CPU_M14KC;
 828                 __cpu_name[cpu] = "MIPS M14Kc";
 829                 break;
 830         case PRID_IMP_M14KEC:
 831                 c->cputype = CPU_M14KEC;
 832                 __cpu_name[cpu] = "MIPS M14KEc";
 833                 break;
 834         case PRID_IMP_1004K:
 835                 c->cputype = CPU_1004K;
 836                 __cpu_name[cpu] = "MIPS 1004Kc";
 837                 break;
 838         case PRID_IMP_1074K:
 839                 c->cputype = CPU_1074K;
 840                 __cpu_name[cpu] = "MIPS 1074Kc";
 841                 break;
 842         case PRID_IMP_INTERAPTIV_UP:
 843                 c->cputype = CPU_INTERAPTIV;
 844                 __cpu_name[cpu] = "MIPS interAptiv";
 845                 break;
 846         case PRID_IMP_INTERAPTIV_MP:
 847                 c->cputype = CPU_INTERAPTIV;
 848                 __cpu_name[cpu] = "MIPS interAptiv (multi)";
 849                 break;
 850         case PRID_IMP_PROAPTIV_UP:
 851                 c->cputype = CPU_PROAPTIV;
 852                 __cpu_name[cpu] = "MIPS proAptiv";
 853                 break;
 854         case PRID_IMP_PROAPTIV_MP:
 855                 c->cputype = CPU_PROAPTIV;
 856                 __cpu_name[cpu] = "MIPS proAptiv (multi)";
 857                 break;
 858         case PRID_IMP_P5600:
 859                 c->cputype = CPU_P5600;
 860                 __cpu_name[cpu] = "MIPS P5600";
 861                 break;
 862         case PRID_IMP_M5150:
 863                 c->cputype = CPU_M5150;
 864                 __cpu_name[cpu] = "MIPS M5150";
 865                 break;
 866         }
 867
 868         decode_configs(c);
 869
 870         spram_config();
 871 }
 872
 873 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 874 {
 875         decode_configs(c);
 876         switch (c->processor_id & PRID_IMP_MASK) {
 877         case PRID_IMP_AU1_REV1:
 878         case PRID_IMP_AU1_REV2:
 879                 c->cputype = CPU_ALCHEMY;
 880                 switch ((c->processor_id >> 24) & 0xff) {
 881                 case 0:
 882                         __cpu_name[cpu] = "Au1000";
 883                         break;
 884                 case 1:
 885                         __cpu_name[cpu] = "Au1500";
 886                         break;
 887                 case 2:
 888                         __cpu_name[cpu] = "Au1100";
 889                         break;
 890                 case 3:
 891                         __cpu_name[cpu] = "Au1550";
 892                         break;
 893                 case 4:
 894                         __cpu_name[cpu] = "Au1200";
 895                         if ((c->processor_id & PRID_REV_MASK) == 2)
 896                                 __cpu_name[cpu] = "Au1250";
 897                         break;
 898                 case 5:
 899                         __cpu_name[cpu] = "Au1210";
 900                         break;
 901                 default:
 902                         __cpu_name[cpu] = "Au1xxx";
 903                         break;
 904                 }
 905                 break;
 906         }
 907 }
 908
 909 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 910 {
 911         decode_configs(c);
 912
 913         switch (c->processor_id & PRID_IMP_MASK) {
 914         case PRID_IMP_SB1:
 915                 c->cputype = CPU_SB1;
 916                 __cpu_name[cpu] = "SiByte SB1";
 917                 /* FPU in pass1 is known to have issues. */
 918                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
 919                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 920                 break;
 921         case PRID_IMP_SB1A:
 922                 c->cputype = CPU_SB1A;
 923                 __cpu_name[cpu] = "SiByte SB1A";
 924                 break;
 925         }
 926 }
 927
 928 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 929 {
 930         decode_configs(c);
 931         switch (c->processor_id & PRID_IMP_MASK) {
 932         case PRID_IMP_SR71000:
 933                 c->cputype = CPU_SR71000;
 934                 __cpu_name[cpu] = "Sandcraft SR71000";
 935                 c->scache.ways = 8;
 936                 c->tlbsize = 64;
 937                 break;
 938         }
 939 }
 940
 941 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 942 {
 943         decode_configs(c);
 944         switch (c->processor_id & PRID_IMP_MASK) {
 945         case PRID_IMP_PR4450:
 946                 c->cputype = CPU_PR4450;
 947                 __cpu_name[cpu] = "Philips PR4450";
 948                 set_isa(c, MIPS_CPU_ISA_M32R1);
 949                 break;
 950         }
 951 }
 952
 953 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 954 {
 955         decode_configs(c);
 956         switch (c->processor_id & PRID_IMP_MASK) {
 957         case PRID_IMP_BMIPS32_REV4:
 958         case PRID_IMP_BMIPS32_REV8:
 959                 c->cputype = CPU_BMIPS32;
 960                 __cpu_name[cpu] = "Broadcom BMIPS32";
 961                 set_elf_platform(cpu, "bmips32");
 962                 break;
 963         case PRID_IMP_BMIPS3300:
 964         case PRID_IMP_BMIPS3300_ALT:
 965         case PRID_IMP_BMIPS3300_BUG:
 966                 c->cputype = CPU_BMIPS3300;
 967                 __cpu_name[cpu] = "Broadcom BMIPS3300";
 968                 set_elf_platform(cpu, "bmips3300");
 969                 break;
 970         case PRID_IMP_BMIPS43XX: {
 971                 int rev = c->processor_id & PRID_REV_MASK;
 972
 973                 if (rev >= PRID_REV_BMIPS4380_LO &&
 974                                 rev <= PRID_REV_BMIPS4380_HI) {
 975                         c->cputype = CPU_BMIPS4380;
 976                         __cpu_name[cpu] = "Broadcom BMIPS4380";
 977                         set_elf_platform(cpu, "bmips4380");
 978                 } else {
 979                         c->cputype = CPU_BMIPS4350;
 980                         __cpu_name[cpu] = "Broadcom BMIPS4350";
 981                         set_elf_platform(cpu, "bmips4350");
 982                 }
 983                 break;
 984         }
 985         case PRID_IMP_BMIPS5000:
 986                 c->cputype = CPU_BMIPS5000;
 987                 __cpu_name[cpu] = "Broadcom BMIPS5000";
 988                 set_elf_platform(cpu, "bmips5000");
 989                 c->options |= MIPS_CPU_ULRI;
 990                 break;
 991         }
 992 }
 993
 994 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 995 {
 996         decode_configs(c);
 997         switch (c->processor_id & PRID_IMP_MASK) {
 998         case PRID_IMP_CAVIUM_CN38XX:
 999         case PRID_IMP_CAVIUM_CN31XX:
1000         case PRID_IMP_CAVIUM_CN30XX:
1001                 c->cputype = CPU_CAVIUM_OCTEON;
1002                 __cpu_name[cpu] = "Cavium Octeon";
1003                 goto platform;
1004         case PRID_IMP_CAVIUM_CN58XX:
1005         case PRID_IMP_CAVIUM_CN56XX:
1006         case PRID_IMP_CAVIUM_CN50XX:
1007         case PRID_IMP_CAVIUM_CN52XX:
1008                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1009                 __cpu_name[cpu] = "Cavium Octeon+";
1010 platform:
1011                 set_elf_platform(cpu, "octeon");
1012                 break;
1013         case PRID_IMP_CAVIUM_CN61XX:
1014         case PRID_IMP_CAVIUM_CN63XX:
1015         case PRID_IMP_CAVIUM_CN66XX:
1016         case PRID_IMP_CAVIUM_CN68XX:
1017         case PRID_IMP_CAVIUM_CNF71XX:
1018                 c->cputype = CPU_CAVIUM_OCTEON2;
1019                 __cpu_name[cpu] = "Cavium Octeon II";
1020                 set_elf_platform(cpu, "octeon2");
1021                 break;
1022         case PRID_IMP_CAVIUM_CN70XX:
1023         case PRID_IMP_CAVIUM_CN78XX:
1024                 c->cputype = CPU_CAVIUM_OCTEON3;
1025                 __cpu_name[cpu] = "Cavium Octeon III";
1026                 set_elf_platform(cpu, "octeon3");
1027                 break;
1028         default:
1029                 printk(KERN_INFO "Unknown Octeon chip!\n");
1030                 c->cputype = CPU_UNKNOWN;
1031                 break;
1032         }
1033 }
1034
1035 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1036 {
1037         decode_configs(c);
1038         /* JZRISC does not implement the CP0 counter. */
1039         c->options &= ~MIPS_CPU_COUNTER;
1040         switch (c->processor_id & PRID_IMP_MASK) {
1041         case PRID_IMP_JZRISC:
1042                 c->cputype = CPU_JZRISC;
1043                 __cpu_name[cpu] = "Ingenic JZRISC";
1044                 break;
1045         default:
1046                 panic("Unknown Ingenic Processor ID!");
1047                 break;
1048         }
1049 }
1050
1051 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1052 {
1053         decode_configs(c);
1054
1055         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1056                 c->cputype = CPU_ALCHEMY;
1057                 __cpu_name[cpu] = "Au1300";
1058                 /* following stuff is not for Alchemy */
1059                 return;
1060         }
1061
1062         c->options = (MIPS_CPU_TLB       |
1063                         MIPS_CPU_4KEX    |
1064                         MIPS_CPU_COUNTER |
1065                         MIPS_CPU_DIVEC   |
1066                         MIPS_CPU_WATCH   |
1067                         MIPS_CPU_EJTAG   |
1068                         MIPS_CPU_LLSC);
1069
1070         switch (c->processor_id & PRID_IMP_MASK) {
1071         case PRID_IMP_NETLOGIC_XLP2XX:
1072         case PRID_IMP_NETLOGIC_XLP9XX:
1073                 c->cputype = CPU_XLP;
1074                 __cpu_name[cpu] = "Broadcom XLPII";
1075                 break;
1076
1077         case PRID_IMP_NETLOGIC_XLP8XX:
1078         case PRID_IMP_NETLOGIC_XLP3XX:
1079                 c->cputype = CPU_XLP;
1080                 __cpu_name[cpu] = "Netlogic XLP";
1081                 break;
1082
1083         case PRID_IMP_NETLOGIC_XLR732:
1084         case PRID_IMP_NETLOGIC_XLR716:
1085         case PRID_IMP_NETLOGIC_XLR532:
1086         case PRID_IMP_NETLOGIC_XLR308:
1087         case PRID_IMP_NETLOGIC_XLR532C:
1088         case PRID_IMP_NETLOGIC_XLR516C:
1089         case PRID_IMP_NETLOGIC_XLR508C:
1090         case PRID_IMP_NETLOGIC_XLR308C:
1091                 c->cputype = CPU_XLR;
1092                 __cpu_name[cpu] = "Netlogic XLR";
1093                 break;
1094
1095         case PRID_IMP_NETLOGIC_XLS608:
1096         case PRID_IMP_NETLOGIC_XLS408:
1097         case PRID_IMP_NETLOGIC_XLS404:
1098         case PRID_IMP_NETLOGIC_XLS208:
1099         case PRID_IMP_NETLOGIC_XLS204:
1100         case PRID_IMP_NETLOGIC_XLS108:
1101         case PRID_IMP_NETLOGIC_XLS104:
1102         case PRID_IMP_NETLOGIC_XLS616B:
1103         case PRID_IMP_NETLOGIC_XLS608B:
1104         case PRID_IMP_NETLOGIC_XLS416B:
1105         case PRID_IMP_NETLOGIC_XLS412B:
1106         case PRID_IMP_NETLOGIC_XLS408B:
1107         case PRID_IMP_NETLOGIC_XLS404B:
1108                 c->cputype = CPU_XLR;
1109                 __cpu_name[cpu] = "Netlogic XLS";
1110                 break;
1111
1112         default:
1113                 pr_info("Unknown Netlogic chip id [%02x]!\n",
1114                        c->processor_id);
1115                 c->cputype = CPU_XLR;
1116                 break;
1117         }
1118
1119         if (c->cputype == CPU_XLP) {
1120                 set_isa(c, MIPS_CPU_ISA_M64R2);
1121                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1122                 /* This will be updated again after all threads are woken up */
1123                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1124         } else {
1125                 set_isa(c, MIPS_CPU_ISA_M64R1);
1126                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1127         }
1128         c->kscratch_mask = 0xf;
1129 }
1130
1131 #ifdef CONFIG_64BIT
1132 /* For use by uaccess.h */
1133 u64 __ua_limit;
1134 EXPORT_SYMBOL(__ua_limit);
1135 #endif
1136
1137 const char *__cpu_name[NR_CPUS];
1138 const char *__elf_platform;
1139
1140 void cpu_probe(void)
1141 {
1142         struct cpuinfo_mips *c = &current_cpu_data;
1143         unsigned int cpu = smp_processor_id();
1144
1145         c->processor_id = PRID_IMP_UNKNOWN;
1146         c->fpu_id       = FPIR_IMP_NONE;
1147         c->cputype      = CPU_UNKNOWN;
1148
1149         c->processor_id = read_c0_prid();
1150         switch (c->processor_id & PRID_COMP_MASK) {
1151         case PRID_COMP_LEGACY:
1152                 cpu_probe_legacy(c, cpu);
1153                 break;
1154         case PRID_COMP_MIPS:
1155                 cpu_probe_mips(c, cpu);
1156                 break;
1157         case PRID_COMP_ALCHEMY:
1158                 cpu_probe_alchemy(c, cpu);
1159                 break;
1160         case PRID_COMP_SIBYTE:
1161                 cpu_probe_sibyte(c, cpu);
1162                 break;
1163         case PRID_COMP_BROADCOM:
1164                 cpu_probe_broadcom(c, cpu);
1165                 break;
1166         case PRID_COMP_SANDCRAFT:
1167                 cpu_probe_sandcraft(c, cpu);
1168                 break;
1169         case PRID_COMP_NXP:
1170                 cpu_probe_nxp(c, cpu);
1171                 break;
1172         case PRID_COMP_CAVIUM:
1173                 cpu_probe_cavium(c, cpu);
1174                 break;
1175         case PRID_COMP_INGENIC:
1176                 cpu_probe_ingenic(c, cpu);
1177                 break;
1178         case PRID_COMP_NETLOGIC:
1179                 cpu_probe_netlogic(c, cpu);
1180                 break;
1181         }
1182
1183         BUG_ON(!__cpu_name[cpu]);
1184         BUG_ON(c->cputype == CPU_UNKNOWN);
1185
1186         /*
1187          * Platform code can force the cpu type to optimize code
1188          * generation. In that case be sure the cpu type is correctly
1189          * manually setup otherwise it could trigger some nasty bugs.
1190          */
1191         BUG_ON(current_cpu_type() != c->cputype);
1192
1193         if (mips_fpu_disabled)
1194                 c->options &= ~MIPS_CPU_FPU;
1195
1196         if (mips_dsp_disabled)
1197                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1198
1199         if (c->options & MIPS_CPU_FPU) {
1200                 c->fpu_id = cpu_get_fpu_id();
1201
1202                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1203                                     MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1204                         if (c->fpu_id & MIPS_FPIR_3D)
1205                                 c->ases |= MIPS_ASE_MIPS3D;
1206                 }
1207         }
1208
1209         if (cpu_has_mips_r2) {
1210                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1211                 /* R2 has Performance Counter Interrupt indicator */
1212                 c->options |= MIPS_CPU_PCI;
1213         }
1214         else
1215                 c->srsets = 1;
1216
1217         if (cpu_has_msa) {
1218                 c->msa_id = cpu_get_msa_id();
1219                 WARN(c->msa_id & MSA_IR_WRPF,
1220                      "Vector register partitioning unimplemented!");
1221         }
1222
1223         cpu_probe_vmbits(c);
1224
1225 #ifdef CONFIG_64BIT
1226         if (cpu == 0)
1227                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1228 #endif
1229 }
1230
1231 void cpu_report(void)
1232 {
1233         struct cpuinfo_mips *c = &current_cpu_data;
1234
1235         pr_info("CPU%d revision is: %08x (%s)\n",
1236                 smp_processor_id(), c->processor_id, cpu_name_string());
1237         if (c->options & MIPS_CPU_FPU)
1238                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1239         if (cpu_has_msa)
1240                 pr_info("MSA revision is: %08x\n", c->msa_id);
1241 }