2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-type.h>
25 #include <asm/mipsregs.h>
26 #include <asm/watch.h>
28 #include <asm/spram.h>
29 #include <asm/uaccess.h>
31 static int mips_fpu_disabled;
33 static int __init fpu_disable(char *s)
35 cpu_data[0].options &= ~MIPS_CPU_FPU;
36 mips_fpu_disabled = 1;
41 __setup("nofpu", fpu_disable);
43 int mips_dsp_disabled;
45 static int __init dsp_disable(char *s)
47 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
48 mips_dsp_disabled = 1;
53 __setup("nodsp", dsp_disable);
55 static inline void check_errata(void)
57 struct cpuinfo_mips *c = ¤t_cpu_data;
59 switch (current_cpu_type()) {
62 * Erratum "RPS May Cause Incorrect Instruction Execution"
63 * This code only handles VPE0, any SMP/SMTC/RTOS code
64 * making use of VPE1 will be responsable for that VPE.
66 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
67 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
74 void __init check_bugs32(void)
80 * Probe whether cpu has config register by trying to play with
81 * alternate cache bit and see whether it matters.
82 * It's used by cpu_probe to distinguish between R3000A and R3081.
84 static inline int cpu_has_confreg(void)
86 #ifdef CONFIG_CPU_R3000
87 extern unsigned long r3k_cache_size(unsigned long);
88 unsigned long size1, size2;
89 unsigned long cfg = read_c0_conf();
91 size1 = r3k_cache_size(ST0_ISC);
92 write_c0_conf(cfg ^ R30XX_CONF_AC);
93 size2 = r3k_cache_size(ST0_ISC);
95 return size1 != size2;
101 static inline void set_elf_platform(int cpu, const char *plat)
104 __elf_platform = plat;
108 * Get the FPU Implementation/Revision.
110 static inline unsigned long cpu_get_fpu_id(void)
112 unsigned long tmp, fpu_id;
114 tmp = read_c0_status();
115 __enable_fpu(FPU_AS_IS);
116 fpu_id = read_32bit_cp1_register(CP1_REVISION);
117 write_c0_status(tmp);
122 * Check the CPU has an FPU the official way.
124 static inline int __cpu_has_fpu(void)
126 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
129 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
131 #ifdef __NEED_VMBITS_PROBE
132 write_c0_entryhi(0x3fffffffffffe000ULL);
133 back_to_back_c0_hazard();
134 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
138 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
141 case MIPS_CPU_ISA_M64R2:
142 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
143 case MIPS_CPU_ISA_M64R1:
144 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
146 c->isa_level |= MIPS_CPU_ISA_V;
147 case MIPS_CPU_ISA_IV:
148 c->isa_level |= MIPS_CPU_ISA_IV;
149 case MIPS_CPU_ISA_III:
150 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
153 case MIPS_CPU_ISA_M32R2:
154 c->isa_level |= MIPS_CPU_ISA_M32R2;
155 case MIPS_CPU_ISA_M32R1:
156 c->isa_level |= MIPS_CPU_ISA_M32R1;
157 case MIPS_CPU_ISA_II:
158 c->isa_level |= MIPS_CPU_ISA_II;
163 static char unknown_isa[] = KERN_ERR \
164 "Unsupported ISA type, c0.config0: %d.";
166 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
168 unsigned int config6;
170 * Config6 is implementation dependent and it's currently only
173 if (c->cputype == CPU_PROAPTIV) {
174 config6 = read_c0_config6();
177 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
180 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
181 back_to_back_c0_hazard();
185 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
187 unsigned int config0;
190 config0 = read_c0_config();
193 * Look for Standard TLB or Dual VTLB and FTLB
195 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
196 (((config0 & MIPS_CONF_MT) >> 7) == 4))
197 c->options |= MIPS_CPU_TLB;
199 isa = (config0 & MIPS_CONF_AT) >> 13;
202 switch ((config0 & MIPS_CONF_AR) >> 10) {
204 set_isa(c, MIPS_CPU_ISA_M32R1);
207 set_isa(c, MIPS_CPU_ISA_M32R2);
214 switch ((config0 & MIPS_CONF_AR) >> 10) {
216 set_isa(c, MIPS_CPU_ISA_M64R1);
219 set_isa(c, MIPS_CPU_ISA_M64R2);
229 return config0 & MIPS_CONF_M;
232 panic(unknown_isa, config0);
235 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
237 unsigned int config1;
239 config1 = read_c0_config1();
241 if (config1 & MIPS_CONF1_MD)
242 c->ases |= MIPS_ASE_MDMX;
243 if (config1 & MIPS_CONF1_WR)
244 c->options |= MIPS_CPU_WATCH;
245 if (config1 & MIPS_CONF1_CA)
246 c->ases |= MIPS_ASE_MIPS16;
247 if (config1 & MIPS_CONF1_EP)
248 c->options |= MIPS_CPU_EJTAG;
249 if (config1 & MIPS_CONF1_FP) {
250 c->options |= MIPS_CPU_FPU;
251 c->options |= MIPS_CPU_32FPR;
254 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
255 c->tlbsizevtlb = c->tlbsize;
256 c->tlbsizeftlbsets = 0;
259 return config1 & MIPS_CONF_M;
262 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
264 unsigned int config2;
266 config2 = read_c0_config2();
268 if (config2 & MIPS_CONF2_SL)
269 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
271 return config2 & MIPS_CONF_M;
274 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
276 unsigned int config3;
278 config3 = read_c0_config3();
280 if (config3 & MIPS_CONF3_SM) {
281 c->ases |= MIPS_ASE_SMARTMIPS;
282 c->options |= MIPS_CPU_RIXI;
284 if (config3 & MIPS_CONF3_RXI)
285 c->options |= MIPS_CPU_RIXI;
286 if (config3 & MIPS_CONF3_DSP)
287 c->ases |= MIPS_ASE_DSP;
288 if (config3 & MIPS_CONF3_DSP2P)
289 c->ases |= MIPS_ASE_DSP2P;
290 if (config3 & MIPS_CONF3_VINT)
291 c->options |= MIPS_CPU_VINT;
292 if (config3 & MIPS_CONF3_VEIC)
293 c->options |= MIPS_CPU_VEIC;
294 if (config3 & MIPS_CONF3_MT)
295 c->ases |= MIPS_ASE_MIPSMT;
296 if (config3 & MIPS_CONF3_ULRI)
297 c->options |= MIPS_CPU_ULRI;
298 if (config3 & MIPS_CONF3_ISA)
299 c->options |= MIPS_CPU_MICROMIPS;
300 if (config3 & MIPS_CONF3_VZ)
301 c->ases |= MIPS_ASE_VZ;
302 if (config3 & MIPS_CONF3_SC)
303 c->options |= MIPS_CPU_SEGMENTS;
305 return config3 & MIPS_CONF_M;
308 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
310 unsigned int config4;
312 unsigned int mmuextdef;
313 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
315 config4 = read_c0_config4();
318 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
319 c->options |= MIPS_CPU_TLBINV;
320 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
322 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
323 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
324 c->tlbsizevtlb = c->tlbsize;
326 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
328 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
329 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
330 c->tlbsize = c->tlbsizevtlb;
331 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
333 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
334 newcf4 = (config4 & ~ftlb_page) |
335 (page_size_ftlb(mmuextdef) <<
336 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
337 write_c0_config4(newcf4);
338 back_to_back_c0_hazard();
339 config4 = read_c0_config4();
340 if (config4 != newcf4) {
341 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
343 /* Switch FTLB off */
344 set_ftlb_enable(c, 0);
347 c->tlbsizeftlbsets = 1 <<
348 ((config4 & MIPS_CONF4_FTLBSETS) >>
349 MIPS_CONF4_FTLBSETS_SHIFT);
350 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
351 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
352 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
357 c->kscratch_mask = (config4 >> 16) & 0xff;
359 return config4 & MIPS_CONF_M;
362 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
364 unsigned int config5;
366 config5 = read_c0_config5();
367 config5 &= ~MIPS_CONF5_UFR;
368 write_c0_config5(config5);
370 return config5 & MIPS_CONF_M;
373 static void decode_configs(struct cpuinfo_mips *c)
377 /* MIPS32 or MIPS64 compliant CPU. */
378 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
379 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
381 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
383 /* Enable FTLB if present */
384 set_ftlb_enable(c, 1);
386 ok = decode_config0(c); /* Read Config registers. */
387 BUG_ON(!ok); /* Arch spec violation! */
389 ok = decode_config1(c);
391 ok = decode_config2(c);
393 ok = decode_config3(c);
395 ok = decode_config4(c);
397 ok = decode_config5(c);
399 mips_probe_watch_registers(c);
401 #ifndef CONFIG_MIPS_CPS
403 c->core = read_c0_ebase() & 0x3ff;
407 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
410 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
412 switch (c->processor_id & PRID_IMP_MASK) {
414 c->cputype = CPU_R2000;
415 __cpu_name[cpu] = "R2000";
416 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
419 c->options |= MIPS_CPU_FPU;
423 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
424 if (cpu_has_confreg()) {
425 c->cputype = CPU_R3081E;
426 __cpu_name[cpu] = "R3081";
428 c->cputype = CPU_R3000A;
429 __cpu_name[cpu] = "R3000A";
432 c->cputype = CPU_R3000;
433 __cpu_name[cpu] = "R3000";
435 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
438 c->options |= MIPS_CPU_FPU;
442 if (read_c0_config() & CONF_SC) {
443 if ((c->processor_id & PRID_REV_MASK) >=
445 c->cputype = CPU_R4400PC;
446 __cpu_name[cpu] = "R4400PC";
448 c->cputype = CPU_R4000PC;
449 __cpu_name[cpu] = "R4000PC";
452 int cca = read_c0_config() & CONF_CM_CMASK;
456 * SC and MC versions can't be reliably told apart,
457 * but only the latter support coherent caching
458 * modes so assume the firmware has set the KSEG0
459 * coherency attribute reasonably (if uncached, we
463 case CONF_CM_CACHABLE_CE:
464 case CONF_CM_CACHABLE_COW:
465 case CONF_CM_CACHABLE_CUW:
472 if ((c->processor_id & PRID_REV_MASK) >=
474 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
475 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
477 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
478 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
482 set_isa(c, MIPS_CPU_ISA_III);
483 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
484 MIPS_CPU_WATCH | MIPS_CPU_VCE |
488 case PRID_IMP_VR41XX:
489 set_isa(c, MIPS_CPU_ISA_III);
490 c->options = R4K_OPTS;
492 switch (c->processor_id & 0xf0) {
493 case PRID_REV_VR4111:
494 c->cputype = CPU_VR4111;
495 __cpu_name[cpu] = "NEC VR4111";
497 case PRID_REV_VR4121:
498 c->cputype = CPU_VR4121;
499 __cpu_name[cpu] = "NEC VR4121";
501 case PRID_REV_VR4122:
502 if ((c->processor_id & 0xf) < 0x3) {
503 c->cputype = CPU_VR4122;
504 __cpu_name[cpu] = "NEC VR4122";
506 c->cputype = CPU_VR4181A;
507 __cpu_name[cpu] = "NEC VR4181A";
510 case PRID_REV_VR4130:
511 if ((c->processor_id & 0xf) < 0x4) {
512 c->cputype = CPU_VR4131;
513 __cpu_name[cpu] = "NEC VR4131";
515 c->cputype = CPU_VR4133;
516 c->options |= MIPS_CPU_LLSC;
517 __cpu_name[cpu] = "NEC VR4133";
521 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
522 c->cputype = CPU_VR41XX;
523 __cpu_name[cpu] = "NEC Vr41xx";
528 c->cputype = CPU_R4300;
529 __cpu_name[cpu] = "R4300";
530 set_isa(c, MIPS_CPU_ISA_III);
531 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
536 c->cputype = CPU_R4600;
537 __cpu_name[cpu] = "R4600";
538 set_isa(c, MIPS_CPU_ISA_III);
539 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
546 * This processor doesn't have an MMU, so it's not
547 * "real easy" to run Linux on it. It is left purely
548 * for documentation. Commented out because it shares
549 * it's c0_prid id number with the TX3900.
551 c->cputype = CPU_R4650;
552 __cpu_name[cpu] = "R4650";
553 set_isa(c, MIPS_CPU_ISA_III);
554 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
559 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
561 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
562 c->cputype = CPU_TX3927;
563 __cpu_name[cpu] = "TX3927";
566 switch (c->processor_id & PRID_REV_MASK) {
567 case PRID_REV_TX3912:
568 c->cputype = CPU_TX3912;
569 __cpu_name[cpu] = "TX3912";
572 case PRID_REV_TX3922:
573 c->cputype = CPU_TX3922;
574 __cpu_name[cpu] = "TX3922";
581 c->cputype = CPU_R4700;
582 __cpu_name[cpu] = "R4700";
583 set_isa(c, MIPS_CPU_ISA_III);
584 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
589 c->cputype = CPU_TX49XX;
590 __cpu_name[cpu] = "R49XX";
591 set_isa(c, MIPS_CPU_ISA_III);
592 c->options = R4K_OPTS | MIPS_CPU_LLSC;
593 if (!(c->processor_id & 0x08))
594 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
598 c->cputype = CPU_R5000;
599 __cpu_name[cpu] = "R5000";
600 set_isa(c, MIPS_CPU_ISA_IV);
601 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
606 c->cputype = CPU_R5432;
607 __cpu_name[cpu] = "R5432";
608 set_isa(c, MIPS_CPU_ISA_IV);
609 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
610 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
614 c->cputype = CPU_R5500;
615 __cpu_name[cpu] = "R5500";
616 set_isa(c, MIPS_CPU_ISA_IV);
617 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
618 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
621 case PRID_IMP_NEVADA:
622 c->cputype = CPU_NEVADA;
623 __cpu_name[cpu] = "Nevada";
624 set_isa(c, MIPS_CPU_ISA_IV);
625 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
626 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
630 c->cputype = CPU_R6000;
631 __cpu_name[cpu] = "R6000";
632 set_isa(c, MIPS_CPU_ISA_II);
633 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
637 case PRID_IMP_R6000A:
638 c->cputype = CPU_R6000A;
639 __cpu_name[cpu] = "R6000A";
640 set_isa(c, MIPS_CPU_ISA_II);
641 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
645 case PRID_IMP_RM7000:
646 c->cputype = CPU_RM7000;
647 __cpu_name[cpu] = "RM7000";
648 set_isa(c, MIPS_CPU_ISA_IV);
649 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
652 * Undocumented RM7000: Bit 29 in the info register of
653 * the RM7000 v2.0 indicates if the TLB has 48 or 64
656 * 29 1 => 64 entry JTLB
659 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
661 case PRID_IMP_RM9000:
662 c->cputype = CPU_RM9000;
663 __cpu_name[cpu] = "RM9000";
664 set_isa(c, MIPS_CPU_ISA_IV);
665 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
668 * Bit 29 in the info register of the RM9000
669 * indicates if the TLB has 48 or 64 entries.
671 * 29 1 => 64 entry JTLB
674 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
677 c->cputype = CPU_R8000;
678 __cpu_name[cpu] = "RM8000";
679 set_isa(c, MIPS_CPU_ISA_IV);
680 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
681 MIPS_CPU_FPU | MIPS_CPU_32FPR |
683 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
685 case PRID_IMP_R10000:
686 c->cputype = CPU_R10000;
687 __cpu_name[cpu] = "R10000";
688 set_isa(c, MIPS_CPU_ISA_IV);
689 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
690 MIPS_CPU_FPU | MIPS_CPU_32FPR |
691 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
695 case PRID_IMP_R12000:
696 c->cputype = CPU_R12000;
697 __cpu_name[cpu] = "R12000";
698 set_isa(c, MIPS_CPU_ISA_IV);
699 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
700 MIPS_CPU_FPU | MIPS_CPU_32FPR |
701 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
705 case PRID_IMP_R14000:
706 c->cputype = CPU_R14000;
707 __cpu_name[cpu] = "R14000";
708 set_isa(c, MIPS_CPU_ISA_IV);
709 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
710 MIPS_CPU_FPU | MIPS_CPU_32FPR |
711 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
715 case PRID_IMP_LOONGSON2:
716 c->cputype = CPU_LOONGSON2;
717 __cpu_name[cpu] = "ICT Loongson-2";
719 switch (c->processor_id & PRID_REV_MASK) {
720 case PRID_REV_LOONGSON2E:
721 set_elf_platform(cpu, "loongson2e");
723 case PRID_REV_LOONGSON2F:
724 set_elf_platform(cpu, "loongson2f");
728 set_isa(c, MIPS_CPU_ISA_III);
729 c->options = R4K_OPTS |
730 MIPS_CPU_FPU | MIPS_CPU_LLSC |
734 case PRID_IMP_LOONGSON1:
737 c->cputype = CPU_LOONGSON1;
739 switch (c->processor_id & PRID_REV_MASK) {
740 case PRID_REV_LOONGSON1B:
741 __cpu_name[cpu] = "Loongson 1B";
749 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
751 switch (c->processor_id & PRID_IMP_MASK) {
753 c->cputype = CPU_4KC;
754 __cpu_name[cpu] = "MIPS 4Kc";
757 case PRID_IMP_4KECR2:
758 c->cputype = CPU_4KEC;
759 __cpu_name[cpu] = "MIPS 4KEc";
763 c->cputype = CPU_4KSC;
764 __cpu_name[cpu] = "MIPS 4KSc";
767 c->cputype = CPU_5KC;
768 __cpu_name[cpu] = "MIPS 5Kc";
771 c->cputype = CPU_5KE;
772 __cpu_name[cpu] = "MIPS 5KE";
775 c->cputype = CPU_20KC;
776 __cpu_name[cpu] = "MIPS 20Kc";
779 c->cputype = CPU_24K;
780 __cpu_name[cpu] = "MIPS 24Kc";
783 c->cputype = CPU_24K;
784 __cpu_name[cpu] = "MIPS 24KEc";
787 c->cputype = CPU_25KF;
788 __cpu_name[cpu] = "MIPS 25Kc";
791 c->cputype = CPU_34K;
792 __cpu_name[cpu] = "MIPS 34Kc";
795 c->cputype = CPU_74K;
796 __cpu_name[cpu] = "MIPS 74Kc";
799 c->cputype = CPU_M14KC;
800 __cpu_name[cpu] = "MIPS M14Kc";
802 case PRID_IMP_M14KEC:
803 c->cputype = CPU_M14KEC;
804 __cpu_name[cpu] = "MIPS M14KEc";
807 c->cputype = CPU_1004K;
808 __cpu_name[cpu] = "MIPS 1004Kc";
811 c->cputype = CPU_1074K;
812 __cpu_name[cpu] = "MIPS 1074Kc";
814 case PRID_IMP_INTERAPTIV_UP:
815 c->cputype = CPU_INTERAPTIV;
816 __cpu_name[cpu] = "MIPS interAptiv";
818 case PRID_IMP_INTERAPTIV_MP:
819 c->cputype = CPU_INTERAPTIV;
820 __cpu_name[cpu] = "MIPS interAptiv (multi)";
822 case PRID_IMP_PROAPTIV_UP:
823 c->cputype = CPU_PROAPTIV;
824 __cpu_name[cpu] = "MIPS proAptiv";
826 case PRID_IMP_PROAPTIV_MP:
827 c->cputype = CPU_PROAPTIV;
828 __cpu_name[cpu] = "MIPS proAptiv (multi)";
837 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
840 switch (c->processor_id & PRID_IMP_MASK) {
841 case PRID_IMP_AU1_REV1:
842 case PRID_IMP_AU1_REV2:
843 c->cputype = CPU_ALCHEMY;
844 switch ((c->processor_id >> 24) & 0xff) {
846 __cpu_name[cpu] = "Au1000";
849 __cpu_name[cpu] = "Au1500";
852 __cpu_name[cpu] = "Au1100";
855 __cpu_name[cpu] = "Au1550";
858 __cpu_name[cpu] = "Au1200";
859 if ((c->processor_id & PRID_REV_MASK) == 2)
860 __cpu_name[cpu] = "Au1250";
863 __cpu_name[cpu] = "Au1210";
866 __cpu_name[cpu] = "Au1xxx";
873 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
877 switch (c->processor_id & PRID_IMP_MASK) {
879 c->cputype = CPU_SB1;
880 __cpu_name[cpu] = "SiByte SB1";
881 /* FPU in pass1 is known to have issues. */
882 if ((c->processor_id & PRID_REV_MASK) < 0x02)
883 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
886 c->cputype = CPU_SB1A;
887 __cpu_name[cpu] = "SiByte SB1A";
892 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
895 switch (c->processor_id & PRID_IMP_MASK) {
896 case PRID_IMP_SR71000:
897 c->cputype = CPU_SR71000;
898 __cpu_name[cpu] = "Sandcraft SR71000";
905 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
908 switch (c->processor_id & PRID_IMP_MASK) {
909 case PRID_IMP_PR4450:
910 c->cputype = CPU_PR4450;
911 __cpu_name[cpu] = "Philips PR4450";
912 set_isa(c, MIPS_CPU_ISA_M32R1);
917 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
920 switch (c->processor_id & PRID_IMP_MASK) {
921 case PRID_IMP_BMIPS32_REV4:
922 case PRID_IMP_BMIPS32_REV8:
923 c->cputype = CPU_BMIPS32;
924 __cpu_name[cpu] = "Broadcom BMIPS32";
925 set_elf_platform(cpu, "bmips32");
927 case PRID_IMP_BMIPS3300:
928 case PRID_IMP_BMIPS3300_ALT:
929 case PRID_IMP_BMIPS3300_BUG:
930 c->cputype = CPU_BMIPS3300;
931 __cpu_name[cpu] = "Broadcom BMIPS3300";
932 set_elf_platform(cpu, "bmips3300");
934 case PRID_IMP_BMIPS43XX: {
935 int rev = c->processor_id & PRID_REV_MASK;
937 if (rev >= PRID_REV_BMIPS4380_LO &&
938 rev <= PRID_REV_BMIPS4380_HI) {
939 c->cputype = CPU_BMIPS4380;
940 __cpu_name[cpu] = "Broadcom BMIPS4380";
941 set_elf_platform(cpu, "bmips4380");
943 c->cputype = CPU_BMIPS4350;
944 __cpu_name[cpu] = "Broadcom BMIPS4350";
945 set_elf_platform(cpu, "bmips4350");
949 case PRID_IMP_BMIPS5000:
950 c->cputype = CPU_BMIPS5000;
951 __cpu_name[cpu] = "Broadcom BMIPS5000";
952 set_elf_platform(cpu, "bmips5000");
953 c->options |= MIPS_CPU_ULRI;
958 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
961 switch (c->processor_id & PRID_IMP_MASK) {
962 case PRID_IMP_CAVIUM_CN38XX:
963 case PRID_IMP_CAVIUM_CN31XX:
964 case PRID_IMP_CAVIUM_CN30XX:
965 c->cputype = CPU_CAVIUM_OCTEON;
966 __cpu_name[cpu] = "Cavium Octeon";
968 case PRID_IMP_CAVIUM_CN58XX:
969 case PRID_IMP_CAVIUM_CN56XX:
970 case PRID_IMP_CAVIUM_CN50XX:
971 case PRID_IMP_CAVIUM_CN52XX:
972 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
973 __cpu_name[cpu] = "Cavium Octeon+";
975 set_elf_platform(cpu, "octeon");
977 case PRID_IMP_CAVIUM_CN61XX:
978 case PRID_IMP_CAVIUM_CN63XX:
979 case PRID_IMP_CAVIUM_CN66XX:
980 case PRID_IMP_CAVIUM_CN68XX:
981 case PRID_IMP_CAVIUM_CNF71XX:
982 c->cputype = CPU_CAVIUM_OCTEON2;
983 __cpu_name[cpu] = "Cavium Octeon II";
984 set_elf_platform(cpu, "octeon2");
986 case PRID_IMP_CAVIUM_CN70XX:
987 case PRID_IMP_CAVIUM_CN78XX:
988 c->cputype = CPU_CAVIUM_OCTEON3;
989 __cpu_name[cpu] = "Cavium Octeon III";
990 set_elf_platform(cpu, "octeon3");
993 printk(KERN_INFO "Unknown Octeon chip!\n");
994 c->cputype = CPU_UNKNOWN;
999 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1002 /* JZRISC does not implement the CP0 counter. */
1003 c->options &= ~MIPS_CPU_COUNTER;
1004 switch (c->processor_id & PRID_IMP_MASK) {
1005 case PRID_IMP_JZRISC:
1006 c->cputype = CPU_JZRISC;
1007 __cpu_name[cpu] = "Ingenic JZRISC";
1010 panic("Unknown Ingenic Processor ID!");
1015 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1019 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1020 c->cputype = CPU_ALCHEMY;
1021 __cpu_name[cpu] = "Au1300";
1022 /* following stuff is not for Alchemy */
1026 c->options = (MIPS_CPU_TLB |
1034 switch (c->processor_id & PRID_IMP_MASK) {
1035 case PRID_IMP_NETLOGIC_XLP2XX:
1036 case PRID_IMP_NETLOGIC_XLP9XX:
1037 c->cputype = CPU_XLP;
1038 __cpu_name[cpu] = "Broadcom XLPII";
1041 case PRID_IMP_NETLOGIC_XLP8XX:
1042 case PRID_IMP_NETLOGIC_XLP3XX:
1043 c->cputype = CPU_XLP;
1044 __cpu_name[cpu] = "Netlogic XLP";
1047 case PRID_IMP_NETLOGIC_XLR732:
1048 case PRID_IMP_NETLOGIC_XLR716:
1049 case PRID_IMP_NETLOGIC_XLR532:
1050 case PRID_IMP_NETLOGIC_XLR308:
1051 case PRID_IMP_NETLOGIC_XLR532C:
1052 case PRID_IMP_NETLOGIC_XLR516C:
1053 case PRID_IMP_NETLOGIC_XLR508C:
1054 case PRID_IMP_NETLOGIC_XLR308C:
1055 c->cputype = CPU_XLR;
1056 __cpu_name[cpu] = "Netlogic XLR";
1059 case PRID_IMP_NETLOGIC_XLS608:
1060 case PRID_IMP_NETLOGIC_XLS408:
1061 case PRID_IMP_NETLOGIC_XLS404:
1062 case PRID_IMP_NETLOGIC_XLS208:
1063 case PRID_IMP_NETLOGIC_XLS204:
1064 case PRID_IMP_NETLOGIC_XLS108:
1065 case PRID_IMP_NETLOGIC_XLS104:
1066 case PRID_IMP_NETLOGIC_XLS616B:
1067 case PRID_IMP_NETLOGIC_XLS608B:
1068 case PRID_IMP_NETLOGIC_XLS416B:
1069 case PRID_IMP_NETLOGIC_XLS412B:
1070 case PRID_IMP_NETLOGIC_XLS408B:
1071 case PRID_IMP_NETLOGIC_XLS404B:
1072 c->cputype = CPU_XLR;
1073 __cpu_name[cpu] = "Netlogic XLS";
1077 pr_info("Unknown Netlogic chip id [%02x]!\n",
1079 c->cputype = CPU_XLR;
1083 if (c->cputype == CPU_XLP) {
1084 set_isa(c, MIPS_CPU_ISA_M64R2);
1085 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1086 /* This will be updated again after all threads are woken up */
1087 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1089 set_isa(c, MIPS_CPU_ISA_M64R1);
1090 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1092 c->kscratch_mask = 0xf;
1096 /* For use by uaccess.h */
1098 EXPORT_SYMBOL(__ua_limit);
1101 const char *__cpu_name[NR_CPUS];
1102 const char *__elf_platform;
1104 void cpu_probe(void)
1106 struct cpuinfo_mips *c = ¤t_cpu_data;
1107 unsigned int cpu = smp_processor_id();
1109 c->processor_id = PRID_IMP_UNKNOWN;
1110 c->fpu_id = FPIR_IMP_NONE;
1111 c->cputype = CPU_UNKNOWN;
1113 c->processor_id = read_c0_prid();
1114 switch (c->processor_id & PRID_COMP_MASK) {
1115 case PRID_COMP_LEGACY:
1116 cpu_probe_legacy(c, cpu);
1118 case PRID_COMP_MIPS:
1119 cpu_probe_mips(c, cpu);
1121 case PRID_COMP_ALCHEMY:
1122 cpu_probe_alchemy(c, cpu);
1124 case PRID_COMP_SIBYTE:
1125 cpu_probe_sibyte(c, cpu);
1127 case PRID_COMP_BROADCOM:
1128 cpu_probe_broadcom(c, cpu);
1130 case PRID_COMP_SANDCRAFT:
1131 cpu_probe_sandcraft(c, cpu);
1134 cpu_probe_nxp(c, cpu);
1136 case PRID_COMP_CAVIUM:
1137 cpu_probe_cavium(c, cpu);
1139 case PRID_COMP_INGENIC:
1140 cpu_probe_ingenic(c, cpu);
1142 case PRID_COMP_NETLOGIC:
1143 cpu_probe_netlogic(c, cpu);
1147 BUG_ON(!__cpu_name[cpu]);
1148 BUG_ON(c->cputype == CPU_UNKNOWN);
1151 * Platform code can force the cpu type to optimize code
1152 * generation. In that case be sure the cpu type is correctly
1153 * manually setup otherwise it could trigger some nasty bugs.
1155 BUG_ON(current_cpu_type() != c->cputype);
1157 if (mips_fpu_disabled)
1158 c->options &= ~MIPS_CPU_FPU;
1160 if (mips_dsp_disabled)
1161 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1163 if (c->options & MIPS_CPU_FPU) {
1164 c->fpu_id = cpu_get_fpu_id();
1166 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1167 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1168 if (c->fpu_id & MIPS_FPIR_3D)
1169 c->ases |= MIPS_ASE_MIPS3D;
1173 if (cpu_has_mips_r2) {
1174 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1175 /* R2 has Performance Counter Interrupt indicator */
1176 c->options |= MIPS_CPU_PCI;
1181 cpu_probe_vmbits(c);
1185 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1189 void cpu_report(void)
1191 struct cpuinfo_mips *c = ¤t_cpu_data;
1193 pr_info("CPU%d revision is: %08x (%s)\n",
1194 smp_processor_id(), c->processor_id, cpu_name_string());
1195 if (c->options & MIPS_CPU_FPU)
1196 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);