arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-type.h>
  24 #include <asm/fpu.h>
  25 #include <asm/mipsregs.h>
  26 #include <asm/watch.h>
  27 #include <asm/elf.h>
  28 #include <asm/spram.h>
  29 #include <asm/uaccess.h>
  30
  31 static int mips_fpu_disabled;
  32
  33 static int __init fpu_disable(char *s)
  34 {
  35         cpu_data[0].options &= ~MIPS_CPU_FPU;
  36         mips_fpu_disabled = 1;
  37
  38         return 1;
  39 }
  40
  41 __setup("nofpu", fpu_disable);
  42
  43 int mips_dsp_disabled;
  44
  45 static int __init dsp_disable(char *s)
  46 {
  47         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
  48         mips_dsp_disabled = 1;
  49
  50         return 1;
  51 }
  52
  53 __setup("nodsp", dsp_disable);
  54
  55 static inline void check_errata(void)
  56 {
  57         struct cpuinfo_mips *c = &current_cpu_data;
  58
  59         switch (current_cpu_type()) {
  60         case CPU_34K:
  61                 /*
  62                  * Erratum "RPS May Cause Incorrect Instruction Execution"
  63                  * This code only handles VPE0, any SMP/SMTC/RTOS code
  64                  * making use of VPE1 will be responsable for that VPE.
  65                  */
  66                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
  67                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
  68                 break;
  69         default:
  70                 break;
  71         }
  72 }
  73
  74 void __init check_bugs32(void)
  75 {
  76         check_errata();
  77 }
  78
  79 /*
  80  * Probe whether cpu has config register by trying to play with
  81  * alternate cache bit and see whether it matters.
  82  * It's used by cpu_probe to distinguish between R3000A and R3081.
  83  */
  84 static inline int cpu_has_confreg(void)
  85 {
  86 #ifdef CONFIG_CPU_R3000
  87         extern unsigned long r3k_cache_size(unsigned long);
  88         unsigned long size1, size2;
  89         unsigned long cfg = read_c0_conf();
  90
  91         size1 = r3k_cache_size(ST0_ISC);
  92         write_c0_conf(cfg ^ R30XX_CONF_AC);
  93         size2 = r3k_cache_size(ST0_ISC);
  94         write_c0_conf(cfg);
  95         return size1 != size2;
  96 #else
  97         return 0;
  98 #endif
  99 }
 100
 101 static inline void set_elf_platform(int cpu, const char *plat)
 102 {
 103         if (cpu == 0)
 104                 __elf_platform = plat;
 105 }
 106
 107 /*
 108  * Get the FPU Implementation/Revision.
 109  */
 110 static inline unsigned long cpu_get_fpu_id(void)
 111 {
 112         unsigned long tmp, fpu_id;
 113
 114         tmp = read_c0_status();
 115         __enable_fpu(FPU_AS_IS);
 116         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 117         write_c0_status(tmp);
 118         return fpu_id;
 119 }
 120
 121 /*
 122  * Check the CPU has an FPU the official way.
 123  */
 124 static inline int __cpu_has_fpu(void)
 125 {
 126         return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
 127 }
 128
 129 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 130 {
 131 #ifdef __NEED_VMBITS_PROBE
 132         write_c0_entryhi(0x3fffffffffffe000ULL);
 133         back_to_back_c0_hazard();
 134         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 135 #endif
 136 }
 137
 138 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 139 {
 140         switch (isa) {
 141         case MIPS_CPU_ISA_M64R2:
 142                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 143         case MIPS_CPU_ISA_M64R1:
 144                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 145         case MIPS_CPU_ISA_V:
 146                 c->isa_level |= MIPS_CPU_ISA_V;
 147         case MIPS_CPU_ISA_IV:
 148                 c->isa_level |= MIPS_CPU_ISA_IV;
 149         case MIPS_CPU_ISA_III:
 150                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 151                 break;
 152
 153         case MIPS_CPU_ISA_M32R2:
 154                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 155         case MIPS_CPU_ISA_M32R1:
 156                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 157         case MIPS_CPU_ISA_II:
 158                 c->isa_level |= MIPS_CPU_ISA_II;
 159                 break;
 160         }
 161 }
 162
 163 static char unknown_isa[] = KERN_ERR \
 164         "Unsupported ISA type, c0.config0: %d.";
 165
 166 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 167 {
 168         unsigned int config6;
 169         /*
 170          * Config6 is implementation dependent and it's currently only
 171          * used by proAptiv
 172          */
 173         if (c->cputype == CPU_PROAPTIV) {
 174                 config6 = read_c0_config6();
 175                 if (enable)
 176                         /* Enable FTLB */
 177                         write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
 178                 else
 179                         /* Disable FTLB */
 180                         write_c0_config6(config6 &  ~MIPS_CONF6_FTLBEN);
 181                 back_to_back_c0_hazard();
 182         }
 183 }
 184
 185 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 186 {
 187         unsigned int config0;
 188         int isa;
 189
 190         config0 = read_c0_config();
 191
 192         /*
 193          * Look for Standard TLB or Dual VTLB and FTLB
 194          */
 195         if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
 196             (((config0 & MIPS_CONF_MT) >> 7) == 4))
 197                 c->options |= MIPS_CPU_TLB;
 198
 199         isa = (config0 & MIPS_CONF_AT) >> 13;
 200         switch (isa) {
 201         case 0:
 202                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 203                 case 0:
 204                         set_isa(c, MIPS_CPU_ISA_M32R1);
 205                         break;
 206                 case 1:
 207                         set_isa(c, MIPS_CPU_ISA_M32R2);
 208                         break;
 209                 default:
 210                         goto unknown;
 211                 }
 212                 break;
 213         case 2:
 214                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 215                 case 0:
 216                         set_isa(c, MIPS_CPU_ISA_M64R1);
 217                         break;
 218                 case 1:
 219                         set_isa(c, MIPS_CPU_ISA_M64R2);
 220                         break;
 221                 default:
 222                         goto unknown;
 223                 }
 224                 break;
 225         default:
 226                 goto unknown;
 227         }
 228
 229         return config0 & MIPS_CONF_M;
 230
 231 unknown:
 232         panic(unknown_isa, config0);
 233 }
 234
 235 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 236 {
 237         unsigned int config1;
 238
 239         config1 = read_c0_config1();
 240
 241         if (config1 & MIPS_CONF1_MD)
 242                 c->ases |= MIPS_ASE_MDMX;
 243         if (config1 & MIPS_CONF1_WR)
 244                 c->options |= MIPS_CPU_WATCH;
 245         if (config1 & MIPS_CONF1_CA)
 246                 c->ases |= MIPS_ASE_MIPS16;
 247         if (config1 & MIPS_CONF1_EP)
 248                 c->options |= MIPS_CPU_EJTAG;
 249         if (config1 & MIPS_CONF1_FP) {
 250                 c->options |= MIPS_CPU_FPU;
 251                 c->options |= MIPS_CPU_32FPR;
 252         }
 253         if (cpu_has_tlb) {
 254                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 255                 c->tlbsizevtlb = c->tlbsize;
 256                 c->tlbsizeftlbsets = 0;
 257         }
 258
 259         return config1 & MIPS_CONF_M;
 260 }
 261
 262 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 263 {
 264         unsigned int config2;
 265
 266         config2 = read_c0_config2();
 267
 268         if (config2 & MIPS_CONF2_SL)
 269                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 270
 271         return config2 & MIPS_CONF_M;
 272 }
 273
 274 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 275 {
 276         unsigned int config3;
 277
 278         config3 = read_c0_config3();
 279
 280         if (config3 & MIPS_CONF3_SM) {
 281                 c->ases |= MIPS_ASE_SMARTMIPS;
 282                 c->options |= MIPS_CPU_RIXI;
 283         }
 284         if (config3 & MIPS_CONF3_RXI)
 285                 c->options |= MIPS_CPU_RIXI;
 286         if (config3 & MIPS_CONF3_DSP)
 287                 c->ases |= MIPS_ASE_DSP;
 288         if (config3 & MIPS_CONF3_DSP2P)
 289                 c->ases |= MIPS_ASE_DSP2P;
 290         if (config3 & MIPS_CONF3_VINT)
 291                 c->options |= MIPS_CPU_VINT;
 292         if (config3 & MIPS_CONF3_VEIC)
 293                 c->options |= MIPS_CPU_VEIC;
 294         if (config3 & MIPS_CONF3_MT)
 295                 c->ases |= MIPS_ASE_MIPSMT;
 296         if (config3 & MIPS_CONF3_ULRI)
 297                 c->options |= MIPS_CPU_ULRI;
 298         if (config3 & MIPS_CONF3_ISA)
 299                 c->options |= MIPS_CPU_MICROMIPS;
 300         if (config3 & MIPS_CONF3_VZ)
 301                 c->ases |= MIPS_ASE_VZ;
 302         if (config3 & MIPS_CONF3_SC)
 303                 c->options |= MIPS_CPU_SEGMENTS;
 304
 305         return config3 & MIPS_CONF_M;
 306 }
 307
 308 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 309 {
 310         unsigned int config4;
 311         unsigned int newcf4;
 312         unsigned int mmuextdef;
 313         unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 314
 315         config4 = read_c0_config4();
 316
 317         if (cpu_has_tlb) {
 318                 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
 319                         c->options |= MIPS_CPU_TLBINV;
 320                 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 321                 switch (mmuextdef) {
 322                 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
 323                         c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 324                         c->tlbsizevtlb = c->tlbsize;
 325                         break;
 326                 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
 327                         c->tlbsizevtlb +=
 328                                 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
 329                                   MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
 330                         c->tlbsize = c->tlbsizevtlb;
 331                         ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
 332                         /* fall through */
 333                 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
 334                         newcf4 = (config4 & ~ftlb_page) |
 335                                 (page_size_ftlb(mmuextdef) <<
 336                                  MIPS_CONF4_FTLBPAGESIZE_SHIFT);
 337                         write_c0_config4(newcf4);
 338                         back_to_back_c0_hazard();
 339                         config4 = read_c0_config4();
 340                         if (config4 != newcf4) {
 341                                 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
 342                                        PAGE_SIZE, config4);
 343                                 /* Switch FTLB off */
 344                                 set_ftlb_enable(c, 0);
 345                                 break;
 346                         }
 347                         c->tlbsizeftlbsets = 1 <<
 348                                 ((config4 & MIPS_CONF4_FTLBSETS) >>
 349                                  MIPS_CONF4_FTLBSETS_SHIFT);
 350                         c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
 351                                               MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
 352                         c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
 353                         break;
 354                 }
 355         }
 356
 357         c->kscratch_mask = (config4 >> 16) & 0xff;
 358
 359         return config4 & MIPS_CONF_M;
 360 }
 361
 362 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 363 {
 364         unsigned int config5;
 365
 366         config5 = read_c0_config5();
 367         config5 &= ~MIPS_CONF5_UFR;
 368         write_c0_config5(config5);
 369
 370         return config5 & MIPS_CONF_M;
 371 }
 372
 373 static void decode_configs(struct cpuinfo_mips *c)
 374 {
 375         int ok;
 376
 377         /* MIPS32 or MIPS64 compliant CPU.  */
 378         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 379                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 380
 381         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 382
 383         /* Enable FTLB if present */
 384         set_ftlb_enable(c, 1);
 385
 386         ok = decode_config0(c);                 /* Read Config registers.  */
 387         BUG_ON(!ok);                            /* Arch spec violation!  */
 388         if (ok)
 389                 ok = decode_config1(c);
 390         if (ok)
 391                 ok = decode_config2(c);
 392         if (ok)
 393                 ok = decode_config3(c);
 394         if (ok)
 395                 ok = decode_config4(c);
 396         if (ok)
 397                 ok = decode_config5(c);
 398
 399         mips_probe_watch_registers(c);
 400
 401 #ifndef CONFIG_MIPS_CPS
 402         if (cpu_has_mips_r2)
 403                 c->core = read_c0_ebase() & 0x3ff;
 404 #endif
 405 }
 406
 407 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 408                 | MIPS_CPU_COUNTER)
 409
 410 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 411 {
 412         switch (c->processor_id & PRID_IMP_MASK) {
 413         case PRID_IMP_R2000:
 414                 c->cputype = CPU_R2000;
 415                 __cpu_name[cpu] = "R2000";
 416                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 417                              MIPS_CPU_NOFPUEX;
 418                 if (__cpu_has_fpu())
 419                         c->options |= MIPS_CPU_FPU;
 420                 c->tlbsize = 64;
 421                 break;
 422         case PRID_IMP_R3000:
 423                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
 424                         if (cpu_has_confreg()) {
 425                                 c->cputype = CPU_R3081E;
 426                                 __cpu_name[cpu] = "R3081";
 427                         } else {
 428                                 c->cputype = CPU_R3000A;
 429                                 __cpu_name[cpu] = "R3000A";
 430                         }
 431                 } else {
 432                         c->cputype = CPU_R3000;
 433                         __cpu_name[cpu] = "R3000";
 434                 }
 435                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 436                              MIPS_CPU_NOFPUEX;
 437                 if (__cpu_has_fpu())
 438                         c->options |= MIPS_CPU_FPU;
 439                 c->tlbsize = 64;
 440                 break;
 441         case PRID_IMP_R4000:
 442                 if (read_c0_config() & CONF_SC) {
 443                         if ((c->processor_id & PRID_REV_MASK) >=
 444                             PRID_REV_R4400) {
 445                                 c->cputype = CPU_R4400PC;
 446                                 __cpu_name[cpu] = "R4400PC";
 447                         } else {
 448                                 c->cputype = CPU_R4000PC;
 449                                 __cpu_name[cpu] = "R4000PC";
 450                         }
 451                 } else {
 452                         int cca = read_c0_config() & CONF_CM_CMASK;
 453                         int mc;
 454
 455                         /*
 456                          * SC and MC versions can't be reliably told apart,
 457                          * but only the latter support coherent caching
 458                          * modes so assume the firmware has set the KSEG0
 459                          * coherency attribute reasonably (if uncached, we
 460                          * assume SC).
 461                          */
 462                         switch (cca) {
 463                         case CONF_CM_CACHABLE_CE:
 464                         case CONF_CM_CACHABLE_COW:
 465                         case CONF_CM_CACHABLE_CUW:
 466                                 mc = 1;
 467                                 break;
 468                         default:
 469                                 mc = 0;
 470                                 break;
 471                         }
 472                         if ((c->processor_id & PRID_REV_MASK) >=
 473                             PRID_REV_R4400) {
 474                                 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
 475                                 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
 476                         } else {
 477                                 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
 478                                 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
 479                         }
 480                 }
 481
 482                 set_isa(c, MIPS_CPU_ISA_III);
 483                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 484                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 485                              MIPS_CPU_LLSC;
 486                 c->tlbsize = 48;
 487                 break;
 488         case PRID_IMP_VR41XX:
 489                 set_isa(c, MIPS_CPU_ISA_III);
 490                 c->options = R4K_OPTS;
 491                 c->tlbsize = 32;
 492                 switch (c->processor_id & 0xf0) {
 493                 case PRID_REV_VR4111:
 494                         c->cputype = CPU_VR4111;
 495                         __cpu_name[cpu] = "NEC VR4111";
 496                         break;
 497                 case PRID_REV_VR4121:
 498                         c->cputype = CPU_VR4121;
 499                         __cpu_name[cpu] = "NEC VR4121";
 500                         break;
 501                 case PRID_REV_VR4122:
 502                         if ((c->processor_id & 0xf) < 0x3) {
 503                                 c->cputype = CPU_VR4122;
 504                                 __cpu_name[cpu] = "NEC VR4122";
 505                         } else {
 506                                 c->cputype = CPU_VR4181A;
 507                                 __cpu_name[cpu] = "NEC VR4181A";
 508                         }
 509                         break;
 510                 case PRID_REV_VR4130:
 511                         if ((c->processor_id & 0xf) < 0x4) {
 512                                 c->cputype = CPU_VR4131;
 513                                 __cpu_name[cpu] = "NEC VR4131";
 514                         } else {
 515                                 c->cputype = CPU_VR4133;
 516                                 c->options |= MIPS_CPU_LLSC;
 517                                 __cpu_name[cpu] = "NEC VR4133";
 518                         }
 519                         break;
 520                 default:
 521                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 522                         c->cputype = CPU_VR41XX;
 523                         __cpu_name[cpu] = "NEC Vr41xx";
 524                         break;
 525                 }
 526                 break;
 527         case PRID_IMP_R4300:
 528                 c->cputype = CPU_R4300;
 529                 __cpu_name[cpu] = "R4300";
 530                 set_isa(c, MIPS_CPU_ISA_III);
 531                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 532                              MIPS_CPU_LLSC;
 533                 c->tlbsize = 32;
 534                 break;
 535         case PRID_IMP_R4600:
 536                 c->cputype = CPU_R4600;
 537                 __cpu_name[cpu] = "R4600";
 538                 set_isa(c, MIPS_CPU_ISA_III);
 539                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 540                              MIPS_CPU_LLSC;
 541                 c->tlbsize = 48;
 542                 break;
 543         #if 0
 544         case PRID_IMP_R4650:
 545                 /*
 546                  * This processor doesn't have an MMU, so it's not
 547                  * "real easy" to run Linux on it. It is left purely
 548                  * for documentation.  Commented out because it shares
 549                  * it's c0_prid id number with the TX3900.
 550                  */
 551                 c->cputype = CPU_R4650;
 552                 __cpu_name[cpu] = "R4650";
 553                 set_isa(c, MIPS_CPU_ISA_III);
 554                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 555                 c->tlbsize = 48;
 556                 break;
 557         #endif
 558         case PRID_IMP_TX39:
 559                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 560
 561                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 562                         c->cputype = CPU_TX3927;
 563                         __cpu_name[cpu] = "TX3927";
 564                         c->tlbsize = 64;
 565                 } else {
 566                         switch (c->processor_id & PRID_REV_MASK) {
 567                         case PRID_REV_TX3912:
 568                                 c->cputype = CPU_TX3912;
 569                                 __cpu_name[cpu] = "TX3912";
 570                                 c->tlbsize = 32;
 571                                 break;
 572                         case PRID_REV_TX3922:
 573                                 c->cputype = CPU_TX3922;
 574                                 __cpu_name[cpu] = "TX3922";
 575                                 c->tlbsize = 64;
 576                                 break;
 577                         }
 578                 }
 579                 break;
 580         case PRID_IMP_R4700:
 581                 c->cputype = CPU_R4700;
 582                 __cpu_name[cpu] = "R4700";
 583                 set_isa(c, MIPS_CPU_ISA_III);
 584                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 585                              MIPS_CPU_LLSC;
 586                 c->tlbsize = 48;
 587                 break;
 588         case PRID_IMP_TX49:
 589                 c->cputype = CPU_TX49XX;
 590                 __cpu_name[cpu] = "R49XX";
 591                 set_isa(c, MIPS_CPU_ISA_III);
 592                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 593                 if (!(c->processor_id & 0x08))
 594                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 595                 c->tlbsize = 48;
 596                 break;
 597         case PRID_IMP_R5000:
 598                 c->cputype = CPU_R5000;
 599                 __cpu_name[cpu] = "R5000";
 600                 set_isa(c, MIPS_CPU_ISA_IV);
 601                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 602                              MIPS_CPU_LLSC;
 603                 c->tlbsize = 48;
 604                 break;
 605         case PRID_IMP_R5432:
 606                 c->cputype = CPU_R5432;
 607                 __cpu_name[cpu] = "R5432";
 608                 set_isa(c, MIPS_CPU_ISA_IV);
 609                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 610                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 611                 c->tlbsize = 48;
 612                 break;
 613         case PRID_IMP_R5500:
 614                 c->cputype = CPU_R5500;
 615                 __cpu_name[cpu] = "R5500";
 616                 set_isa(c, MIPS_CPU_ISA_IV);
 617                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 618                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 619                 c->tlbsize = 48;
 620                 break;
 621         case PRID_IMP_NEVADA:
 622                 c->cputype = CPU_NEVADA;
 623                 __cpu_name[cpu] = "Nevada";
 624                 set_isa(c, MIPS_CPU_ISA_IV);
 625                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 626                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 627                 c->tlbsize = 48;
 628                 break;
 629         case PRID_IMP_R6000:
 630                 c->cputype = CPU_R6000;
 631                 __cpu_name[cpu] = "R6000";
 632                 set_isa(c, MIPS_CPU_ISA_II);
 633                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 634                              MIPS_CPU_LLSC;
 635                 c->tlbsize = 32;
 636                 break;
 637         case PRID_IMP_R6000A:
 638                 c->cputype = CPU_R6000A;
 639                 __cpu_name[cpu] = "R6000A";
 640                 set_isa(c, MIPS_CPU_ISA_II);
 641                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 642                              MIPS_CPU_LLSC;
 643                 c->tlbsize = 32;
 644                 break;
 645         case PRID_IMP_RM7000:
 646                 c->cputype = CPU_RM7000;
 647                 __cpu_name[cpu] = "RM7000";
 648                 set_isa(c, MIPS_CPU_ISA_IV);
 649                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 650                              MIPS_CPU_LLSC;
 651                 /*
 652                  * Undocumented RM7000:  Bit 29 in the info register of
 653                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 654                  * entries.
 655                  *
 656                  * 29      1 =>    64 entry JTLB
 657                  *         0 =>    48 entry JTLB
 658                  */
 659                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 660                 break;
 661         case PRID_IMP_RM9000:
 662                 c->cputype = CPU_RM9000;
 663                 __cpu_name[cpu] = "RM9000";
 664                 set_isa(c, MIPS_CPU_ISA_IV);
 665                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 666                              MIPS_CPU_LLSC;
 667                 /*
 668                  * Bit 29 in the info register of the RM9000
 669                  * indicates if the TLB has 48 or 64 entries.
 670                  *
 671                  * 29      1 =>    64 entry JTLB
 672                  *         0 =>    48 entry JTLB
 673                  */
 674                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 675                 break;
 676         case PRID_IMP_R8000:
 677                 c->cputype = CPU_R8000;
 678                 __cpu_name[cpu] = "RM8000";
 679                 set_isa(c, MIPS_CPU_ISA_IV);
 680                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 681                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 682                              MIPS_CPU_LLSC;
 683                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 684                 break;
 685         case PRID_IMP_R10000:
 686                 c->cputype = CPU_R10000;
 687                 __cpu_name[cpu] = "R10000";
 688                 set_isa(c, MIPS_CPU_ISA_IV);
 689                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 690                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 691                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 692                              MIPS_CPU_LLSC;
 693                 c->tlbsize = 64;
 694                 break;
 695         case PRID_IMP_R12000:
 696                 c->cputype = CPU_R12000;
 697                 __cpu_name[cpu] = "R12000";
 698                 set_isa(c, MIPS_CPU_ISA_IV);
 699                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 700                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 701                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 702                              MIPS_CPU_LLSC;
 703                 c->tlbsize = 64;
 704                 break;
 705         case PRID_IMP_R14000:
 706                 c->cputype = CPU_R14000;
 707                 __cpu_name[cpu] = "R14000";
 708                 set_isa(c, MIPS_CPU_ISA_IV);
 709                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 710                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 711                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 712                              MIPS_CPU_LLSC;
 713                 c->tlbsize = 64;
 714                 break;
 715         case PRID_IMP_LOONGSON2:
 716                 c->cputype = CPU_LOONGSON2;
 717                 __cpu_name[cpu] = "ICT Loongson-2";
 718
 719                 switch (c->processor_id & PRID_REV_MASK) {
 720                 case PRID_REV_LOONGSON2E:
 721                         set_elf_platform(cpu, "loongson2e");
 722                         break;
 723                 case PRID_REV_LOONGSON2F:
 724                         set_elf_platform(cpu, "loongson2f");
 725                         break;
 726                 }
 727
 728                 set_isa(c, MIPS_CPU_ISA_III);
 729                 c->options = R4K_OPTS |
 730                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 731                              MIPS_CPU_32FPR;
 732                 c->tlbsize = 64;
 733                 break;
 734         case PRID_IMP_LOONGSON1:
 735                 decode_configs(c);
 736
 737                 c->cputype = CPU_LOONGSON1;
 738
 739                 switch (c->processor_id & PRID_REV_MASK) {
 740                 case PRID_REV_LOONGSON1B:
 741                         __cpu_name[cpu] = "Loongson 1B";
 742                         break;
 743                 }
 744
 745                 break;
 746         }
 747 }
 748
 749 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 750 {
 751         switch (c->processor_id & PRID_IMP_MASK) {
 752         case PRID_IMP_4KC:
 753                 c->cputype = CPU_4KC;
 754                 __cpu_name[cpu] = "MIPS 4Kc";
 755                 break;
 756         case PRID_IMP_4KEC:
 757         case PRID_IMP_4KECR2:
 758                 c->cputype = CPU_4KEC;
 759                 __cpu_name[cpu] = "MIPS 4KEc";
 760                 break;
 761         case PRID_IMP_4KSC:
 762         case PRID_IMP_4KSD:
 763                 c->cputype = CPU_4KSC;
 764                 __cpu_name[cpu] = "MIPS 4KSc";
 765                 break;
 766         case PRID_IMP_5KC:
 767                 c->cputype = CPU_5KC;
 768                 __cpu_name[cpu] = "MIPS 5Kc";
 769                 break;
 770         case PRID_IMP_5KE:
 771                 c->cputype = CPU_5KE;
 772                 __cpu_name[cpu] = "MIPS 5KE";
 773                 break;
 774         case PRID_IMP_20KC:
 775                 c->cputype = CPU_20KC;
 776                 __cpu_name[cpu] = "MIPS 20Kc";
 777                 break;
 778         case PRID_IMP_24K:
 779                 c->cputype = CPU_24K;
 780                 __cpu_name[cpu] = "MIPS 24Kc";
 781                 break;
 782         case PRID_IMP_24KE:
 783                 c->cputype = CPU_24K;
 784                 __cpu_name[cpu] = "MIPS 24KEc";
 785                 break;
 786         case PRID_IMP_25KF:
 787                 c->cputype = CPU_25KF;
 788                 __cpu_name[cpu] = "MIPS 25Kc";
 789                 break;
 790         case PRID_IMP_34K:
 791                 c->cputype = CPU_34K;
 792                 __cpu_name[cpu] = "MIPS 34Kc";
 793                 break;
 794         case PRID_IMP_74K:
 795                 c->cputype = CPU_74K;
 796                 __cpu_name[cpu] = "MIPS 74Kc";
 797                 break;
 798         case PRID_IMP_M14KC:
 799                 c->cputype = CPU_M14KC;
 800                 __cpu_name[cpu] = "MIPS M14Kc";
 801                 break;
 802         case PRID_IMP_M14KEC:
 803                 c->cputype = CPU_M14KEC;
 804                 __cpu_name[cpu] = "MIPS M14KEc";
 805                 break;
 806         case PRID_IMP_1004K:
 807                 c->cputype = CPU_1004K;
 808                 __cpu_name[cpu] = "MIPS 1004Kc";
 809                 break;
 810         case PRID_IMP_1074K:
 811                 c->cputype = CPU_1074K;
 812                 __cpu_name[cpu] = "MIPS 1074Kc";
 813                 break;
 814         case PRID_IMP_INTERAPTIV_UP:
 815                 c->cputype = CPU_INTERAPTIV;
 816                 __cpu_name[cpu] = "MIPS interAptiv";
 817                 break;
 818         case PRID_IMP_INTERAPTIV_MP:
 819                 c->cputype = CPU_INTERAPTIV;
 820                 __cpu_name[cpu] = "MIPS interAptiv (multi)";
 821                 break;
 822         case PRID_IMP_PROAPTIV_UP:
 823                 c->cputype = CPU_PROAPTIV;
 824                 __cpu_name[cpu] = "MIPS proAptiv";
 825                 break;
 826         case PRID_IMP_PROAPTIV_MP:
 827                 c->cputype = CPU_PROAPTIV;
 828                 __cpu_name[cpu] = "MIPS proAptiv (multi)";
 829                 break;
 830         }
 831
 832         decode_configs(c);
 833
 834         spram_config();
 835 }
 836
 837 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 838 {
 839         decode_configs(c);
 840         switch (c->processor_id & PRID_IMP_MASK) {
 841         case PRID_IMP_AU1_REV1:
 842         case PRID_IMP_AU1_REV2:
 843                 c->cputype = CPU_ALCHEMY;
 844                 switch ((c->processor_id >> 24) & 0xff) {
 845                 case 0:
 846                         __cpu_name[cpu] = "Au1000";
 847                         break;
 848                 case 1:
 849                         __cpu_name[cpu] = "Au1500";
 850                         break;
 851                 case 2:
 852                         __cpu_name[cpu] = "Au1100";
 853                         break;
 854                 case 3:
 855                         __cpu_name[cpu] = "Au1550";
 856                         break;
 857                 case 4:
 858                         __cpu_name[cpu] = "Au1200";
 859                         if ((c->processor_id & PRID_REV_MASK) == 2)
 860                                 __cpu_name[cpu] = "Au1250";
 861                         break;
 862                 case 5:
 863                         __cpu_name[cpu] = "Au1210";
 864                         break;
 865                 default:
 866                         __cpu_name[cpu] = "Au1xxx";
 867                         break;
 868                 }
 869                 break;
 870         }
 871 }
 872
 873 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 874 {
 875         decode_configs(c);
 876
 877         switch (c->processor_id & PRID_IMP_MASK) {
 878         case PRID_IMP_SB1:
 879                 c->cputype = CPU_SB1;
 880                 __cpu_name[cpu] = "SiByte SB1";
 881                 /* FPU in pass1 is known to have issues. */
 882                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
 883                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 884                 break;
 885         case PRID_IMP_SB1A:
 886                 c->cputype = CPU_SB1A;
 887                 __cpu_name[cpu] = "SiByte SB1A";
 888                 break;
 889         }
 890 }
 891
 892 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 893 {
 894         decode_configs(c);
 895         switch (c->processor_id & PRID_IMP_MASK) {
 896         case PRID_IMP_SR71000:
 897                 c->cputype = CPU_SR71000;
 898                 __cpu_name[cpu] = "Sandcraft SR71000";
 899                 c->scache.ways = 8;
 900                 c->tlbsize = 64;
 901                 break;
 902         }
 903 }
 904
 905 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 906 {
 907         decode_configs(c);
 908         switch (c->processor_id & PRID_IMP_MASK) {
 909         case PRID_IMP_PR4450:
 910                 c->cputype = CPU_PR4450;
 911                 __cpu_name[cpu] = "Philips PR4450";
 912                 set_isa(c, MIPS_CPU_ISA_M32R1);
 913                 break;
 914         }
 915 }
 916
 917 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 918 {
 919         decode_configs(c);
 920         switch (c->processor_id & PRID_IMP_MASK) {
 921         case PRID_IMP_BMIPS32_REV4:
 922         case PRID_IMP_BMIPS32_REV8:
 923                 c->cputype = CPU_BMIPS32;
 924                 __cpu_name[cpu] = "Broadcom BMIPS32";
 925                 set_elf_platform(cpu, "bmips32");
 926                 break;
 927         case PRID_IMP_BMIPS3300:
 928         case PRID_IMP_BMIPS3300_ALT:
 929         case PRID_IMP_BMIPS3300_BUG:
 930                 c->cputype = CPU_BMIPS3300;
 931                 __cpu_name[cpu] = "Broadcom BMIPS3300";
 932                 set_elf_platform(cpu, "bmips3300");
 933                 break;
 934         case PRID_IMP_BMIPS43XX: {
 935                 int rev = c->processor_id & PRID_REV_MASK;
 936
 937                 if (rev >= PRID_REV_BMIPS4380_LO &&
 938                                 rev <= PRID_REV_BMIPS4380_HI) {
 939                         c->cputype = CPU_BMIPS4380;
 940                         __cpu_name[cpu] = "Broadcom BMIPS4380";
 941                         set_elf_platform(cpu, "bmips4380");
 942                 } else {
 943                         c->cputype = CPU_BMIPS4350;
 944                         __cpu_name[cpu] = "Broadcom BMIPS4350";
 945                         set_elf_platform(cpu, "bmips4350");
 946                 }
 947                 break;
 948         }
 949         case PRID_IMP_BMIPS5000:
 950                 c->cputype = CPU_BMIPS5000;
 951                 __cpu_name[cpu] = "Broadcom BMIPS5000";
 952                 set_elf_platform(cpu, "bmips5000");
 953                 c->options |= MIPS_CPU_ULRI;
 954                 break;
 955         }
 956 }
 957
 958 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 959 {
 960         decode_configs(c);
 961         switch (c->processor_id & PRID_IMP_MASK) {
 962         case PRID_IMP_CAVIUM_CN38XX:
 963         case PRID_IMP_CAVIUM_CN31XX:
 964         case PRID_IMP_CAVIUM_CN30XX:
 965                 c->cputype = CPU_CAVIUM_OCTEON;
 966                 __cpu_name[cpu] = "Cavium Octeon";
 967                 goto platform;
 968         case PRID_IMP_CAVIUM_CN58XX:
 969         case PRID_IMP_CAVIUM_CN56XX:
 970         case PRID_IMP_CAVIUM_CN50XX:
 971         case PRID_IMP_CAVIUM_CN52XX:
 972                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
 973                 __cpu_name[cpu] = "Cavium Octeon+";
 974 platform:
 975                 set_elf_platform(cpu, "octeon");
 976                 break;
 977         case PRID_IMP_CAVIUM_CN61XX:
 978         case PRID_IMP_CAVIUM_CN63XX:
 979         case PRID_IMP_CAVIUM_CN66XX:
 980         case PRID_IMP_CAVIUM_CN68XX:
 981         case PRID_IMP_CAVIUM_CNF71XX:
 982                 c->cputype = CPU_CAVIUM_OCTEON2;
 983                 __cpu_name[cpu] = "Cavium Octeon II";
 984                 set_elf_platform(cpu, "octeon2");
 985                 break;
 986         case PRID_IMP_CAVIUM_CN70XX:
 987         case PRID_IMP_CAVIUM_CN78XX:
 988                 c->cputype = CPU_CAVIUM_OCTEON3;
 989                 __cpu_name[cpu] = "Cavium Octeon III";
 990                 set_elf_platform(cpu, "octeon3");
 991                 break;
 992         default:
 993                 printk(KERN_INFO "Unknown Octeon chip!\n");
 994                 c->cputype = CPU_UNKNOWN;
 995                 break;
 996         }
 997 }
 998
 999 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1000 {
1001         decode_configs(c);
1002         /* JZRISC does not implement the CP0 counter. */
1003         c->options &= ~MIPS_CPU_COUNTER;
1004         switch (c->processor_id & PRID_IMP_MASK) {
1005         case PRID_IMP_JZRISC:
1006                 c->cputype = CPU_JZRISC;
1007                 __cpu_name[cpu] = "Ingenic JZRISC";
1008                 break;
1009         default:
1010                 panic("Unknown Ingenic Processor ID!");
1011                 break;
1012         }
1013 }
1014
1015 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1016 {
1017         decode_configs(c);
1018
1019         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1020                 c->cputype = CPU_ALCHEMY;
1021                 __cpu_name[cpu] = "Au1300";
1022                 /* following stuff is not for Alchemy */
1023                 return;
1024         }
1025
1026         c->options = (MIPS_CPU_TLB       |
1027                         MIPS_CPU_4KEX    |
1028                         MIPS_CPU_COUNTER |
1029                         MIPS_CPU_DIVEC   |
1030                         MIPS_CPU_WATCH   |
1031                         MIPS_CPU_EJTAG   |
1032                         MIPS_CPU_LLSC);
1033
1034         switch (c->processor_id & PRID_IMP_MASK) {
1035         case PRID_IMP_NETLOGIC_XLP2XX:
1036         case PRID_IMP_NETLOGIC_XLP9XX:
1037                 c->cputype = CPU_XLP;
1038                 __cpu_name[cpu] = "Broadcom XLPII";
1039                 break;
1040
1041         case PRID_IMP_NETLOGIC_XLP8XX:
1042         case PRID_IMP_NETLOGIC_XLP3XX:
1043                 c->cputype = CPU_XLP;
1044                 __cpu_name[cpu] = "Netlogic XLP";
1045                 break;
1046
1047         case PRID_IMP_NETLOGIC_XLR732:
1048         case PRID_IMP_NETLOGIC_XLR716:
1049         case PRID_IMP_NETLOGIC_XLR532:
1050         case PRID_IMP_NETLOGIC_XLR308:
1051         case PRID_IMP_NETLOGIC_XLR532C:
1052         case PRID_IMP_NETLOGIC_XLR516C:
1053         case PRID_IMP_NETLOGIC_XLR508C:
1054         case PRID_IMP_NETLOGIC_XLR308C:
1055                 c->cputype = CPU_XLR;
1056                 __cpu_name[cpu] = "Netlogic XLR";
1057                 break;
1058
1059         case PRID_IMP_NETLOGIC_XLS608:
1060         case PRID_IMP_NETLOGIC_XLS408:
1061         case PRID_IMP_NETLOGIC_XLS404:
1062         case PRID_IMP_NETLOGIC_XLS208:
1063         case PRID_IMP_NETLOGIC_XLS204:
1064         case PRID_IMP_NETLOGIC_XLS108:
1065         case PRID_IMP_NETLOGIC_XLS104:
1066         case PRID_IMP_NETLOGIC_XLS616B:
1067         case PRID_IMP_NETLOGIC_XLS608B:
1068         case PRID_IMP_NETLOGIC_XLS416B:
1069         case PRID_IMP_NETLOGIC_XLS412B:
1070         case PRID_IMP_NETLOGIC_XLS408B:
1071         case PRID_IMP_NETLOGIC_XLS404B:
1072                 c->cputype = CPU_XLR;
1073                 __cpu_name[cpu] = "Netlogic XLS";
1074                 break;
1075
1076         default:
1077                 pr_info("Unknown Netlogic chip id [%02x]!\n",
1078                        c->processor_id);
1079                 c->cputype = CPU_XLR;
1080                 break;
1081         }
1082
1083         if (c->cputype == CPU_XLP) {
1084                 set_isa(c, MIPS_CPU_ISA_M64R2);
1085                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1086                 /* This will be updated again after all threads are woken up */
1087                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1088         } else {
1089                 set_isa(c, MIPS_CPU_ISA_M64R1);
1090                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1091         }
1092         c->kscratch_mask = 0xf;
1093 }
1094
1095 #ifdef CONFIG_64BIT
1096 /* For use by uaccess.h */
1097 u64 __ua_limit;
1098 EXPORT_SYMBOL(__ua_limit);
1099 #endif
1100
1101 const char *__cpu_name[NR_CPUS];
1102 const char *__elf_platform;
1103
1104 void cpu_probe(void)
1105 {
1106         struct cpuinfo_mips *c = &current_cpu_data;
1107         unsigned int cpu = smp_processor_id();
1108
1109         c->processor_id = PRID_IMP_UNKNOWN;
1110         c->fpu_id       = FPIR_IMP_NONE;
1111         c->cputype      = CPU_UNKNOWN;
1112
1113         c->processor_id = read_c0_prid();
1114         switch (c->processor_id & PRID_COMP_MASK) {
1115         case PRID_COMP_LEGACY:
1116                 cpu_probe_legacy(c, cpu);
1117                 break;
1118         case PRID_COMP_MIPS:
1119                 cpu_probe_mips(c, cpu);
1120                 break;
1121         case PRID_COMP_ALCHEMY:
1122                 cpu_probe_alchemy(c, cpu);
1123                 break;
1124         case PRID_COMP_SIBYTE:
1125                 cpu_probe_sibyte(c, cpu);
1126                 break;
1127         case PRID_COMP_BROADCOM:
1128                 cpu_probe_broadcom(c, cpu);
1129                 break;
1130         case PRID_COMP_SANDCRAFT:
1131                 cpu_probe_sandcraft(c, cpu);
1132                 break;
1133         case PRID_COMP_NXP:
1134                 cpu_probe_nxp(c, cpu);
1135                 break;
1136         case PRID_COMP_CAVIUM:
1137                 cpu_probe_cavium(c, cpu);
1138                 break;
1139         case PRID_COMP_INGENIC:
1140                 cpu_probe_ingenic(c, cpu);
1141                 break;
1142         case PRID_COMP_NETLOGIC:
1143                 cpu_probe_netlogic(c, cpu);
1144                 break;
1145         }
1146
1147         BUG_ON(!__cpu_name[cpu]);
1148         BUG_ON(c->cputype == CPU_UNKNOWN);
1149
1150         /*
1151          * Platform code can force the cpu type to optimize code
1152          * generation. In that case be sure the cpu type is correctly
1153          * manually setup otherwise it could trigger some nasty bugs.
1154          */
1155         BUG_ON(current_cpu_type() != c->cputype);
1156
1157         if (mips_fpu_disabled)
1158                 c->options &= ~MIPS_CPU_FPU;
1159
1160         if (mips_dsp_disabled)
1161                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1162
1163         if (c->options & MIPS_CPU_FPU) {
1164                 c->fpu_id = cpu_get_fpu_id();
1165
1166                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1167                                     MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1168                         if (c->fpu_id & MIPS_FPIR_3D)
1169                                 c->ases |= MIPS_ASE_MIPS3D;
1170                 }
1171         }
1172
1173         if (cpu_has_mips_r2) {
1174                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1175                 /* R2 has Performance Counter Interrupt indicator */
1176                 c->options |= MIPS_CPU_PCI;
1177         }
1178         else
1179                 c->srsets = 1;
1180
1181         cpu_probe_vmbits(c);
1182
1183 #ifdef CONFIG_64BIT
1184         if (cpu == 0)
1185                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1186 #endif
1187 }
1188
1189 void cpu_report(void)
1190 {
1191         struct cpuinfo_mips *c = &current_cpu_data;
1192
1193         pr_info("CPU%d revision is: %08x (%s)\n",
1194                 smp_processor_id(), c->processor_id, cpu_name_string());
1195         if (c->options & MIPS_CPU_FPU)
1196                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1197 }