2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/module.h>
24 #include <asm/mipsregs.h>
25 #include <asm/system.h>
26 #include <asm/watch.h>
27 #include <asm/spram.h>
29 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
30 * the implementation of the "wait" feature differs between CPU families. This
31 * points to the function that implements CPU specific wait.
32 * The wait instruction stops the pipeline and reduces the power consumption of
35 void (*cpu_wait)(void);
36 EXPORT_SYMBOL(cpu_wait);
38 static void r3081_wait(void)
40 unsigned long cfg = read_c0_conf();
41 write_c0_conf(cfg | R30XX_CONF_HALT);
44 static void r39xx_wait(void)
48 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
52 extern void r4k_wait(void);
55 * This variant is preferable as it allows testing need_resched and going to
56 * sleep depending on the outcome atomically. Unfortunately the "It is
57 * implementation-dependent whether the pipeline restarts when a non-enabled
58 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
59 * using this version a gamble.
61 void r4k_wait_irqoff(void)
65 __asm__(" .set push \n"
70 __asm__(" .globl __pastwait \n"
76 * The RM7000 variant has to handle erratum 38. The workaround is to not
77 * have any pending stores when the WAIT instruction is executed.
79 static void rm7k_wait_irqoff(void)
89 " mtc0 $1, $12 # stalls until W stage \n"
91 " mtc0 $1, $12 # stalls until W stage \n"
97 * The Au1xxx wait is available only if using 32khz counter or
98 * external timer source, but specifically not CP0 Counter.
99 * alchemy/common/time.c may override cpu_wait!
101 static void au1k_wait(void)
103 __asm__(" .set mips3 \n"
104 " cache 0x14, 0(%0) \n"
105 " cache 0x14, 32(%0) \n"
114 : : "r" (au1k_wait));
117 static int __initdata nowait;
119 static int __init wait_disable(char *s)
126 __setup("nowait", wait_disable);
128 static int __cpuinitdata mips_fpu_disabled;
130 static int __init fpu_disable(char *s)
132 cpu_data[0].options &= ~MIPS_CPU_FPU;
133 mips_fpu_disabled = 1;
138 __setup("nofpu", fpu_disable);
140 int __cpuinitdata mips_dsp_disabled;
142 static int __init dsp_disable(char *s)
144 cpu_data[0].ases &= ~MIPS_ASE_DSP;
145 mips_dsp_disabled = 1;
150 __setup("nodsp", dsp_disable);
152 void __init check_wait(void)
154 struct cpuinfo_mips *c = ¤t_cpu_data;
157 printk("Wait instruction disabled.\n");
161 switch (c->cputype) {
164 cpu_wait = r3081_wait;
167 cpu_wait = r39xx_wait;
170 /* case CPU_R4300: */
188 case CPU_CAVIUM_OCTEON:
189 case CPU_CAVIUM_OCTEON_PLUS:
195 cpu_wait = rm7k_wait_irqoff;
202 if (read_c0_config7() & MIPS_CONF7_WII)
203 cpu_wait = r4k_wait_irqoff;
208 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
209 cpu_wait = r4k_wait_irqoff;
213 cpu_wait = r4k_wait_irqoff;
216 cpu_wait = au1k_wait;
220 * WAIT on Rev1.0 has E1, E2, E3 and E16.
221 * WAIT on Rev2.0 and Rev3.0 has E16.
222 * Rev3.1 WAIT is nop, why bother
224 if ((c->processor_id & 0xff) <= 0x64)
228 * Another rev is incremeting c0_count at a reduced clock
229 * rate while in WAIT mode. So we basically have the choice
230 * between using the cp0 timer as clocksource or avoiding
231 * the WAIT instruction. Until more details are known,
232 * disable the use of WAIT for 20Kc entirely.
237 if ((c->processor_id & 0x00ff) >= 0x40)
245 static inline void check_errata(void)
247 struct cpuinfo_mips *c = ¤t_cpu_data;
249 switch (c->cputype) {
252 * Erratum "RPS May Cause Incorrect Instruction Execution"
253 * This code only handles VPE0, any SMP/SMTC/RTOS code
254 * making use of VPE1 will be responsable for that VPE.
256 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
257 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
264 void __init check_bugs32(void)
270 * Probe whether cpu has config register by trying to play with
271 * alternate cache bit and see whether it matters.
272 * It's used by cpu_probe to distinguish between R3000A and R3081.
274 static inline int cpu_has_confreg(void)
276 #ifdef CONFIG_CPU_R3000
277 extern unsigned long r3k_cache_size(unsigned long);
278 unsigned long size1, size2;
279 unsigned long cfg = read_c0_conf();
281 size1 = r3k_cache_size(ST0_ISC);
282 write_c0_conf(cfg ^ R30XX_CONF_AC);
283 size2 = r3k_cache_size(ST0_ISC);
285 return size1 != size2;
292 * Get the FPU Implementation/Revision.
294 static inline unsigned long cpu_get_fpu_id(void)
296 unsigned long tmp, fpu_id;
298 tmp = read_c0_status();
300 fpu_id = read_32bit_cp1_register(CP1_REVISION);
301 write_c0_status(tmp);
306 * Check the CPU has an FPU the official way.
308 static inline int __cpu_has_fpu(void)
310 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
313 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
315 #ifdef __NEED_VMBITS_PROBE
316 write_c0_entryhi(0x3fffffffffffe000ULL);
317 back_to_back_c0_hazard();
318 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
322 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
325 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
327 switch (c->processor_id & 0xff00) {
329 c->cputype = CPU_R2000;
330 __cpu_name[cpu] = "R2000";
331 c->isa_level = MIPS_CPU_ISA_I;
332 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
335 c->options |= MIPS_CPU_FPU;
339 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
340 if (cpu_has_confreg()) {
341 c->cputype = CPU_R3081E;
342 __cpu_name[cpu] = "R3081";
344 c->cputype = CPU_R3000A;
345 __cpu_name[cpu] = "R3000A";
349 c->cputype = CPU_R3000;
350 __cpu_name[cpu] = "R3000";
352 c->isa_level = MIPS_CPU_ISA_I;
353 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
356 c->options |= MIPS_CPU_FPU;
360 if (read_c0_config() & CONF_SC) {
361 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
362 c->cputype = CPU_R4400PC;
363 __cpu_name[cpu] = "R4400PC";
365 c->cputype = CPU_R4000PC;
366 __cpu_name[cpu] = "R4000PC";
369 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
370 c->cputype = CPU_R4400SC;
371 __cpu_name[cpu] = "R4400SC";
373 c->cputype = CPU_R4000SC;
374 __cpu_name[cpu] = "R4000SC";
378 c->isa_level = MIPS_CPU_ISA_III;
379 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
380 MIPS_CPU_WATCH | MIPS_CPU_VCE |
384 case PRID_IMP_VR41XX:
385 switch (c->processor_id & 0xf0) {
386 case PRID_REV_VR4111:
387 c->cputype = CPU_VR4111;
388 __cpu_name[cpu] = "NEC VR4111";
390 case PRID_REV_VR4121:
391 c->cputype = CPU_VR4121;
392 __cpu_name[cpu] = "NEC VR4121";
394 case PRID_REV_VR4122:
395 if ((c->processor_id & 0xf) < 0x3) {
396 c->cputype = CPU_VR4122;
397 __cpu_name[cpu] = "NEC VR4122";
399 c->cputype = CPU_VR4181A;
400 __cpu_name[cpu] = "NEC VR4181A";
403 case PRID_REV_VR4130:
404 if ((c->processor_id & 0xf) < 0x4) {
405 c->cputype = CPU_VR4131;
406 __cpu_name[cpu] = "NEC VR4131";
408 c->cputype = CPU_VR4133;
409 __cpu_name[cpu] = "NEC VR4133";
413 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
414 c->cputype = CPU_VR41XX;
415 __cpu_name[cpu] = "NEC Vr41xx";
418 c->isa_level = MIPS_CPU_ISA_III;
419 c->options = R4K_OPTS;
423 c->cputype = CPU_R4300;
424 __cpu_name[cpu] = "R4300";
425 c->isa_level = MIPS_CPU_ISA_III;
426 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
431 c->cputype = CPU_R4600;
432 __cpu_name[cpu] = "R4600";
433 c->isa_level = MIPS_CPU_ISA_III;
434 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
441 * This processor doesn't have an MMU, so it's not
442 * "real easy" to run Linux on it. It is left purely
443 * for documentation. Commented out because it shares
444 * it's c0_prid id number with the TX3900.
446 c->cputype = CPU_R4650;
447 __cpu_name[cpu] = "R4650";
448 c->isa_level = MIPS_CPU_ISA_III;
449 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
454 c->isa_level = MIPS_CPU_ISA_I;
455 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
457 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
458 c->cputype = CPU_TX3927;
459 __cpu_name[cpu] = "TX3927";
462 switch (c->processor_id & 0xff) {
463 case PRID_REV_TX3912:
464 c->cputype = CPU_TX3912;
465 __cpu_name[cpu] = "TX3912";
468 case PRID_REV_TX3922:
469 c->cputype = CPU_TX3922;
470 __cpu_name[cpu] = "TX3922";
477 c->cputype = CPU_R4700;
478 __cpu_name[cpu] = "R4700";
479 c->isa_level = MIPS_CPU_ISA_III;
480 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
485 c->cputype = CPU_TX49XX;
486 __cpu_name[cpu] = "R49XX";
487 c->isa_level = MIPS_CPU_ISA_III;
488 c->options = R4K_OPTS | MIPS_CPU_LLSC;
489 if (!(c->processor_id & 0x08))
490 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
494 c->cputype = CPU_R5000;
495 __cpu_name[cpu] = "R5000";
496 c->isa_level = MIPS_CPU_ISA_IV;
497 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
502 c->cputype = CPU_R5432;
503 __cpu_name[cpu] = "R5432";
504 c->isa_level = MIPS_CPU_ISA_IV;
505 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
506 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
510 c->cputype = CPU_R5500;
511 __cpu_name[cpu] = "R5500";
512 c->isa_level = MIPS_CPU_ISA_IV;
513 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
514 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
517 case PRID_IMP_NEVADA:
518 c->cputype = CPU_NEVADA;
519 __cpu_name[cpu] = "Nevada";
520 c->isa_level = MIPS_CPU_ISA_IV;
521 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
522 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
526 c->cputype = CPU_R6000;
527 __cpu_name[cpu] = "R6000";
528 c->isa_level = MIPS_CPU_ISA_II;
529 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
533 case PRID_IMP_R6000A:
534 c->cputype = CPU_R6000A;
535 __cpu_name[cpu] = "R6000A";
536 c->isa_level = MIPS_CPU_ISA_II;
537 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
541 case PRID_IMP_RM7000:
542 c->cputype = CPU_RM7000;
543 __cpu_name[cpu] = "RM7000";
544 c->isa_level = MIPS_CPU_ISA_IV;
545 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
548 * Undocumented RM7000: Bit 29 in the info register of
549 * the RM7000 v2.0 indicates if the TLB has 48 or 64
552 * 29 1 => 64 entry JTLB
555 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
557 case PRID_IMP_RM9000:
558 c->cputype = CPU_RM9000;
559 __cpu_name[cpu] = "RM9000";
560 c->isa_level = MIPS_CPU_ISA_IV;
561 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
564 * Bit 29 in the info register of the RM9000
565 * indicates if the TLB has 48 or 64 entries.
567 * 29 1 => 64 entry JTLB
570 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
573 c->cputype = CPU_R8000;
574 __cpu_name[cpu] = "RM8000";
575 c->isa_level = MIPS_CPU_ISA_IV;
576 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
577 MIPS_CPU_FPU | MIPS_CPU_32FPR |
579 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
581 case PRID_IMP_R10000:
582 c->cputype = CPU_R10000;
583 __cpu_name[cpu] = "R10000";
584 c->isa_level = MIPS_CPU_ISA_IV;
585 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
586 MIPS_CPU_FPU | MIPS_CPU_32FPR |
587 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
591 case PRID_IMP_R12000:
592 c->cputype = CPU_R12000;
593 __cpu_name[cpu] = "R12000";
594 c->isa_level = MIPS_CPU_ISA_IV;
595 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
596 MIPS_CPU_FPU | MIPS_CPU_32FPR |
597 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
601 case PRID_IMP_R14000:
602 c->cputype = CPU_R14000;
603 __cpu_name[cpu] = "R14000";
604 c->isa_level = MIPS_CPU_ISA_IV;
605 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
606 MIPS_CPU_FPU | MIPS_CPU_32FPR |
607 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
611 case PRID_IMP_LOONGSON2:
612 c->cputype = CPU_LOONGSON2;
613 __cpu_name[cpu] = "ICT Loongson-2";
614 c->isa_level = MIPS_CPU_ISA_III;
615 c->options = R4K_OPTS |
616 MIPS_CPU_FPU | MIPS_CPU_LLSC |
623 static char unknown_isa[] __cpuinitdata = KERN_ERR \
624 "Unsupported ISA type, c0.config0: %d.";
626 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
628 unsigned int config0;
631 config0 = read_c0_config();
633 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
634 c->options |= MIPS_CPU_TLB;
635 isa = (config0 & MIPS_CONF_AT) >> 13;
638 switch ((config0 & MIPS_CONF_AR) >> 10) {
640 c->isa_level = MIPS_CPU_ISA_M32R1;
643 c->isa_level = MIPS_CPU_ISA_M32R2;
650 switch ((config0 & MIPS_CONF_AR) >> 10) {
652 c->isa_level = MIPS_CPU_ISA_M64R1;
655 c->isa_level = MIPS_CPU_ISA_M64R2;
665 return config0 & MIPS_CONF_M;
668 panic(unknown_isa, config0);
671 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
673 unsigned int config1;
675 config1 = read_c0_config1();
677 if (config1 & MIPS_CONF1_MD)
678 c->ases |= MIPS_ASE_MDMX;
679 if (config1 & MIPS_CONF1_WR)
680 c->options |= MIPS_CPU_WATCH;
681 if (config1 & MIPS_CONF1_CA)
682 c->ases |= MIPS_ASE_MIPS16;
683 if (config1 & MIPS_CONF1_EP)
684 c->options |= MIPS_CPU_EJTAG;
685 if (config1 & MIPS_CONF1_FP) {
686 c->options |= MIPS_CPU_FPU;
687 c->options |= MIPS_CPU_32FPR;
690 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
692 return config1 & MIPS_CONF_M;
695 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
697 unsigned int config2;
699 config2 = read_c0_config2();
701 if (config2 & MIPS_CONF2_SL)
702 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
704 return config2 & MIPS_CONF_M;
707 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
709 unsigned int config3;
711 config3 = read_c0_config3();
713 if (config3 & MIPS_CONF3_SM)
714 c->ases |= MIPS_ASE_SMARTMIPS;
715 if (config3 & MIPS_CONF3_DSP)
716 c->ases |= MIPS_ASE_DSP;
717 if (config3 & MIPS_CONF3_VINT)
718 c->options |= MIPS_CPU_VINT;
719 if (config3 & MIPS_CONF3_VEIC)
720 c->options |= MIPS_CPU_VEIC;
721 if (config3 & MIPS_CONF3_MT)
722 c->ases |= MIPS_ASE_MIPSMT;
723 if (config3 & MIPS_CONF3_ULRI)
724 c->options |= MIPS_CPU_ULRI;
726 return config3 & MIPS_CONF_M;
729 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
731 unsigned int config4;
733 config4 = read_c0_config4();
735 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
737 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
739 return config4 & MIPS_CONF_M;
742 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
746 /* MIPS32 or MIPS64 compliant CPU. */
747 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
748 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
750 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
752 ok = decode_config0(c); /* Read Config registers. */
753 BUG_ON(!ok); /* Arch spec violation! */
755 ok = decode_config1(c);
757 ok = decode_config2(c);
759 ok = decode_config3(c);
761 ok = decode_config4(c);
763 mips_probe_watch_registers(c);
766 c->core = read_c0_ebase() & 0x3ff;
769 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
772 switch (c->processor_id & 0xff00) {
774 c->cputype = CPU_4KC;
775 __cpu_name[cpu] = "MIPS 4Kc";
778 case PRID_IMP_4KECR2:
779 c->cputype = CPU_4KEC;
780 __cpu_name[cpu] = "MIPS 4KEc";
784 c->cputype = CPU_4KSC;
785 __cpu_name[cpu] = "MIPS 4KSc";
788 c->cputype = CPU_5KC;
789 __cpu_name[cpu] = "MIPS 5Kc";
792 c->cputype = CPU_20KC;
793 __cpu_name[cpu] = "MIPS 20Kc";
797 c->cputype = CPU_24K;
798 __cpu_name[cpu] = "MIPS 24Kc";
801 c->cputype = CPU_25KF;
802 __cpu_name[cpu] = "MIPS 25Kc";
805 c->cputype = CPU_34K;
806 __cpu_name[cpu] = "MIPS 34Kc";
809 c->cputype = CPU_74K;
810 __cpu_name[cpu] = "MIPS 74Kc";
813 c->cputype = CPU_1004K;
814 __cpu_name[cpu] = "MIPS 1004Kc";
821 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
824 switch (c->processor_id & 0xff00) {
825 case PRID_IMP_AU1_REV1:
826 case PRID_IMP_AU1_REV2:
827 c->cputype = CPU_ALCHEMY;
828 switch ((c->processor_id >> 24) & 0xff) {
830 __cpu_name[cpu] = "Au1000";
833 __cpu_name[cpu] = "Au1500";
836 __cpu_name[cpu] = "Au1100";
839 __cpu_name[cpu] = "Au1550";
842 __cpu_name[cpu] = "Au1200";
843 if ((c->processor_id & 0xff) == 2)
844 __cpu_name[cpu] = "Au1250";
847 __cpu_name[cpu] = "Au1210";
850 __cpu_name[cpu] = "Au1xxx";
857 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
861 switch (c->processor_id & 0xff00) {
863 c->cputype = CPU_SB1;
864 __cpu_name[cpu] = "SiByte SB1";
865 /* FPU in pass1 is known to have issues. */
866 if ((c->processor_id & 0xff) < 0x02)
867 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
870 c->cputype = CPU_SB1A;
871 __cpu_name[cpu] = "SiByte SB1A";
876 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
879 switch (c->processor_id & 0xff00) {
880 case PRID_IMP_SR71000:
881 c->cputype = CPU_SR71000;
882 __cpu_name[cpu] = "Sandcraft SR71000";
889 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
892 switch (c->processor_id & 0xff00) {
893 case PRID_IMP_PR4450:
894 c->cputype = CPU_PR4450;
895 __cpu_name[cpu] = "Philips PR4450";
896 c->isa_level = MIPS_CPU_ISA_M32R1;
901 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
904 switch (c->processor_id & 0xff00) {
905 case PRID_IMP_BCM3302:
906 /* same as PRID_IMP_BCM6338 */
907 c->cputype = CPU_BCM3302;
908 __cpu_name[cpu] = "Broadcom BCM3302";
910 case PRID_IMP_BCM4710:
911 c->cputype = CPU_BCM4710;
912 __cpu_name[cpu] = "Broadcom BCM4710";
914 case PRID_IMP_BCM6345:
915 c->cputype = CPU_BCM6345;
916 __cpu_name[cpu] = "Broadcom BCM6345";
918 case PRID_IMP_BCM6348:
919 c->cputype = CPU_BCM6348;
920 __cpu_name[cpu] = "Broadcom BCM6348";
922 case PRID_IMP_BCM4350:
923 switch (c->processor_id & 0xf0) {
924 case PRID_REV_BCM6358:
925 c->cputype = CPU_BCM6358;
926 __cpu_name[cpu] = "Broadcom BCM6358";
929 c->cputype = CPU_UNKNOWN;
936 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
939 switch (c->processor_id & 0xff00) {
940 case PRID_IMP_CAVIUM_CN38XX:
941 case PRID_IMP_CAVIUM_CN31XX:
942 case PRID_IMP_CAVIUM_CN30XX:
943 c->cputype = CPU_CAVIUM_OCTEON;
944 __cpu_name[cpu] = "Cavium Octeon";
946 case PRID_IMP_CAVIUM_CN58XX:
947 case PRID_IMP_CAVIUM_CN56XX:
948 case PRID_IMP_CAVIUM_CN50XX:
949 case PRID_IMP_CAVIUM_CN52XX:
950 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
951 __cpu_name[cpu] = "Cavium Octeon+";
954 __elf_platform = "octeon";
957 printk(KERN_INFO "Unknown Octeon chip!\n");
958 c->cputype = CPU_UNKNOWN;
963 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
966 /* JZRISC does not implement the CP0 counter. */
967 c->options &= ~MIPS_CPU_COUNTER;
968 switch (c->processor_id & 0xff00) {
969 case PRID_IMP_JZRISC:
970 c->cputype = CPU_JZRISC;
971 __cpu_name[cpu] = "Ingenic JZRISC";
974 panic("Unknown Ingenic Processor ID!");
979 const char *__cpu_name[NR_CPUS];
980 const char *__elf_platform;
982 __cpuinit void cpu_probe(void)
984 struct cpuinfo_mips *c = ¤t_cpu_data;
985 unsigned int cpu = smp_processor_id();
987 c->processor_id = PRID_IMP_UNKNOWN;
988 c->fpu_id = FPIR_IMP_NONE;
989 c->cputype = CPU_UNKNOWN;
991 c->processor_id = read_c0_prid();
992 switch (c->processor_id & 0xff0000) {
993 case PRID_COMP_LEGACY:
994 cpu_probe_legacy(c, cpu);
997 cpu_probe_mips(c, cpu);
999 case PRID_COMP_ALCHEMY:
1000 cpu_probe_alchemy(c, cpu);
1002 case PRID_COMP_SIBYTE:
1003 cpu_probe_sibyte(c, cpu);
1005 case PRID_COMP_BROADCOM:
1006 cpu_probe_broadcom(c, cpu);
1008 case PRID_COMP_SANDCRAFT:
1009 cpu_probe_sandcraft(c, cpu);
1012 cpu_probe_nxp(c, cpu);
1014 case PRID_COMP_CAVIUM:
1015 cpu_probe_cavium(c, cpu);
1017 case PRID_COMP_INGENIC:
1018 cpu_probe_ingenic(c, cpu);
1022 BUG_ON(!__cpu_name[cpu]);
1023 BUG_ON(c->cputype == CPU_UNKNOWN);
1026 * Platform code can force the cpu type to optimize code
1027 * generation. In that case be sure the cpu type is correctly
1028 * manually setup otherwise it could trigger some nasty bugs.
1030 BUG_ON(current_cpu_type() != c->cputype);
1032 if (mips_fpu_disabled)
1033 c->options &= ~MIPS_CPU_FPU;
1035 if (mips_dsp_disabled)
1036 c->ases &= ~MIPS_ASE_DSP;
1038 if (c->options & MIPS_CPU_FPU) {
1039 c->fpu_id = cpu_get_fpu_id();
1041 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1042 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1043 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1044 c->isa_level == MIPS_CPU_ISA_M64R2) {
1045 if (c->fpu_id & MIPS_FPIR_3D)
1046 c->ases |= MIPS_ASE_MIPS3D;
1050 if (cpu_has_mips_r2)
1051 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1055 cpu_probe_vmbits(c);
1058 __cpuinit void cpu_report(void)
1060 struct cpuinfo_mips *c = ¤t_cpu_data;
1062 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1063 c->processor_id, cpu_name_string());
1064 if (c->options & MIPS_CPU_FPU)
1065 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);