2 * MIPS idle loop and WAIT instruction support.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/export.h>
15 #include <linux/init.h>
16 #include <linux/irqflags.h>
17 #include <linux/printk.h>
18 #include <linux/sched.h>
20 #include <asm/cpu-info.h>
22 #include <asm/mipsregs.h>
25 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
26 * the implementation of the "wait" feature differs between CPU families. This
27 * points to the function that implements CPU specific wait.
28 * The wait instruction stops the pipeline and reduces the power consumption of
31 void (*cpu_wait)(void);
32 EXPORT_SYMBOL(cpu_wait);
34 static void r3081_wait(void)
36 unsigned long cfg = read_c0_conf();
37 write_c0_conf(cfg | R30XX_CONF_HALT);
41 static void r39xx_wait(void)
44 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
55 * This variant is preferable as it allows testing need_resched and going to
56 * sleep depending on the outcome atomically. Unfortunately the "It is
57 * implementation-dependent whether the pipeline restarts when a non-enabled
58 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
59 * using this version a gamble.
61 void r4k_wait_irqoff(void)
71 " .globl __pastwait \n"
76 * The RM7000 variant has to handle erratum 38. The workaround is to not
77 * have any pending stores when the WAIT instruction is executed.
79 static void rm7k_wait_irqoff(void)
88 " mtc0 $1, $12 # stalls until W stage \n"
90 " mtc0 $1, $12 # stalls until W stage \n"
96 * Au1 'wait' is only useful when the 32kHz counter is used as timer,
97 * since coreclock (and the cp0 counter) stops upon executing it. Only an
98 * interrupt can wake it, so they must be enabled before entering idle modes.
100 static void au1k_wait(void)
102 unsigned long c0status = read_c0_status() | 1; /* irqs on */
106 " cache 0x14, 0(%0) \n"
107 " cache 0x14, 32(%0) \n"
109 " mtc0 %1, $12 \n" /* wr c0status */
116 : : "r" (au1k_wait), "r" (c0status));
119 static int __initdata nowait;
121 static int __init wait_disable(char *s)
128 __setup("nowait", wait_disable);
130 void __init check_wait(void)
132 struct cpuinfo_mips *c = ¤t_cpu_data;
135 printk("Wait instruction disabled.\n");
139 switch (c->cputype) {
142 cpu_wait = r3081_wait;
145 cpu_wait = r39xx_wait;
148 /* case CPU_R4300: */
166 case CPU_CAVIUM_OCTEON:
167 case CPU_CAVIUM_OCTEON_PLUS:
168 case CPU_CAVIUM_OCTEON2:
177 cpu_wait = rm7k_wait_irqoff;
186 if (read_c0_config7() & MIPS_CONF7_WII)
187 cpu_wait = r4k_wait_irqoff;
192 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
193 cpu_wait = r4k_wait_irqoff;
197 cpu_wait = r4k_wait_irqoff;
200 cpu_wait = au1k_wait;
204 * WAIT on Rev1.0 has E1, E2, E3 and E16.
205 * WAIT on Rev2.0 and Rev3.0 has E16.
206 * Rev3.1 WAIT is nop, why bother
208 if ((c->processor_id & 0xff) <= 0x64)
212 * Another rev is incremeting c0_count at a reduced clock
213 * rate while in WAIT mode. So we basically have the choice
214 * between using the cp0 timer as clocksource or avoiding
215 * the WAIT instruction. Until more details are known,
216 * disable the use of WAIT for 20Kc entirely.
221 if ((c->processor_id & 0x00ff) >= 0x40)
229 static void smtc_idle_hook(void)
231 #ifdef CONFIG_MIPS_MT_SMTC
232 void smtc_idle_loop_hook(void);
234 smtc_idle_loop_hook();
238 void arch_cpu_idle(void)