2 * MIPS idle loop and WAIT instruction support.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/export.h>
15 #include <linux/init.h>
16 #include <linux/irqflags.h>
17 #include <linux/printk.h>
18 #include <linux/sched.h>
20 #include <asm/cpu-info.h>
21 #include <asm/cpu-type.h>
23 #include <asm/mipsregs.h>
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
27 * the implementation of the "wait" feature differs between CPU families. This
28 * points to the function that implements CPU specific wait.
29 * The wait instruction stops the pipeline and reduces the power consumption of
32 void (*cpu_wait)(void);
33 EXPORT_SYMBOL(cpu_wait);
35 static void r3081_wait(void)
37 unsigned long cfg = read_c0_conf();
38 write_c0_conf(cfg | R30XX_CONF_HALT);
42 static void r39xx_wait(void)
45 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
56 * This variant is preferable as it allows testing need_resched and going to
57 * sleep depending on the outcome atomically. Unfortunately the "It is
58 * implementation-dependent whether the pipeline restarts when a non-enabled
59 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
60 * using this version a gamble.
62 void r4k_wait_irqoff(void)
74 * The RM7000 variant has to handle erratum 38. The workaround is to not
75 * have any pending stores when the WAIT instruction is executed.
77 static void rm7k_wait_irqoff(void)
86 " mtc0 $1, $12 # stalls until W stage \n"
88 " mtc0 $1, $12 # stalls until W stage \n"
94 * Au1 'wait' is only useful when the 32kHz counter is used as timer,
95 * since coreclock (and the cp0 counter) stops upon executing it. Only an
96 * interrupt can wake it, so they must be enabled before entering idle modes.
98 static void au1k_wait(void)
100 unsigned long c0status = read_c0_status() | 1; /* irqs on */
103 " .set arch=r4000 \n"
104 " cache 0x14, 0(%0) \n"
105 " cache 0x14, 32(%0) \n"
107 " mtc0 %1, $12 \n" /* wr c0status */
114 : : "r" (au1k_wait), "r" (c0status));
117 static int __initdata nowait;
119 static int __init wait_disable(char *s)
126 __setup("nowait", wait_disable);
128 void __init check_wait(void)
130 struct cpuinfo_mips *c = ¤t_cpu_data;
133 printk("Wait instruction disabled.\n");
137 switch (current_cpu_type()) {
140 cpu_wait = r3081_wait;
143 cpu_wait = r39xx_wait;
146 /* case CPU_R4300: */
164 case CPU_CAVIUM_OCTEON:
165 case CPU_CAVIUM_OCTEON_PLUS:
166 case CPU_CAVIUM_OCTEON2:
167 case CPU_CAVIUM_OCTEON3:
176 cpu_wait = rm7k_wait_irqoff;
182 * Incoming Fast Debug Channel (FDC) data during a wait
183 * instruction causes the wait never to resume, even if an
184 * interrupt is received. Avoid using wait at all if FDC data is
185 * likely to be received.
187 if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY))
198 case CPU_QEMU_GENERIC:
201 if (read_c0_config7() & MIPS_CONF7_WII)
202 cpu_wait = r4k_wait_irqoff;
207 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
208 cpu_wait = r4k_wait_irqoff;
212 cpu_wait = r4k_wait_irqoff;
215 cpu_wait = au1k_wait;
219 * WAIT on Rev1.0 has E1, E2, E3 and E16.
220 * WAIT on Rev2.0 and Rev3.0 has E16.
221 * Rev3.1 WAIT is nop, why bother
223 if ((c->processor_id & 0xff) <= 0x64)
227 * Another rev is incremeting c0_count at a reduced clock
228 * rate while in WAIT mode. So we basically have the choice
229 * between using the cp0 timer as clocksource or avoiding
230 * the WAIT instruction. Until more details are known,
231 * disable the use of WAIT for 20Kc entirely.
240 void arch_cpu_idle(void)
248 #ifdef CONFIG_CPU_IDLE
250 int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
251 struct cpuidle_driver *drv, int index)