2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <linux/errno.h>
13 #include <asm/mips-cm.h>
14 #include <asm/mipsregs.h>
16 void __iomem *mips_cm_base;
17 void __iomem *mips_cm_l2sync_base;
20 phys_addr_t __mips_cm_phys_base(void)
22 u32 config3 = read_c0_config3();
25 /* Check the CMGCRBase register is implemented */
26 if (!(config3 & MIPS_CONF3_CMGCR))
29 /* Read the address from CMGCRBase */
30 cmgcr = read_c0_cmgcrbase();
31 return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
34 phys_addr_t mips_cm_phys_base(void)
35 __attribute__((weak, alias("__mips_cm_phys_base")));
37 phys_addr_t __mips_cm_l2sync_phys_base(void)
42 * If the L2-only sync region is already enabled then leave it at it's
45 base_reg = read_gcr_l2_only_sync_base();
46 if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK)
47 return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK;
49 /* Default to following the CM */
50 return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
53 phys_addr_t mips_cm_l2sync_phys_base(void)
54 __attribute__((weak, alias("__mips_cm_l2sync_phys_base")));
56 static void mips_cm_probe_l2sync(void)
61 /* L2-only sync was introduced with CM major revision 6 */
62 major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >>
67 /* Find a location for the L2 sync region */
68 addr = mips_cm_l2sync_phys_base();
69 BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK) != addr);
73 /* Set the region base address & enable it */
74 write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK);
77 mips_cm_l2sync_base = ioremap_nocache(addr, MIPS_CM_L2SYNC_SIZE);
80 int mips_cm_probe(void)
86 * No need to probe again if we have already been
92 addr = mips_cm_phys_base();
93 BUG_ON((addr & CM_GCR_BASE_GCRBASE_MSK) != addr);
97 mips_cm_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE);
101 /* sanity check that we're looking at a CM */
102 base_reg = read_gcr_base();
103 if ((base_reg & CM_GCR_BASE_GCRBASE_MSK) != addr) {
104 pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
105 (unsigned long)addr);
110 /* set default target to memory */
111 base_reg &= ~CM_GCR_BASE_CMDEFTGT_MSK;
112 base_reg |= CM_GCR_BASE_CMDEFTGT_MEM;
113 write_gcr_base(base_reg);
115 /* disable CM regions */
116 write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
117 write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
118 write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
119 write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
120 write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
121 write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
122 write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
123 write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
125 /* probe for an L2-only sync region */
126 mips_cm_probe_l2sync();
128 /* determine register width for this CM */
129 mips_cm_is64 = config_enabled(CONFIG_64BIT) && (mips_cm_revision() >= CM_REV_CM3);