2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <linux/errno.h>
13 #include <asm/mips-cm.h>
14 #include <asm/mipsregs.h>
16 void __iomem *mips_cm_base;
17 void __iomem *mips_cm_l2sync_base;
19 phys_addr_t __mips_cm_phys_base(void)
21 u32 config3 = read_c0_config3();
24 /* Check the CMGCRBase register is implemented */
25 if (!(config3 & MIPS_CONF3_CMGCR))
28 /* Read the address from CMGCRBase */
29 cmgcr = read_c0_cmgcrbase();
30 return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
33 phys_addr_t mips_cm_phys_base(void)
34 __attribute__((weak, alias("__mips_cm_phys_base")));
36 phys_addr_t __mips_cm_l2sync_phys_base(void)
41 * If the L2-only sync region is already enabled then leave it at it's
44 base_reg = read_gcr_l2_only_sync_base();
45 if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK)
46 return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK;
48 /* Default to following the CM */
49 return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
52 phys_addr_t mips_cm_l2sync_phys_base(void)
53 __attribute__((weak, alias("__mips_cm_l2sync_phys_base")));
55 static void mips_cm_probe_l2sync(void)
60 /* L2-only sync was introduced with CM major revision 6 */
61 major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >>
66 /* Find a location for the L2 sync region */
67 addr = mips_cm_l2sync_phys_base();
68 BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK) != addr);
72 /* Set the region base address & enable it */
73 write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK);
76 mips_cm_l2sync_base = ioremap_nocache(addr, MIPS_CM_L2SYNC_SIZE);
79 int mips_cm_probe(void)
84 addr = mips_cm_phys_base();
85 BUG_ON((addr & CM_GCR_BASE_GCRBASE_MSK) != addr);
89 mips_cm_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE);
93 /* sanity check that we're looking at a CM */
94 base_reg = read_gcr_base();
95 if ((base_reg & CM_GCR_BASE_GCRBASE_MSK) != addr) {
96 pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
102 /* set default target to memory */
103 base_reg &= ~CM_GCR_BASE_CMDEFTGT_MSK;
104 base_reg |= CM_GCR_BASE_CMDEFTGT_MEM;
105 write_gcr_base(base_reg);
107 /* disable CM regions */
108 write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
109 write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
110 write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
111 write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
112 write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
113 write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
114 write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
115 write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
117 /* probe for an L2-only sync region */
118 mips_cm_probe_l2sync();